[PATCH] riscv: Allow vector constants in riscv_const_insns.

[Robin Dapp <rdapp.gcc@gmail.com>]

Hi,

I figured I'm going to start sending some patches that build on top
of the upcoming RISC-V autovectorization.  This one is obviously
not supposed to be installed before the basic support lands but
it's small enough that it shouldn't hurt to send it now.

This patch allows vector constants in riscv_const_insns in order
for them to be properly recognized as immediate operands such that
we can emit vmv.v.i instructions via autovec.

Bootstrapped and regtested on riscv32gcv and riscv64gcv.

Regards
 Robin

--

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_const_insns): Add permissible
	vector constants.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vmv-imm.c: New test.
---
 gcc/config/riscv/riscv.cc                     |  10 +-
 .../gcc.target/riscv/rvv/autovec/vmv-imm.c    | 109 ++++++++++++++++++
 2 files changed, 118 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index eb7364ca110..6f9c6743028 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1228,7 +1228,15 @@ riscv_const_insns (rtx x)
     case CONST_DOUBLE:
     case CONST_VECTOR:
       /* We can use x0 to load floating-point zero.  */
-      return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
+      if (x == CONST0_RTX (GET_MODE (x)))
+	return 1;
+      /* Constants from -16 to 15 can be loaded with vmv.v.i.
+	 The Wc0, Wc1 constraints are already covered by the
+	 vi constraint so we do not need to check them here
+	 separately.  */
+      else if (TARGET_VECTOR && satisfies_constraint_vi (x))
+	return 1;
+      return 0;
 
     case CONST:
       /* See if we can refer to X directly.  */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm.c
new file mode 100644
index 00000000000..42ca56d4b5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm.c
@@ -0,0 +1,109 @@
+/* { dg-do run } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-builtin --save-temps" } */
+
+#include <stdint.h>
+#include <assert.h>
+
+#define VMV_POS(TYPE,VAL)				\
+  __attribute__ ((noipa))                               \
+  void vmv_##VAL (TYPE dst[], int n)			\
+  {                                                     \
+    for (int i = 0; i < n; i++)                         \
+      dst[i] = VAL;					\
+  }
+
+#define VMV_NEG(TYPE,VAL)				\
+  __attribute__ ((noipa))                               \
+  void vmv_m##VAL (TYPE dst[], int n)			\
+  {                                                     \
+    for (int i = 0; i < n; i++)                         \
+      dst[i] = -VAL;					\
+  }
+
+#define TEST_ALL()	\
+VMV_NEG(int8_t,16)	\
+VMV_NEG(int8_t,15)    	\
+VMV_NEG(int8_t,14)    	\
+VMV_NEG(int8_t,13)    	\
+VMV_NEG(int16_t,12)     \
+VMV_NEG(int16_t,11)     \
+VMV_NEG(int16_t,10)     \
+VMV_NEG(int16_t,9)	\
+VMV_NEG(int32_t,8)	\
+VMV_NEG(int32_t,7)	\
+VMV_NEG(int32_t,6)	\
+VMV_NEG(int32_t,5)	\
+VMV_NEG(int64_t,4)	\
+VMV_NEG(int64_t,3)	\
+VMV_NEG(int64_t,2)	\
+VMV_NEG(int64_t,1)	\
+VMV_POS(uint8_t,0)	\
+VMV_POS(uint8_t,1)	\
+VMV_POS(uint8_t,2)	\
+VMV_POS(uint8_t,3)	\
+VMV_POS(uint16_t,4)	\
+VMV_POS(uint16_t,5)	\
+VMV_POS(uint16_t,6)	\
+VMV_POS(uint16_t,7)	\
+VMV_POS(uint32_t,8)	\
+VMV_POS(uint32_t,9)	\
+VMV_POS(uint32_t,10)	\
+VMV_POS(uint32_t,11)	\
+VMV_POS(uint64_t,12)	\
+VMV_POS(uint64_t,13)	\
+VMV_POS(uint64_t,14)	\
+VMV_POS(uint64_t,15)
+
+TEST_ALL()
+
+#define SZ 32
+
+#define TEST_POS(TYPE,VAL)		\
+  TYPE a##TYPE##VAL[SZ];	  	\
+  vmv_##VAL (a##TYPE##VAL, SZ);	  	\
+  for (int i = 0; i < SZ; i++)	  	\
+    assert (a##TYPE##VAL[i] == VAL);
+
+#define TEST_NEG(TYPE,VAL)		\
+  TYPE am##TYPE##VAL[SZ];	  	\
+  vmv_m##VAL (am##TYPE##VAL, SZ); 	\
+  for (int i = 0; i < SZ; i++)	  	\
+    assert (am##TYPE##VAL[i] == -VAL);
+
+int main ()
+{
+  TEST_NEG(int8_t, 16)
+  TEST_NEG(int8_t, 15)
+  TEST_NEG(int8_t, 14)
+  TEST_NEG(int8_t, 13)
+  TEST_NEG(int16_t, 12)
+  TEST_NEG(int16_t, 11)
+  TEST_NEG(int16_t, 10)
+  TEST_NEG(int16_t, 9)
+  TEST_NEG(int32_t, 8)
+  TEST_NEG(int32_t, 7)
+  TEST_NEG(int32_t, 6)
+  TEST_NEG(int32_t, 5)
+  TEST_NEG(int64_t, 4)
+  TEST_NEG(int64_t, 3)
+  TEST_NEG(int64_t, 2)
+  TEST_NEG(int64_t, 1)
+  TEST_POS(uint8_t, 0)
+  TEST_POS(uint8_t, 1)
+  TEST_POS(uint8_t, 2)
+  TEST_POS(uint8_t, 3)
+  TEST_POS(uint16_t, 4)
+  TEST_POS(uint16_t, 5)
+  TEST_POS(uint16_t, 6)
+  TEST_POS(uint16_t, 7)
+  TEST_POS(uint32_t, 8)
+  TEST_POS(uint32_t, 9)
+  TEST_POS(uint32_t, 10)
+  TEST_POS(uint32_t, 11)
+  TEST_POS(uint64_t, 12)
+  TEST_POS(uint64_t, 13)
+  TEST_POS(uint64_t, 14)
+  TEST_POS(uint64_t, 15)
+}
+
+/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */
-- 
2.40.0