From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id CCE08386F839; Fri, 10 Jul 2020 01:39:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org CCE08386F839 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06A1VdMC175688; Thu, 9 Jul 2020 21:39:49 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com with ESMTP id 326bp043wu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Jul 2020 21:39:49 -0400 Received: from m0098419.ppops.net (m0098419.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 06A1VcvL175615; Thu, 9 Jul 2020 21:39:48 -0400 Received: from ppma03fra.de.ibm.com (6b.4a.5195.ip4.static.sl-reverse.com [149.81.74.107]) by mx0b-001b2d01.pphosted.com with ESMTP id 326bp043wf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Jul 2020 21:39:48 -0400 Received: from pps.filterd (ppma03fra.de.ibm.com [127.0.0.1]) by ppma03fra.de.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 06A1a2vh008074; Fri, 10 Jul 2020 01:39:46 GMT Received: from b06cxnps4074.portsmouth.uk.ibm.com (d06relay11.portsmouth.uk.ibm.com [9.149.109.196]) by ppma03fra.de.ibm.com with ESMTP id 326bch82as-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Jul 2020 01:39:46 +0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 06A1dib163373336 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 10 Jul 2020 01:39:44 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0CC614C046; Fri, 10 Jul 2020 01:39:44 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BAAEB4C040; Fri, 10 Jul 2020 01:39:41 +0000 (GMT) Received: from luoxhus-MacBook-Pro.local (unknown [9.200.53.92]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 10 Jul 2020 01:39:41 +0000 (GMT) Subject: Re: [PATCH] rs6000: Define movsf_from_si2 to extract high part SF element from DImode[PR89310] To: Segher Boessenkool Cc: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com, wschmidt@linux.ibm.com, guojiufu@linux.ibm.com, linkw@gcc.gnu.org References: <20200706021757.1118129-1-luoxhu@linux.ibm.com> <20200707001803.GR3598@gate.crashing.org> <66c7b5d6-afa6-53d7-704d-44834ff00311@linux.ibm.com> <20200707213116.GU3598@gate.crashing.org> <66faac54-0620-5ee0-ff48-5609ad9e3fa7@linux.ibm.com> <20200708224334.GY3598@gate.crashing.org> <20200709192515.GO3598@gate.crashing.org> From: luoxhu Message-ID: <472e0dc4-6fc6-8d0b-2c0c-259dccd29a89@linux.ibm.com> Date: Fri, 10 Jul 2020 09:39:40 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200709192515.GO3598@gate.crashing.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-09_11:2020-07-09, 2020-07-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 phishscore=0 suspectscore=0 spamscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007100001 X-Spam-Status: No, score=-14.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Jul 2020 01:39:51 -0000 Hi, On 2020/7/10 03:25, Segher Boessenkool wrote: > Hi! > > On Thu, Jul 09, 2020 at 11:09:42AM +0800, luoxhu wrote: >>> Maybe change it back to just SI? It won't match often at all for QI or >>> HI anyway, it seems. Sorry for that detour. Should be good with the >>> above nits fixed :-) >> >> OK, if I see correctly, subreg of DImode should be SImode and I used >> subreg:SI to match only SI, so no need to consider mask for QI and HI? :) > > My problem with it was that the shift amounts won't be 32 for QI etc.? But if the subreg:SI only accepts SImode comes in, why do we need handle the shift amounts for QI/HI? It not using QHSI here... > >> +;; {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;} >> +;; split it before reload with "and mask" to avoid generating shift right >> +;; 32 bit then shift left 32 bit. >> +(define_insn_and_split "movsf_from_si2" >> + [(set (match_operand:SF 0 "gpc_reg_operand" "=wa") >> + (unspec:SF [ >> + (subreg:SI ( >> + ashiftrt:DI ( > > Opening parens *start* a line, they never end it. So: > > (define_insn_and_split "movsf_from_si2" > [(set (match_operand:SF 0 "vsx_reg_sfsubreg_ok" "=wa") > (unspec:SF > [(subreg:SI > (ashiftrt:DI > (match_operand:DI 1 "input_operand" "r") > (const_int 32)) > 0)] > UNSPEC_SF_FROM_SI)) > (clobber (match_scratch:DI 2 "=r"))] > > or something like that. There aren't really any real rules... The > important points are that nested things should be indented, and things > at the same level should have the same indent (like the outer set and > clobber). The [ for an unspec is sometimes put at the end of a line, > that reads a little better perhaps. OK, seems the md file needs a format tool too... > >> + "TARGET_NO_SF_SUBREG" >> + "#" >> + "&& vsx_reg_sfsubreg_ok (operands[0], SFmode)" > > Put this in the insn condition? And since this is just a predicate, > you can just use it instead of gpc_reg_operand. > > (The split condition becomes "&& 1" then, not ""). OK, this seems a bit strange as movsi_from_sf, movsf_from_si and movdi_from_sf_zero_ext all use it as condition... And why vsx_reg_sfsubreg_ok allows "SF SUBREGS" and TARGET_NO_SF_SUBREG "avoid (SUBREG:SF (REG:SI)", I guess they are not the same meaning? (The TARGET_NO_SF_SUBREG is also copied from other similar defines.) Thanks. Updated patch and correct the title: Define movsf_from_si2 to extract high part SF element from DImode[PR89310] For extracting high part element from DImode register like: {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;} split it before reload with "and mask" to avoid generating shift right 32 bit then shift left 32 bit. This pattern also exists in PR42475 and PR67741, etc. srdi 3,3,32 sldi 9,3,32 mtvsrd 1,9 xscvspdpn 1,1 => rldicr 3,3,0,31 mtvsrd 1,3 xscvspdpn 1,1 Bootstrap and regression tested pass on Power8-LE. gcc/ChangeLog: 2020-07-08 Xionghu Luo PR rtl-optimization/89310 * config/rs6000/rs6000.md (movsf_from_si2): New define_insn_and_split. gcc/testsuite/ChangeLog: 2020-07-08 Xionghu Luo PR rtl-optimization/89310 * gcc.target/powerpc/pr89310.c: New test. --- gcc/config/rs6000/rs6000.md | 32 ++++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr89310.c | 17 ++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr89310.c diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 4fcd6a94022..2331c84dcbd 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7593,6 +7593,38 @@ (define_insn_and_split "movsf_from_si" "*, *, p9v, p8v, *, *, p8v, p8v, p8v, *")]) +;; For extracting high part element from DImode register like: +;; {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;} +;; split it before reload with "and mask" to avoid generating shift right +;; 32 bit then shift left 32 bit. +(define_insn_and_split "movsf_from_si2" + [(set (match_operand:SF 0 "vsx_reg_sfsubreg_ok" "=wa") + (unspec:SF + [(subreg:SI + (ashiftrt:DI + (match_operand:DI 1 "input_operand" "r") + (const_int 32)) + 0)] + UNSPEC_SF_FROM_SI)) + (clobber (match_scratch:DI 2 "=r"))] + "TARGET_NO_SF_SUBREG" + "#" + "&& 1" + [(const_int 0)] +{ + if (GET_CODE (operands[2]) == SCRATCH) + operands[2] = gen_reg_rtx (DImode); + + rtx mask = GEN_INT (HOST_WIDE_INT_M1U << 32); + emit_insn (gen_anddi3 (operands[2], operands[1], mask)); + emit_insn (gen_p8_mtvsrd_sf (operands[0], operands[2])); + emit_insn (gen_vsx_xscvspdpn_directmove (operands[0], operands[0])); + DONE; +} + [(set_attr "length" "12") + (set_attr "type" "vecfloat") + (set_attr "isa" "p8v")]) ;; Move 64-bit binary/decimal floating point (define_expand "mov" diff --git a/gcc/testsuite/gcc.target/powerpc/pr89310.c b/gcc/testsuite/gcc.target/powerpc/pr89310.c new file mode 100644 index 00000000000..15e78509246 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr89310.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +struct s { + int i; + float f; +}; + +float +foo (struct s arg) +{ + return arg.f; +} + +/* { dg-final { scan-assembler-not {\msrdi\M} } } */ +/* { dg-final { scan-assembler-not {\msldi\M} } } */ +/* { dg-final { scan-assembler-times {\mrldicr\M} 1 } } */ -- 2.21.0.777.g83232e3864