[PATCH, ARM] [3/3] iWMMXt intrinsics documentation

[PATCH, ARM] [3/3] iWMMXt intrinsics documentation

[Xinyu Qi]

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Hi,

This patch adds iWMMXt intrinsics documentation into gcc doc.

doc/extend.texi: Update iwmmxt intrinsics doc.
doc/arm-iwmmxt-intrinsics.texi: New.

Thanks,
Xinyu

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Index: gcc/doc/arm-iwmmxt-intrinsics.texi
===================================================================
--- gcc/doc/arm-iwmmxt-intrinsics.texi	(revision 0)
+++ gcc/doc/arm-iwmmxt-intrinsics.texi	(revision 0)
@@ -0,0 +1,1088 @@
+@c Copyright (C) 2006 Free Software Foundation, Inc.
+@c This is part of the GCC manual.
+@c For copying conditions, see the file gcc.texi.
+
+@itemize @bullet
+@item __m64 _mm_abs_pi8 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wabsb @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_abs_pi16 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wabsh @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_abs_pi32 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wabsw @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_absdiff_pu8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wabsdiffb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_absdiff_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wabsdiffh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_absdiff_pu32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wabsdiffw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_acc_pu8 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{waccb @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_acc_pu16 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wacch @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_acc_pu32 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{waccw @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_add_pi8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{waddb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_add_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{waddh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_add_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{waddw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_addc_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{waddhc @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_addc_pu32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{waddwc @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_addbhusl_pu8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{waddbhusl @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_addbhusm_pu8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{waddbhusm @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_adds_pi8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{waddbss @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_adds_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{waddhss @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_adds_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{waddwss @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_adds_pu8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{waddbus @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_adds_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{waddhus @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_adds_pu32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{waddwus @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_addsubhx_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{waddsubhx @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_align_si64 (__m64 m1, __m64 m2, #const)
+@*@emph{Form of expected instruction(s):} @code{waligni @var{wr0}, @var{wr0}, @var{wr0}, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_alignr0_si64 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{walignr0 @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_alignr1_si64 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{walignr1 @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_alignr2_si64 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{walignr2 @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_alignr3_si64 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{walignr3 @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_and_si64 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wand @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_andnot_si64 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wandn @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_avg_pu8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wavg2br @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_avg_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wavg2hr @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_avg2_pu8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wavg2b @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_avg2_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wavg2h @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_avg4_pu8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wavg4 @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_avg4r_pu8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wavg4r @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_cmpeq_pi8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wcmpeqb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_cmpeq_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wcmpeqh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_cmpeq_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wcmpeqw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_cmpgt_pi8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wcmpgtsb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_cmpgt_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wcmpgtsh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_cmpgt_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wcmpgtsw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_cmpgt_pu8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wcmpgtub @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_cmpgt_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wcmpgtuh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_cmpgt_pu32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wcmpgtuw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __int64 _mm_cvtm64_si64 (__m64 m1)
+@end itemize
+
+@itemize @bullet
+@item __int64 _mm_cvtsi32_si64 (int m1)
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_cvtsi64_m64 (__int64 m1)
+@end itemize
+
+@itemize @bullet
+@item int _mm_cvtsi64_si32 (__int64 m1)
+@end itemize
+
+@itemize @bullet
+@item int _mm_extract_pi8 (__m64 m1, #const)
+@*@emph{Form of expected instruction(s):} @code{textrmsb @var{r0}, @var{wr0}, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item int _mm_extract_pi16 (__m64 m1, #const)
+@*@emph{Form of expected instruction(s):} @code{textrmsh @var{r0}, @var{wr0}, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item int _mm_extract_pi32 (__m64 m1, #const)
+@*@emph{Form of expected instruction(s):} @code{textrmsw @var{r0}, @var{wr0}, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item int _mm_extract_pu8 (__m64 m1, #const)
+@*@emph{Form of expected instruction(s):} @code{textrmub @var{r0}, @var{wr0}, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item int _mm_extract_pu16 (__m64 m1, #const)
+@*@emph{Form of expected instruction(s):} @code{textrmuh @var{r0}, @var{wr0}, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item int _mm_extract_pu32 (__m64 m1, #const)
+@*@emph{Form of expected instruction(s):} @code{textrmsw @var{r0}, @var{wr0}, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item int _mm_getwcx (int number)
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_insert_pi8 (__m64 m1, int d, #const)
+@*@emph{Form of expected instruction(s):} @code{tinsrb @var{wr0}, @var{r0}, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_insert_pi16 (__m64 m1, int d, #const)
+@*@emph{Form of expected instruction(s):} @code{tinsrh @var{wr0}, @var{r0}, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_insert_pi32 (__m64 m1, int d, #const)
+@*@emph{Form of expected instruction(s):} @code{tinsrw @var{wr0}, @var{r0}, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_mac_pi16 (__m64 m1, __m64 m2, __m64 m3)
+@*@emph{Form of expected instruction(s):} @code{wmacs @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_mac_pu16 (__m64 m1, __m64 m2, __m64 m3)
+@*@emph{Form of expected instruction(s):} @code{wmacu @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_macz_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmacsz @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_macz_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmacuz @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_madd_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmadds @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_madd_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmaddu @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_maddx_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmaddsx @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_maddx_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmaddux @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_msub_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmaddsn @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_msub_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmaddun @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_max_pi8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmaxsb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_max_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmaxsh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_max_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmaxsw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_max_pu8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmaxub @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_max_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmaxuh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_max_pu32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmaxuw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_merge_si64 (__m64 m1, __m64 m2, #const)
+@*@emph{Form of expected instruction(s):} @code{wmerge @var{wr0}, @var{wr0}, @var{wr0}, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_mia_si64 (__m64 m1, int a, int b)
+@*@emph{Form of expected instruction(s):} @code{tmia @var{wr0}, @var{r0}, @var{r0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_miabb_si64 (__m64 m1, int a, int b)
+@*@emph{Form of expected instruction(s):} @code{tmiabb @var{wr0}, @var{r0}, @var{r0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_miabt_si64 (__m64 m1, int a, int b)
+@*@emph{Form of expected instruction(s):} @code{tmiabt @var{wr0}, @var{r0}, @var{r0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_miaph_si64 (__m64 m1, int a, int b)
+@*@emph{Form of expected instruction(s):} @code{tmiaph @var{wr0}, @var{r0}, @var{r0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_miatb_si64 (__m64 m1, int a, int b)
+@*@emph{Form of expected instruction(s):} @code{tmiatb @var{wr0}, @var{r0}, @var{r0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_miatt_si64 (__m64 m1, int a, int b)
+@*@emph{Form of expected instruction(s):} @code{tmiatt @var{wr0}, @var{r0}, @var{r0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_min_pi8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wminsb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_min_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wminsh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_min_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wminsw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_min_pu8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wminub @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_min_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wminuh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_min_pu32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wminuw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_movemask_pi8 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{tmovmskb @var{r0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_movemask_pi16 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{tmovmskh @var{r0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_movemask_pi32 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{tmovmskw @var{r0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_mulhi_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmulsm @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_mulhi_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmulwsm @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_mulhi_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmulum @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_mulhi_pu32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmulwum @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_mulhir_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmulsmr @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_mulhir_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmulumr @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_mulhir_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmulwsmr @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_mulhir_pu32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmulwumr @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_mullo_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmulul @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_mullo_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmulwl @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_or_si64 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wor @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_packs_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wpackhss @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_packs_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wpackwss @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_packs_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wpackhus @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_packs_pu32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wpackwus @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_packs_pi64 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wpackdss @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_packs_pu64 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wpackdus @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_qmiabb_pi32 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wqmiabb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_qmiabbn_pi32 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wqmiabbn @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_qmiabt_pi32 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wqmiabt @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_qmiabtn_pi32 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wqmiabtn @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_qmiatb_pi32 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wqmiatb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_qmiatbn_pi32 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wqmiatbn @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_qmiatt_pi32 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wqmiatt @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_qmiattn_pi32 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wqmiattn @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_qmulm_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wqmulm @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_qmulm_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wqmulwm @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_qmulmr_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wqmulmr @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_qmulmr_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wqmulwmr @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_ror_pi16 (__m64 m1, __m64 count)
+@*@emph{Form of expected instruction(s):} @code{wrorh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_ror_pi32 (__m64 m1, __m64 count)
+@*@emph{Form of expected instruction(s):} @code{wrorw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_ror_si64 (__m64 m1, __m64 count)
+@*@emph{Form of expected instruction(s):} @code{wrord @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_rori_pi16 (__m64 m1, int count)
+@*@emph{Form of expected instruction(s):} @code{wrorh(g) @var{wr0}, @var{wr0}, #@var{0}(@var{wcgr0})}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_rori_pi32 (__m64 m1, int count)
+@*@emph{Form of expected instruction(s):} @code{wrorw(g) @var{wr0}, @var{wr0}, #@var{0}(@var{wcgr0})}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_rori_si64 (__m64 m1, int count)
+@*@emph{Form of expected instruction(s):} @code{wrord(g) @var{wr0}, @var{wr0}, #@var{0}(@var{wcgr0})}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_sad_pu8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wsadbz @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_sad_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wsadhz @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_sada_pu8 (__m64 m1, __m64 m2, __m64 m3)
+@*@emph{Form of expected instruction(s):} @code{wsadb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_sada_pu16 (__m64 m1, __m64 m2, __m64 m3)
+@*@emph{Form of expected instruction(s):} @code{wsadh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_set_pi8 (char b7, char b6, char b5, char b4, char b3, char b2, char b1, char b0)
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_set_pi16 (short w3, short w2, short w1, short w0)
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_set_pi32 (int i1, int i0)
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_set1_pi8 (char b)
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_set1_pi16 (short w)
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_set1_pi32 (int i)
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_setr_pi8 (char b0, char b1, char b2, char b3, char b4, char b5, char b6, char b7)
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_setr_pi16 (short w0, short w1, short w2, short w3)
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_setr_pi32 (int i0, int i1)
+@end itemize
+
+@itemize @bullet
+@item void _mm_setwcx (int value, int munber)
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_setzero_si64 (__m64 m1, __m64 m2, __m64 m3)
+@*@emph{Form of expected instruction(s):} @code{wxor @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_shuffle_pi16 (__m64 m1, #const)
+@*@emph{Form of expected instruction(s):} @code{wshufh @var{wr0}, @var{wr0}, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_sll_pi16 (__m64 m1, __m64 count)
+@*@emph{Form of expected instruction(s):} @code{wsllh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_sll_pi32 (__m64 m1, __m64 count)
+@*@emph{Form of expected instruction(s):} @code{wsllw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_sll_si64 (__m64 m1, __m64 count)
+@*@emph{Form of expected instruction(s):} @code{wslld @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_slli_pi16 (__m64 m1, int count)
+@*@emph{Form of expected instruction(s):} @code{wsllh(g) @var{wr0}, @var{wr0}, #@var{0}(@var{wcgr0})}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_slli_pi32 (__m64 m1, int count)
+@*@emph{Form of expected instruction(s):} @code{wsllw(g) @var{wr0}, @var{wr0}, #@var{0}(@var{wcgr0})}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_slli_si64 (__m64 m1, int count)
+@*@emph{Form of expected instruction(s):} @code{wslld(g) @var{wr0}, @var{wr0}, #@var{0}(@var{wcgr0})}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_sra_pi16 (__m64 m1, __m64 count)
+@*@emph{Form of expected instruction(s):} @code{wsrah @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_sra_pi32 (__m64 m1, __m64 count)
+@*@emph{Form of expected instruction(s):} @code{wsraw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_sra_si64 (__m64 m1, __m64 count)
+@*@emph{Form of expected instruction(s):} @code{wsrad @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_srai_pi16 (__m64 m1, int count)
+@*@emph{Form of expected instruction(s):} @code{wsrah(g) @var{wr0}, @var{wr0}, #@var{0}(@var{wcgr0})}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_srai_pi32 (__m64 m1, int count)
+@*@emph{Form of expected instruction(s):} @code{wsraw(g) @var{wr0}, @var{wr0}, #@var{0}(@var{wcgr0})}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_srai_si64 (__m64 m1, int count)
+@*@emph{Form of expected instruction(s):} @code{wsrad(g) @var{wr0}, @var{wr0}, #@var{0}(@var{wcgr0})}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_srl_pi16 (__m64 m1, __m64 count)
+@*@emph{Form of expected instruction(s):} @code{wsrlh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_srl_pi32 (__m64 m1, __m64 count)
+@*@emph{Form of expected instruction(s):} @code{wsrlw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_srl_si64 (__m64 m1, __m64 count)
+@*@emph{Form of expected instruction(s):} @code{wsrld @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_srli_pi16 (__m64 m1, int count)
+@*@emph{Form of expected instruction(s):} @code{wsrlh(g) @var{wr0}, @var{wr0}, #@var{0}(@var{wcgr0})}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_srli_pi32 (__m64 m1, int count)
+@*@emph{Form of expected instruction(s):} @code{wsrlw(g) @var{wr0}, @var{wr0}, #@var{0}(@var{wcgr0})}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_srli_si64 (__m64 m1, int count)
+@*@emph{Form of expected instruction(s):} @code{wsrld(g) @var{wr0}, @var{wr0}, #@var{0}(@var{wcgr0})}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_sub_pi8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wsubb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_sub_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wsubh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_sub_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wsubw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_subaddhx_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wsubaddhx @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_subs_pi8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wsubbss @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_subs_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wsubhss @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_subs_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wsubwss @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_subs_pu8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wsubbus @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_subs_pu16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wsubhus @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_subs_pu32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wsubwus @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item void _mm_tandcb ()
+@*@emph{Form of expected instruction(s):} @code{tandcb r15}
+@end itemize
+
+@itemize @bullet
+@item void _mm_tandch ()
+@*@emph{Form of expected instruction(s):} @code{tandch r15}
+@end itemize
+
+@itemize @bullet
+@item void _mm_tandcw ()
+@*@emph{Form of expected instruction(s):} @code{tandcw r15}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_tbcst_pi8 (int value)
+@*@emph{Form of expected instruction(s):} @code{tbcstb @var{wr0}, @var{r0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_tbcst_pi16 (int value)
+@*@emph{Form of expected instruction(s):} @code{tbcsth @var{wr0}, @var{r0}}
+@end itemize
+
+@itemize @bullet
+@item _m64 _mm_tbcst_pi32 (int value)
+@*@emph{Form of expected instruction(s):} @code{tbcstw @var{wr0}, @var{r0}}
+@end itemize
+
+@itemize @bullet
+@item void _mm_textrcb (#const)
+@*@emph{Form of expected instruction(s):} @code{textrcb r15, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item void _mm_textrch (#const)
+@*@emph{Form of expected instruction(s):} @code{textrch r15, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item void _mm_textrcw (#const)
+@*@emph{Form of expected instruction(s):} @code{textrcw r15, #@var{0}}
+@end itemize
+
+@itemize @bullet
+@item void _mm_torcb ()
+@*@emph{Form of expected instruction(s):} @code{torcb r15}
+@end itemize
+
+@itemize @bullet
+@item void _mm_torch ()
+@*@emph{Form of expected instruction(s):} @code{torch r15}
+@end itemize
+
+@itemize @bullet
+@item void _mm_torcw ()
+@*@emph{Form of expected instruction(s):} @code{torcw r15}
+@end itemize
+
+@itemize @bullet
+@item void _mm_torvscb ()
+@*@emph{Form of expected instruction(s):} @code{torvscb r15}
+@end itemize
+
+@itemize @bullet
+@item void _mm_torvsch ()
+@*@emph{Form of expected instruction(s):} @code{torvsch r15}
+@end itemize
+
+@itemize @bullet
+@item void _mm_torvscw ()
+@*@emph{Form of expected instruction(s):} @code{torvscw r15}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackeh_pi8 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wunpckehsb @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackeh_pi16 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wunpckehsh @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackeh_pi32 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wunpckehsw @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackeh_pu8 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wunpckehub @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackeh_pu16 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wunpckehuh @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackeh_pu32 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wunpckehuw @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackel_pi8 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wunpckelsb @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackel_pi16 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wunpckelsh @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackel_pi32 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wunpckelsw @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackel_pu8 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wunpckelub @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackel_pu16 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wunpckeluh @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackel_pu32 (__m64 m1)
+@*@emph{Form of expected instruction(s):} @code{wunpckeluw @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackhi_pi8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wunpckihb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackhi_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wunpckihh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpackhi_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wunpckihw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpacklo_pi8 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wunpckilb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpacklo_pi16 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wunpckilh @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_unpacklo_pi32 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wunpckilw @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiabb_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiabb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiabbn_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiabbn @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiabt_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiabt @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiabtn_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiabtn @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiatb_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiatb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiatbn_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiatbn @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiatt_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiatt @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiattn_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiattn @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiawbb_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiawbb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiawbbn_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiawbbn @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiawbt_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiawbt @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiawbtn_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiawbtn @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiawtb_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiawtb @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiawtbn_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiawtbn @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiawtt_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiawtt @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_wmiawttn_si64 (__m64 acc, __m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wmiawttn @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
+
+@itemize @bullet
+@item __m64 _mm_xor_si64 (__m64 m1, __m64 m2)
+@*@emph{Form of expected instruction(s):} @code{wxor @var{wr0}, @var{wr0}, @var{wr0}}
+@end itemize
Index: gcc/doc/extend.texi
===================================================================
--- gcc/doc/extend.texi	(revision 175285)
+++ gcc/doc/extend.texi	(working copy)
@@ -8037,153 +8037,15 @@
 void __builtin_set_thread_pointer (void *)
 @end smallexample
 
-@node ARM iWMMXt Built-in Functions
-@subsection ARM iWMMXt Built-in Functions
+@node ARM iWMMXt Intrinsics
+@subsection ARM iWMMXT Intrinsics
 
-These built-in functions are available for the ARM family of
-processors when the @option{-mcpu=iwmmxt} switch is used:
+These built-in intrinsics are available for the ARM family of
+processors when mmintrin.h is included and the @option{-mcpu=iwmmxt}
+switch is used:
 
-@smallexample
-typedef int v2si __attribute__ ((vector_size (8)));
-typedef short v4hi __attribute__ ((vector_size (8)));
-typedef char v8qi __attribute__ ((vector_size (8)));
+@include arm-iwmmxt-intrinsics.texi
 
-int __builtin_arm_getwcx (int)
-void __builtin_arm_setwcx (int, int)
-int __builtin_arm_textrmsb (v8qi, int)
-int __builtin_arm_textrmsh (v4hi, int)
-int __builtin_arm_textrmsw (v2si, int)
-int __builtin_arm_textrmub (v8qi, int)
-int __builtin_arm_textrmuh (v4hi, int)
-int __builtin_arm_textrmuw (v2si, int)
-v8qi __builtin_arm_tinsrb (v8qi, int)
-v4hi __builtin_arm_tinsrh (v4hi, int)
-v2si __builtin_arm_tinsrw (v2si, int)
-long long __builtin_arm_tmia (long long, int, int)
-long long __builtin_arm_tmiabb (long long, int, int)
-long long __builtin_arm_tmiabt (long long, int, int)
-long long __builtin_arm_tmiaph (long long, int, int)
-long long __builtin_arm_tmiatb (long long, int, int)
-long long __builtin_arm_tmiatt (long long, int, int)
-int __builtin_arm_tmovmskb (v8qi)
-int __builtin_arm_tmovmskh (v4hi)
-int __builtin_arm_tmovmskw (v2si)
-long long __builtin_arm_waccb (v8qi)
-long long __builtin_arm_wacch (v4hi)
-long long __builtin_arm_waccw (v2si)
-v8qi __builtin_arm_waddb (v8qi, v8qi)
-v8qi __builtin_arm_waddbss (v8qi, v8qi)
-v8qi __builtin_arm_waddbus (v8qi, v8qi)
-v4hi __builtin_arm_waddh (v4hi, v4hi)
-v4hi __builtin_arm_waddhss (v4hi, v4hi)
-v4hi __builtin_arm_waddhus (v4hi, v4hi)
-v2si __builtin_arm_waddw (v2si, v2si)
-v2si __builtin_arm_waddwss (v2si, v2si)
-v2si __builtin_arm_waddwus (v2si, v2si)
-v8qi __builtin_arm_walign (v8qi, v8qi, int)
-long long __builtin_arm_wand(long long, long long)
-long long __builtin_arm_wandn (long long, long long)
-v8qi __builtin_arm_wavg2b (v8qi, v8qi)
-v8qi __builtin_arm_wavg2br (v8qi, v8qi)
-v4hi __builtin_arm_wavg2h (v4hi, v4hi)
-v4hi __builtin_arm_wavg2hr (v4hi, v4hi)
-v8qi __builtin_arm_wcmpeqb (v8qi, v8qi)
-v4hi __builtin_arm_wcmpeqh (v4hi, v4hi)
-v2si __builtin_arm_wcmpeqw (v2si, v2si)
-v8qi __builtin_arm_wcmpgtsb (v8qi, v8qi)
-v4hi __builtin_arm_wcmpgtsh (v4hi, v4hi)
-v2si __builtin_arm_wcmpgtsw (v2si, v2si)
-v8qi __builtin_arm_wcmpgtub (v8qi, v8qi)
-v4hi __builtin_arm_wcmpgtuh (v4hi, v4hi)
-v2si __builtin_arm_wcmpgtuw (v2si, v2si)
-long long __builtin_arm_wmacs (long long, v4hi, v4hi)
-long long __builtin_arm_wmacsz (v4hi, v4hi)
-long long __builtin_arm_wmacu (long long, v4hi, v4hi)
-long long __builtin_arm_wmacuz (v4hi, v4hi)
-v4hi __builtin_arm_wmadds (v4hi, v4hi)
-v4hi __builtin_arm_wmaddu (v4hi, v4hi)
-v8qi __builtin_arm_wmaxsb (v8qi, v8qi)
-v4hi __builtin_arm_wmaxsh (v4hi, v4hi)
-v2si __builtin_arm_wmaxsw (v2si, v2si)
-v8qi __builtin_arm_wmaxub (v8qi, v8qi)
-v4hi __builtin_arm_wmaxuh (v4hi, v4hi)
-v2si __builtin_arm_wmaxuw (v2si, v2si)
-v8qi __builtin_arm_wminsb (v8qi, v8qi)
-v4hi __builtin_arm_wminsh (v4hi, v4hi)
-v2si __builtin_arm_wminsw (v2si, v2si)
-v8qi __builtin_arm_wminub (v8qi, v8qi)
-v4hi __builtin_arm_wminuh (v4hi, v4hi)
-v2si __builtin_arm_wminuw (v2si, v2si)
-v4hi __builtin_arm_wmulsm (v4hi, v4hi)
-v4hi __builtin_arm_wmulul (v4hi, v4hi)
-v4hi __builtin_arm_wmulum (v4hi, v4hi)
-long long __builtin_arm_wor (long long, long long)
-v2si __builtin_arm_wpackdss (long long, long long)
-v2si __builtin_arm_wpackdus (long long, long long)
-v8qi __builtin_arm_wpackhss (v4hi, v4hi)
-v8qi __builtin_arm_wpackhus (v4hi, v4hi)
-v4hi __builtin_arm_wpackwss (v2si, v2si)
-v4hi __builtin_arm_wpackwus (v2si, v2si)
-long long __builtin_arm_wrord (long long, long long)
-long long __builtin_arm_wrordi (long long, int)
-v4hi __builtin_arm_wrorh (v4hi, long long)
-v4hi __builtin_arm_wrorhi (v4hi, int)
-v2si __builtin_arm_wrorw (v2si, long long)
-v2si __builtin_arm_wrorwi (v2si, int)
-v2si __builtin_arm_wsadb (v8qi, v8qi)
-v2si __builtin_arm_wsadbz (v8qi, v8qi)
-v2si __builtin_arm_wsadh (v4hi, v4hi)
-v2si __builtin_arm_wsadhz (v4hi, v4hi)
-v4hi __builtin_arm_wshufh (v4hi, int)
-long long __builtin_arm_wslld (long long, long long)
-long long __builtin_arm_wslldi (long long, int)
-v4hi __builtin_arm_wsllh (v4hi, long long)
-v4hi __builtin_arm_wsllhi (v4hi, int)
-v2si __builtin_arm_wsllw (v2si, long long)
-v2si __builtin_arm_wsllwi (v2si, int)
-long long __builtin_arm_wsrad (long long, long long)
-long long __builtin_arm_wsradi (long long, int)
-v4hi __builtin_arm_wsrah (v4hi, long long)
-v4hi __builtin_arm_wsrahi (v4hi, int)
-v2si __builtin_arm_wsraw (v2si, long long)
-v2si __builtin_arm_wsrawi (v2si, int)
-long long __builtin_arm_wsrld (long long, long long)
-long long __builtin_arm_wsrldi (long long, int)
-v4hi __builtin_arm_wsrlh (v4hi, long long)
-v4hi __builtin_arm_wsrlhi (v4hi, int)
-v2si __builtin_arm_wsrlw (v2si, long long)
-v2si __builtin_arm_wsrlwi (v2si, int)
-v8qi __builtin_arm_wsubb (v8qi, v8qi)
-v8qi __builtin_arm_wsubbss (v8qi, v8qi)
-v8qi __builtin_arm_wsubbus (v8qi, v8qi)
-v4hi __builtin_arm_wsubh (v4hi, v4hi)
-v4hi __builtin_arm_wsubhss (v4hi, v4hi)
-v4hi __builtin_arm_wsubhus (v4hi, v4hi)
-v2si __builtin_arm_wsubw (v2si, v2si)
-v2si __builtin_arm_wsubwss (v2si, v2si)
-v2si __builtin_arm_wsubwus (v2si, v2si)
-v4hi __builtin_arm_wunpckehsb (v8qi)
-v2si __builtin_arm_wunpckehsh (v4hi)
-long long __builtin_arm_wunpckehsw (v2si)
-v4hi __builtin_arm_wunpckehub (v8qi)
-v2si __builtin_arm_wunpckehuh (v4hi)
-long long __builtin_arm_wunpckehuw (v2si)
-v4hi __builtin_arm_wunpckelsb (v8qi)
-v2si __builtin_arm_wunpckelsh (v4hi)
-long long __builtin_arm_wunpckelsw (v2si)
-v4hi __builtin_arm_wunpckelub (v8qi)
-v2si __builtin_arm_wunpckeluh (v4hi)
-long long __builtin_arm_wunpckeluw (v2si)
-v8qi __builtin_arm_wunpckihb (v8qi, v8qi)
-v4hi __builtin_arm_wunpckihh (v4hi, v4hi)
-v2si __builtin_arm_wunpckihw (v2si, v2si)
-v8qi __builtin_arm_wunpckilb (v8qi, v8qi)
-v4hi __builtin_arm_wunpckilh (v4hi, v4hi)
-v2si __builtin_arm_wunpckilw (v2si, v2si)
-long long __builtin_arm_wxor (long long, long long)
-long long __builtin_arm_wzero ()
-@end smallexample
-
 @node ARM NEON Intrinsics
 @subsection ARM NEON Intrinsics