From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4866 invoked by alias); 13 Mar 2012 08:57:22 -0000 Received: (qmail 4857 invoked by uid 22791); 13 Mar 2012 08:57:20 -0000 X-SWARE-Spam-Status: No, hits=-1.6 required=5.0 tests=AWL,BAYES_00,TW_IW,TW_MX X-Spam-Check-By: sourceware.org Received: from na3sys009aog134.obsmtp.com (HELO psmtp.com) (74.125.149.83) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 13 Mar 2012 08:57:07 +0000 Received: from sc-owa02.marvell.com ([65.219.4.130]) (using TLSv1) by na3sys009aob134.postini.com ([74.125.148.12]) with SMTP ID DSNKT18L3g55iS8eHDmrccAt7GLJG0TA2Fu7@postini.com; Tue, 13 Mar 2012 01:57:07 PDT Received: from SC-vEXCH2.marvell.com ([10.93.76.134]) by sc-owa02.marvell.com ([10.93.76.22]) with mapi; Tue, 13 Mar 2012 01:57:01 -0700 From: Xinyu Qi To: Xinyu Qi , Richard Earnshaw CC: Ramana Radhakrishnan , "gcc-patches@gcc.gnu.org" Date: Tue, 13 Mar 2012 08:57:00 -0000 Subject: RE: PING: [PATCH, ARM, iWMMXt][4/5]: WMMX machine description Message-ID: <4737A960563B524DA805CA602BE04B3064CB1C22D9@SC-VEXCH2.marvell.com> References: <4737A960563B524DA805CA602BE04B306010E1F4E9@SC-VEXCH2.marvell.com> <4737A960563B524DA805CA602BE04B30602611FB90@SC-VEXCH2.marvell.com> <4737A960563B524DA805CA602BE04B30602925062B@SC-VEXCH2.marvell.com> <4EE8DD9D.3060508@arm.com> <4737A960563B524DA805CA602BE04B3063206B1776@SC-VEXCH2.marvell.com> <4EF2FE29.1060204@arm.com> x-cr-hashedpuzzle: C8cm D8x0 IUzz JKtJ Jx3s QhHu REFn UspK W0T/ Zu1R ce4S fIlw gD6K gIX7 jON+ kNqk;3;ZwBjAGMALQBwAGEAdABjAGgAZQBzAEAAZwBjAGMALgBnAG4AdQAuAG8AcgBnADsAcgBhAG0AYQBuAGEALgByAGEAZABoAGEAawByAGkAcwBoAG4AYQBuAEAAbABpAG4AYQByAG8ALgBvAHIAZwA7AHIAZQBhAHIAbgBzAGgAYQBAAGEAcgBtAC4AYwBvAG0A;Sosha1_v1;7;{15FB8B68-B0B8-4703-9019-C14589B341CB};eAB5AHEAaQBAAG0AYQByAHYAZQBsAGwALgBjAG8AbQA=;Tue, 13 Mar 2012 08:56:47 GMT;UgBFADoAIABQAEkATgBHADoAIABbAFAAQQBUAEMASAAsACAAQQBSAE0ALAAgAGkAVwBNAE0AWAB0AF0AWwA0AC8ANQBdADoAIABXAE0ATQBYACAAbQBhAGMAaABpAG4AZQAgAGQAZQBzAGMAcgBpAHAAdABpAG8AbgA= x-cr-puzzleid: {15FB8B68-B0B8-4703-9019-C14589B341CB} Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2012-03/txt/msg00893.txt.bz2 PING At 2012-02-03 10:09:55,"Xinyu Qi" wrote: > PING >=20 > http://gcc.gnu.org/ml/gcc-patches/2011-12/msg01786.html >=20 > At 2011-12-29 14:12:44,"Xinyu Qi" wrote: > > At 2011-12-22 17:53:45,"Richard Earnshaw" wrote: > > > On 22/12/11 06:38, Xinyu Qi wrote: > > > > At 2011-12-15 01:32:13,"Richard Earnshaw" > wrote: > > > >> On 24/11/11 01:33, Xinyu Qi wrote: > > > >>> Hi Ramana, > > > >>> > > > >>> I solve the conflict, please try again. The new diff is attached. > > > >>> > > > >>> Thanks, > > > >>> Xinyu > > > >>> > > > >>> At 2011-11-19 07:36:15,"Ramana Radhakrishnan" > > > >> wrote: > > > >>>> > > > >>>> Hi Xinyu, > > > >>>> > > > >>>> This doesn't apply cleanly currently on trunk and the reject > > > >>>> appears to come from iwmmxt.md and I've not yet investigated why. > > > >>>> > > > >>>> Can you have a look ? > > > >>>> > > > >> > > > >> This patch is NOT ok. > > > >> > > > >> You're adding features that were new in iWMMXt2 (ie not in the > > > >> original > > > >> implementation) but you've provided no means by which the compiler > > > >> can detect which operations are only available on the new cores. > > > > > > > > Hi Richard, > > > > > > > > All of the WMMX chips support WMMX2 instructions. > > > > > > This may be true for Marvell's current range of processors, but I find > > > it hard to reconcile with the assembler support in GAS, which clearly > > > distinguishes between iWMMXT and iWMMXT2 instruction sets. Are you > > > telling me that no cores were ever manufactured (even by Intel) that > > > only supported iWMMXT? > > > > > > I'm concerned that this patch will break support for existing users > > > who have older chips (for GCC we have to go through a deprecation > > > cycle if we want to drop support for something we now believe is > > > no-longer worth maintaining). > > > > > > > What I do is to complement the WMMX2 intrinsic support in GCC. > > > > > > I understand that, and I'm not saying the patch can never go in; just > > > that it needs to separate out the support for the different > > > architecture variants. > > > > > > > I don't think it is necessary for users to consider whether one WMMX > > > > insn is a > > > WMMX2 insn or not. > > > > > > Users don't (unless they want their code to run on legacy processors > > > that only support the original instruction set), but the compiler > > > surely must know what it is targeting. Remember that the instruction > > > patterns are not entirely black boxes, the compiler can do > > > optimizations on intrinsics (it's one of the reasons why they are > > > better than inline assembly). Unless the compiler knows exactly what > > > instructions are legal, it could end up optimizing something that > > > started as a WMMX insn into something that's a WMMX2 insn (for > > > example, propagating a constant into a vector shift expression). > > > > > > R. > > > > Hi, Richard, > > > > You are right. There exist the chips that only support WMMX instruction= s in > the > > history. > > I distinguish the iWMMXt and iWMMXt2 in the patch update this time. > > > > In current GCC, -march=3Diwmmxt and -march=3Diwmmxt2 (or -mcpu=3Diwmmxt > and > > -mcpu=3Diwmmxt2) are almost no difference in the compiling stage. > > I take advantage of them to do the work, that is, make -march=3Diwmmxt = (or > > -mcpu=3Diwmmxt) only support iWMMXt intrinsic iWMMXt built in and WMMX > > instructions, and make -march=3Diwmmxt2 (or -mcpu=3Diwmmxt2) support fu= lly > > iWMMXt2. > > > > Define a new flag FL_IWMMXT2 to represent the chip support iWMMXt2 > > extension, which directly controls the iWMMXt2 built in initialization = and the > > followed defines. > > Define __IWMMXT2__ in TARGET_CPU_CPP_BUILTINS to control the access > of > > iWMMXt2 intrinsics. > > Define TARGET_REALLY_IWMMXT2 to control the access of WMMX2 > > instructions' machine description. > > In arm.md, define iwmmxt2 in "arch" attr to control the access of the > > alternative in shift patterns. > > > > The updated patch 4/5 is attached here. 1/5, 2/5 and 3/5 are updated > > accordingly. Attach them in related mails. > > Please take a look if such modification is proper. > > > > Changelog: > > > > * config/arm/arm.c (arm_output_iwmmxt_shift_immediate): New > > function. > > (arm_output_iwmmxt_tinsr): Likewise. > > * config/arm/arm-protos.h (arm_output_iwmmxt_shift_immediate): > > Declare. > > (arm_output_iwmmxt_tinsr): Likewise. > > * config/arm/iwmmxt.md (WCGR0, WCGR1, WCGR2, WCGR3): New > > constant. > > (iwmmxt_psadbw, iwmmxt_walign, iwmmxt_tmrc, iwmmxt_tmcr): > > Delete. > > (rorv4hi3, rorv2si3, rordi3): Likewise. > > (rorv4hi3_di, rorv2si3_di, rordi3_di): Likewise. > > (ashrv4hi3_di, ashrv2si3_di, ashrdi3_di): Likewise. > > (lshrv4hi3_di, lshrv2si3_di, lshrdi3_di): Likewise. > > (ashlv4hi3_di, ashlv2si3_di, ashldi3_di): Likewise. > > (iwmmxt_tbcstqi, iwmmxt_tbcsthi, iwmmxt_tbcstsi): Likewise > > (*iwmmxt_clrv8qi, *iwmmxt_clrv4hi, *iwmmxt_clrv2si): Likewise. > > (tbcstv8qi, tbcstv4hi, tbsctv2si): New pattern. > > (iwmmxt_clrv8qi, iwmmxt_clrv4hi, iwmmxt_clrv2si): Likewise. > > (*and3_iwmmxt, *ior3_iwmmxt, *xor3_iwmmxt): > > Likewise. > > (ror3, ror3_di): Likewise. > > (ashr3_di, lshr3_di, ashl3_di): Likewise. > > (ashli3_iwmmxt, iwmmxt_waligni, iwmmxt_walignr): Likewise. > > (iwmmxt_walignr0, iwmmxt_walignr1): Likewise. > > (iwmmxt_walignr2, iwmmxt_walignr3): Likewise. > > (iwmmxt_setwcgr0, iwmmxt_setwcgr1): Likewise. > > (iwmmxt_setwcgr2, iwmmxt_setwcgr3): Likewise. > > (iwmmxt_getwcgr0, iwmmxt_getwcgr1): Likewise. > > (iwmmxt_getwcgr2, iwmmxt_getwcgr3): Likewise. > > (All instruction patterns): Add wtype attribute. > > (*iwmmxt_arm_movdi, *iwmmxt_movsi_insn): iWMMXt coexist with vfp. > > (iwmmxt_uavgrndv8qi3, iwmmxt_uavgrndv4hi3): Revise the pattern. > > (iwmmxt_uavgv8qi3, iwmmxt_uavgv4hi3): Likewise. > > (ashr3_iwmmxt, ashl3_iwmmxt, lshr3_iwmmxt): > > Likewise. > > (iwmmxt_tinsrb, iwmmxt_tinsrh, iwmmxt_tinsrw):Likewise. > > (eqv8qi3, eqv4hi3, eqv2si3, gtuv8qi3): Likewise. > > (gtuv4hi3, gtuv2si3, gtv8qi3, gtv4hi3, gtv2si3): Likewise. > > (iwmmxt_wunpckihh, iwmmxt_wunpckihw, iwmmxt_wunpckilh): Likewise. > > (iwmmxt_wunpckilw, iwmmxt_wunpckehub, iwmmxt_wunpckehuh): > > Likewise. > > (iwmmxt_wunpckehuw, iwmmxt_wunpckehsb, iwmmxt_wunpckehsh): > > Likewise. > > (iwmmxt_wunpckehsw, iwmmxt_wunpckelub, iwmmxt_wunpckeluh): > > Likewise. > > (iwmmxt_wunpckeluw, iwmmxt_wunpckelsb, iwmmxt_wunpckelsh): > > Likewise. > > (iwmmxt_wunpckelsw, iwmmxt_wmadds, iwmmxt_wmaddu): Likewise. > > (iwmmxt_wsadb, iwmmxt_wsadh, iwmmxt_wsadbz, iwmmxt_wsadhz): > > Likewise. > > (iwmmxt2.md): Include. > > * config/arm/iwmmxt2.md: New file. > > * config/arm/iterators.md (VMMX2): New mode_iterator. > > * config/arm/arm.md (wtype): New attribute. > > (UNSPEC_WMADDS, UNSPEC_WMADDU): Delete. > > (UNSPEC_WALIGNI): New unspec. > > * config/arm/t-arm (MD_INCLUDES): Add iwmmxt2.md. > > * config/arm/predicates.md (imm_or_reg_operand): New predicate. > > > > Thanks, > > Xinyu