Patch is updated to leave  register allocation same as HEAD for default 
ordering

I have made -morder2  new alternative - ( the previous order2 always 
created worse code so it's loss is unlikely to upset anyone.). We can 
consider using this as default at a latter date.

In addition, I added "Q" constraint to HI mode moves. This will  prefer 
HI mode use of  pointer registers X,Y,Z  - but not when X is used as 
base pointer.  QI, SI and SF mode already used this constraint and are 
unchanged.

Tested with no regression.

If this is acceptable, please comit.

Andy


Andrew Hutchinson wrote:
> Anatoly, could please review and comit this solution if it meets your 
> approval.
>
> The attached patch addresses BASE_POINTER spill failure ICE  bugs:
>
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19636
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=31786
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=24894
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=31644
>
> The patch has been tested against gcc head of 20080121 , but with 
> latest avr target revision (as noted on diff listing)
>
> All example test cases included in  bug reports  now pass compilation 
> without failure. (whereas they all failed before at -O2)
>
> Testsuite (execute) has been run and there were no regressions.
>
>                === gcc Summary ===
>
> # of expected passes            11799
> # of unexpected failures        52
> # of unresolved testcases       23
> # of unsupported tests          682
> /cygdrive/e/awhconf/gcc/xgcc  version 4.3.0 20080121 (experimental) (GCC)
>
>
> The cause of  problem was trying to use base pointer register to 
> reload an expression that got spilled out of a register - when the 
> were no base pointers left available!
> This typically occurs when r30,r31 - they only freely available base 
> pointer - was used for function pointer or EEPROM addressing.
>
> The fix is based around introducing r26,r27 as an additional 
> 'emergency' base pointer register.
>
> 1)  The LEGITIMIZE_RELOAD_ADDRESS substitution is disabled. This allow 
> gcc to explore alternatives (which often avoid need for base pointer!)
> 2)  'legitimate_address_p()'  now accepts R26 as base pointer. No new 
> assembler patterns were needed as these already existed.
>
> These two changes remove basic problem, but as R26 cannot be used as 
> base pointer without extra instructions  code quality suffers. To 
> prevent this the following changes were made to limit unnecessary 
> usage of r26 as base pointer, while still retaining situations where 
> r26,r27 is a good solution.
>
> 3) Register allocation order (priority) is changed. R26,R27 is now 
> demoted to the last "call used" pair. R30/31 is now higher priority 
> and if available will be used as base pointer before R26/27. R28/R29 
> remains at  lower priority (since it is call saved). I also cleaned up 
> declarations.
> 4) Small change made to 'avr_hard_regno_mode_ok' to exclude 
> possibility that a large operand can span off the range of available 
> registers (R31+)
> 5) Existing Q Constraint was used to for memory addressing using base 
> pointer registers. This preferred category has been expanded to 
> include pre_inc and post_dec of pointer registers - thus promoting  
> r26/r27 for this situation.
> 6) The general memory 'm' constraint  is where r26/27 can be still 
> assigned as a base pointer. This has been demoted using '?m' to  give 
> it a lower score than "Q" constraint. (do not use ! - this prevent it 
> being used after reload)
>
>
> In addition:
>
> 6) HI and SImode patterns have "Q" constraint added - this was missing 
> before. If anything pointers are more useful on larger operands!
> 7)  'legitimate_address_p()' was rejecting  address registers that 
> were contained inside subreg RTL patterns. e.g. (subreg:HI ((reg:SI 
> 46) 0)). Such patterns are created when a structure is stored in 
> register. If this structure contained pointer, it would not be 
> recognized immediately as a valid address. e.g  same as (reg:HI 46). 
> This led to poor pointer code often missing easy opportunities for 
> post increment and base +offset instructions.  The simple solution 
> (taken from MIPS port)  is to take the inner register.
>
> With above changes, it as rare to see r26 used as base pointer - and 
> beneficial when it does get used. Overall perhaps a small win on code 
> size and speed. But importantly 4 less bugs!
>
> Andy
>
>