[4.4 PATCH, i386]: Bug target/33555; x86 missed opportunity for sbb

[4.4 PATCH, i386]: Bug target/33555; x86 missed opportunity for sbb

[Uros Bizjak]

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Hello!

This patch implements missed optimization, as proposed in PR 
target/33555. For following testcase:

int test(unsigned long a, unsigned long b)
{
  return -(a < b);
}

we currently generate:

        xorl    %eax, %eax
        cmpq    %rsi, %rdi
        setb    %al
        negl    %eax

with the patch applied, much shorter sequence is produced:

        cmpq    %rsi, %rdi
        sbbl    %eax, %eax


2008-02-18  Uros Bizjak  <ubizjak@gmail.com>

        PR target/33555
        * config/i386/i386.md (*x86_movsicc_0_m1_se): New insn pattern.
        (*x86_movdicc_0_m1_se): Ditto.

testsuite/ChangeLog:

2008-02-18  Uros Bizjak  <ubizjak@gmail.com>

        PR target/33555
        * gcc.target/i386/pr33555.c: New test.

The patch was bootstrapped and regression tested on i686-pc-linux-gnu 
and x86_64-pc-linux-gnu {,-m32}.
Patch will be committed to 4.4 when the trunk opens in stage1.

Uros.

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Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md	(revision 132390)
+++ config/i386/i386.md	(working copy)
@@ -19402,6 +19402,21 @@
    (set_attr "mode" "DI")
    (set_attr "length_immediate" "0")])
 
+(define_insn "*x86_movdicc_0_m1_se"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extract:DI (match_operand 1 "ix86_carry_flag_operator" "")
+			 (const_int 1)
+			 (const_int 0)))
+   (clobber (reg:CC FLAGS_REG))]
+  ""
+  "sbb{q}\t%0, %0"
+  [(set_attr "type" "alu")
+   (set_attr "pent_pair" "pu")
+   (set_attr "memory" "none")
+   (set_attr "imm_disp" "false")
+   (set_attr "mode" "DI")
+   (set_attr "length_immediate" "0")])
+
 (define_insn "*movdicc_c_rex64"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(if_then_else:DI (match_operator 1 "ix86_comparison_operator"
@@ -19445,6 +19460,21 @@
    (set_attr "mode" "SI")
    (set_attr "length_immediate" "0")])
 
+(define_insn "*x86_movsicc_0_m1_se"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(sign_extract:SI (match_operand 1 "ix86_carry_flag_operator" "")
+			 (const_int 1)
+			 (const_int 0)))
+   (clobber (reg:CC FLAGS_REG))]
+  ""
+  "sbb{l}\t%0, %0"
+  [(set_attr "type" "alu")
+   (set_attr "pent_pair" "pu")
+   (set_attr "memory" "none")
+   (set_attr "imm_disp" "false")
+   (set_attr "mode" "SI")
+   (set_attr "length_immediate" "0")])
+
 (define_insn "*movsicc_noc"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(if_then_else:SI (match_operator 1 "ix86_comparison_operator"
Index: testsuite/gcc.target/i386/pr33555.c
===================================================================
--- testsuite/gcc.target/i386/pr33555.c	(revision 0)
+++ testsuite/gcc.target/i386/pr33555.c	(revision 0)
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "sbbl" } } */
+
+int test(unsigned long a, unsigned long b)
+{
+  return -(a < b);
+}