Selective scheduling pass - middle end changes [1/1]

[Andrey Belevantsev <abel@ispras.ru>]

[-- Attachment #1: Type: text/plain, Size: 3687 bytes --]

Hello,

This patch represents the middle-end changes needed for the selective 
scheduler.  They are relatively small and include the following:

o hooks to catch new insns and basic blocks, which can be generated as a 
  result of changing control flow in cfgrtl mode.  These are out of the 
scheduler control, but still we need to initialize internal data for them.

o fixes needed to work with loop data after register allocation and in 
cfgrtl mode, I think one of them was sent by Zdenek to me some time ago.

o a function in genautomata to output maximal insn latency.

o an iterator over hard reg sets analogous to the bitmap iterator.

o an interface to validate_replace_rtx that allows postponing 
simplification of the new rtx until later.

o an interface to rtx_equal_p and hash_rtx that allows skipping certain 
parts of rtx while comparing or hashing.  This is needed for unification 
of e.g. control speculative and data speculative insns (which have 
different patterns, of course).  The similar mechanism for may_trap_p is 
already in trunk, where it is implemented via a target hook.

OK for trunk?
Andrey


2008-06-03  Andrey Belevantsev  <abel@ispras.ru>
	    Dmitry Melnik  <dm@ispras.ru>
	    Dmitry Zhurikhin  <zhur@ispras.ru>
	    Alexander Monakov  <amonakov@ispras.ru>
	    Maxim Kuvyrkov  <maxim@codesourcery.com>
	
	* cfghooks.h (get_cfg_hooks, set_cfg_hooks): New prototypes.

	* cfghooks.c (get_cfg_hooks, set_cfg_hooks): New functions.
	(make_forwarder_block): Update loop latch if we have redirected
	the loop latch edge.

	* cfgloop.c (get_loop_body_in_custom_order): New function.

	* cfgloop.h (LOOPS_HAVE_FALLTHRU_PREHEADERS): New enum field.
	(CP_FALLTHRU_PREHEADERS): Likewise.
	(get_loop_body_in_custom_order): Declare.
	
	* cfgloopmanip.c (has_preds_from_loop): New.
	(create_preheader): Honor CP_FALLTHRU_PREHEADERS.
	Assert that the preheader edge will be fall thru when it is set.
	
	* cse.c (hash_rtx_cb): New.
	(hash_rtx): Use it.

	* emit-rtl.c (add_insn, add_insn_after, add_insn_before,
	emit_insn_after_1): Call insn_added hook.

	* genattr.c (main): Output maximal_insn_latency prototype.

	* genautomata.c (output_default_latencies): New. Factor its code from ...
	(output_internal_insn_latency_func): ... here.
	(output_internal_maximal_insn_latency_func): New.
	(output_maximal_insn_latency_func): New.

	* hard-reg-set.h (UHOST_BITS_PER_WIDE_INT): Define unconditionally.
	(struct hard_reg_set_iterator): New.
	(hard_reg_set_iter_init, hard_reg_set_iter_set,
	hard_reg_set_iter_next): New functions.
	(EXECUTE_IF_SET_IN_HARD_REG_SET): New macro.

	* lists.c (remove_free_INSN_LIST_node,
	remove_free_EXPR_LIST_node): New functions.

	* loop-init.c (loop_optimizer_init): When LOOPS_HAVE_FALLTHRU_PREHEADERS,
	set CP_FALLTHRU_PREHEADERS when calling create_preheaders.
	(loop_optimizer_finalize): Do not verify flow info after reload.

	* passes.c (init_optimization_passes): 	Move pass_compute_alignments
	after pass_machine_reorg.

	* recog.c (validate_replace_rtx_1): New parameter simplify.
	Default it to true.  Update all uses.  Factor out simplifying
	code to ...
	(simplify_while_replacing): ... this new function.
	(validate_replace_rtx_part,
	validate_replace_rtx_part_nosimplify): New.

	* recog.h (validate_replace_rtx_part,
	validate_replace_rtx_part_nosimplify): Declare.

	* rtl.c (rtx_equal_p_cb): New.
	(rtx_equal_p): Use it.

	* rtl.h (rtx_equal_p_cb, hash_rtx_cb): Declare.
	(remove_free_INSN_LIST_NODE, remove_free_EXPR_LIST_node,
	debug_bb_n_slim, debug_bb_slim,	print_rtl_slim,
	sel_sched_fix_param, insn_added): Likewise.

	* rtlhooks-def.h (RTL_HOOKS_INSN_ADDED): Define to NULL.
	Add to RTL_HOOKS_INITIALIZER.


[-- Attachment #2: sel-sched-merge-middle-end.diff.gz --]
[-- Type: application/gzip, Size: 11818 bytes --]