Fix selective scheduling failures on power6

Fix selective scheduling failures on power6

[Andrey Belevantsev]

Hello,

In this thread I will post three separate patches, two of which fix bugs 
found when testing on power6 (bootstrap and SPEC compiling), and the 
third one supports adjusting priority in the rs6000 backend.  The 
combined patch was tested on power6 by Revital Eres with default flags, 
i.e. disabled sel-sched, and by me on x86_64 with sel-sched enabled by 
default.  The power6 test with sel-sched enabled by default bootstraps 
successfully, but has several new execution failures which we cannot 
analyze until we get access to power6.  I think we'll have access soon. 
  Nevertheless, I'm posting the patches now as these are an obvious 
improvement over current situation.  We can start tuning the scheduler 
for power6 after these patches will be checked in.

For two of the patches, I have tests which are reduced from the SPEC2k 
code, so I'm not sure whether these can be included in the GCC test 
suite.  If yes, then I'll include tests when committing the patches.

Andrey

Fix selective scheduling failures on power6 [1/3]

[Andrey Belevantsev]

[-- Attachment #1: Type: text/plain, Size: 976 bytes --]

Hello,

This patch fixes a failure when compiling perl from SPEC CPU2k.  The 
problem was that when the chosen destination register for an expression 
is the same as the existing register, we short-circuited the checks for 
validity of all insns that originated this expression with the chosen 
register.  Obviously not all of the original insns will have the same 
register as the expression -- some of them can have different registers, 
and the check should still be made.

The fix is actually shorter than the explanation.  There is a test 
reduced from SPEC code, I will include it in the commit if this is 
acceptable.

OK for trunk?
Andrey

2008-09-29  Andrey Belevantsev  <abel@ispras.ru>

	* sel-sched.c (try_replace_dest_reg): When chosen register
	and original register is the same, do not bail out early, but
	still check all original insns for validity of replacing destination
	register.  Set EXPR_TARGET_AVAILABLE to 1 before leaving function
	in this case.




[-- Attachment #2: fix-perl-power6.diff --]
[-- Type: text/x-patch, Size: 1839 bytes --]

Index: gcc/sel-sched.c
===================================================================
*** gcc/sel-sched.c	(revision 140752)
--- gcc/sel-sched.c	(working copy)
*************** collect_unavailable_regs_from_bnds (expr
*** 1640,1653 ****
  static bool
  try_replace_dest_reg (ilist_t orig_insns, rtx best_reg, expr_t expr)
  {
-   if (expr_dest_regno (expr) == REGNO (best_reg))
-     {
-       EXPR_TARGET_AVAILABLE (expr) = 1;
-       return true;
-     }
- 
-   gcc_assert (orig_insns);
- 
    /* Try whether we'll be able to generate the insn
       'dest := best_reg' at the place of the original operation.  */
    for (; orig_insns; orig_insns = ILIST_NEXT (orig_insns))
--- 1640,1645 ----
*************** try_replace_dest_reg (ilist_t orig_insns
*** 1655,1669 ****
        insn_t orig_insn = DEF_LIST_DEF (orig_insns)->orig_insn;
  
        gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn)));
! 
!       if (!replace_src_with_reg_ok_p (orig_insn, best_reg)
! 	  || !replace_dest_with_reg_ok_p (orig_insn, best_reg))
  	return false;
      }
  
    /* Make sure that EXPR has the right destination
       register.  */
!   replace_dest_with_reg_in_expr (expr, best_reg);
    return true;
  }
  
--- 1647,1666 ----
        insn_t orig_insn = DEF_LIST_DEF (orig_insns)->orig_insn;
  
        gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn)));
!       
!       if (REGNO (best_reg) != REGNO (INSN_LHS (orig_insn))
! 	  && (! replace_src_with_reg_ok_p (orig_insn, best_reg)
! 	      || ! replace_dest_with_reg_ok_p (orig_insn, best_reg)))
  	return false;
      }
  
    /* Make sure that EXPR has the right destination
       register.  */
!   if (expr_dest_regno (expr) != REGNO (best_reg))
!     replace_dest_with_reg_in_expr (expr, best_reg);
!   else
!     EXPR_TARGET_AVAILABLE (expr) = 1;
!     
    return true;
  }
  

Fix selective scheduling failures on power6 [2/3]

[Andrey Belevantsev]

[-- Attachment #1: Type: text/plain, Size: 1359 bytes --]

Hello,

This patch fixes quite rare situation when can_issue_more variable 
retains incorrect value while switching between the fences.  It is not 
initialized to issue_rate only when the fence to which we are switching 
schedules a USE or something similar with INSN_CODE < 0.  This leads to 
ICE when we try to issue more insns than possible.  Fixed by saving 
can_issue_more with other fence-dependent data and restored when 
starting scheduling on a fence.

The test is reduced from apsi, and I have the same licensing concerns 
about it.

OK for trunk?
Andrey

2008-09-29  Andrey Belevantsev  <abel@ispras.ru>

	* sel-sched.c (advance_one_cycle): Set FENCE_ISSUE_MORE
	to can_issue_more.
	(advance_state_on_fence): Likewise.
	(sel_target_adjust_priority): Print debug output only when
	sched_verbose >= 4, not 2.
	(get_expr_cost): Do not issue all unique insns on the next cycle.
	(fill_insns): Initialize can_issue_more from the value saved
	with the fence.
	* sel-sched-ir.c (flist_add): New parameter issue_more.
	Init FENCE_ISSUE_MORE with it.
	(merge_fences): Likewise.
	(init_fences): Update call to flist_add.
	(add_to_fences, add_clean_fence_to_fences,
	add_dirty_fence_to_fences): Likewise.
	(move_fence_to_fences): Update call to merge_fences.
	* sel-sched-ir.h (struct _fence): New field issue_more.
	(FENCE_ISSUE_MORE): New accessor macro.



[-- Attachment #2: fix-can-issue-more.diff --]
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Index: gcc/sel-sched.c
===================================================================
*** gcc/sel-sched.c	(revision 140752)
--- gcc/sel-sched.c	(working copy)
*************** advance_one_cycle (fence_t fence)
*** 587,592 ****
--- 587,593 ----
    FENCE_ISSUED_INSNS (fence) = 0;
    FENCE_STARTS_CYCLE_P (fence) = 1;
    can_issue_more = issue_rate;
+   FENCE_ISSUE_MORE (fence) = can_issue_more;
  
    for (i = 0; VEC_iterate (rtx, FENCE_EXECUTING_INSNS (fence), i, insn); )
      {
*************** sel_target_adjust_priority (expr_t expr)
*** 3237,3244 ****
  
    gcc_assert (EXPR_PRIORITY_ADJ (expr) >= 0);
  
!   if (sched_verbose >= 2)
!     sel_print ("sel_target_adjust_priority: insn %d,  %d +%d = %d.\n", 
  	       INSN_UID (EXPR_INSN_RTX (expr)), EXPR_PRIORITY (expr), 
  	       EXPR_PRIORITY_ADJ (expr), new_priority);
  
--- 3238,3245 ----
  
    gcc_assert (EXPR_PRIORITY_ADJ (expr) >= 0);
  
!   if (sched_verbose >= 4)
!     sel_print ("sel_target_adjust_priority: insn %d,  %d+%d = %d.\n", 
  	       INSN_UID (EXPR_INSN_RTX (expr)), EXPR_PRIORITY (expr), 
  	       EXPR_PRIORITY_ADJ (expr), new_priority);
  
*************** get_expr_cost (expr_t expr, fence_t fenc
*** 4227,4234 ****
    if (recog_memoized (insn) < 0)
      {
        if (!FENCE_STARTS_CYCLE_P (fence) 
-           /* FIXME: Is this condition necessary?  */
-           && VINSN_UNIQUE_P (EXPR_VINSN (expr))
  	  && INSN_ASM_P (insn))
  	/* This is asm insn which is tryed to be issued on the
  	   cycle not first.  Issue it on the next cycle.  */
--- 4228,4233 ----
*************** advance_state_on_fence (fence_t fence, i
*** 5039,5045 ****
--- 5038,5046 ----
  
    if (sched_verbose >= 2)
      debug_state (FENCE_STATE (fence));
+ 
    FENCE_STARTS_CYCLE_P (fence) = 0;
+   FENCE_ISSUE_MORE (fence) = can_issue_more;
    return asm_p;
  }
  
*************** fill_insns (fence_t fence, int seqno, il
*** 5225,5230 ****
--- 5226,5232 ----
    blist_add (&bnds, insn, NULL, FENCE_DC (fence));
    bnds_tailp = &BLIST_NEXT (bnds);
    set_target_context (FENCE_TC (fence));
+   can_issue_more = FENCE_ISSUE_MORE (fence);
    target_bb = INSN_BB (insn);
  
    /* Do while we can add any operation to the current group.  */
Index: gcc/sel-sched-ir.c
===================================================================
*** gcc/sel-sched-ir.c	(revision 140752)
--- gcc/sel-sched-ir.c	(working copy)
*************** static void
*** 261,267 ****
  flist_add (flist_t *lp, insn_t insn, state_t state, deps_t dc, void *tc, 
             insn_t last_scheduled_insn, VEC(rtx,gc) *executing_insns, 
             int *ready_ticks, int ready_ticks_size, insn_t sched_next, 
!            int cycle, int cycle_issued_insns, 
             bool starts_cycle_p, bool after_stall_p)
  {
    fence_t f;
--- 261,267 ----
  flist_add (flist_t *lp, insn_t insn, state_t state, deps_t dc, void *tc, 
             insn_t last_scheduled_insn, VEC(rtx,gc) *executing_insns, 
             int *ready_ticks, int ready_ticks_size, insn_t sched_next, 
!            int cycle, int cycle_issued_insns, int issue_more, 
             bool starts_cycle_p, bool after_stall_p)
  {
    fence_t f;
*************** flist_add (flist_t *lp, insn_t insn, sta
*** 286,291 ****
--- 286,292 ----
    FENCE_TC (f) = tc;
  
    FENCE_LAST_SCHEDULED_INSN (f) = last_scheduled_insn;
+   FENCE_ISSUE_MORE (f) = issue_more;
    FENCE_EXECUTING_INSNS (f) = executing_insns;
    FENCE_READY_TICKS (f) = ready_ticks;
    FENCE_READY_TICKS_SIZE (f) = ready_ticks_size;
*************** init_fences (insn_t old_fence)
*** 617,622 ****
--- 618,624 ----
                   ready_ticks_size,
                   NULL_RTX /* sched_next */,
  		 1 /* cycle */, 0 /* cycle_issued_insns */, 
+ 		 issue_rate, /* issue_more */
  		 1 /* starts_cycle_p */, 0 /* after_stall_p */);  
      }
  }
*************** init_fences (insn_t old_fence)
*** 628,641 ****
     3) all other fields are set to corresponding constant values.  
  
     INSN, STATE, DC, TC, LAST_SCHEDULED_INSN, EXECUTING_INSNS, 
!    READY_TICKS, READY_TICKS_SIZE, SCHED_NEXT, CYCLE and AFTER_STALL_P
!    are the corresponding fields of the second fence.  */
  static void
  merge_fences (fence_t f, insn_t insn,
  	      state_t state, deps_t dc, void *tc, 
                rtx last_scheduled_insn, VEC(rtx, gc) *executing_insns,
                int *ready_ticks, int ready_ticks_size,
! 	      rtx sched_next, int cycle, bool after_stall_p)
  {
    insn_t last_scheduled_insn_old = FENCE_LAST_SCHEDULED_INSN (f);
  
--- 630,643 ----
     3) all other fields are set to corresponding constant values.  
  
     INSN, STATE, DC, TC, LAST_SCHEDULED_INSN, EXECUTING_INSNS, 
!    READY_TICKS, READY_TICKS_SIZE, SCHED_NEXT, CYCLE, ISSUE_MORE 
!    and AFTER_STALL_P are the corresponding fields of the second fence.  */
  static void
  merge_fences (fence_t f, insn_t insn,
  	      state_t state, deps_t dc, void *tc, 
                rtx last_scheduled_insn, VEC(rtx, gc) *executing_insns,
                int *ready_ticks, int ready_ticks_size,
! 	      rtx sched_next, int cycle, int issue_more, bool after_stall_p)
  {
    insn_t last_scheduled_insn_old = FENCE_LAST_SCHEDULED_INSN (f);
  
*************** merge_fences (fence_t f, insn_t insn,
*** 665,670 ****
--- 667,673 ----
          FENCE_CYCLE (f) = cycle;
  
        FENCE_LAST_SCHEDULED_INSN (f) = NULL;
+       FENCE_ISSUE_MORE (f) = issue_rate; 
        VEC_free (rtx, gc, executing_insns);
        free (ready_ticks);
        if (FENCE_EXECUTING_INSNS (f))
*************** merge_fences (fence_t f, insn_t insn,
*** 696,701 ****
--- 699,705 ----
            delete_target_context (tc);
    
            FENCE_LAST_SCHEDULED_INSN (f) = NULL;
+ 	  FENCE_ISSUE_MORE (f) = issue_rate;
          }
        else
          if (candidate->src == BLOCK_FOR_INSN (last_scheduled_insn))
*************** merge_fences (fence_t f, insn_t insn,
*** 712,717 ****
--- 716,722 ----
              FENCE_TC (f) = tc;
  
              FENCE_LAST_SCHEDULED_INSN (f) = last_scheduled_insn;
+ 	    FENCE_ISSUE_MORE (f) = issue_more;
            }
          else
            {
*************** add_to_fences (flist_tail_t new_fences, 
*** 798,804 ****
                 state_t state, deps_t dc, void *tc, rtx last_scheduled_insn, 
                 VEC(rtx, gc) *executing_insns, int *ready_ticks, 
                 int ready_ticks_size, rtx sched_next, int cycle, 
!                int cycle_issued_insns, bool starts_cycle_p, bool after_stall_p)
  {
    fence_t f = flist_lookup (FLIST_TAIL_HEAD (new_fences), insn);
  
--- 803,810 ----
                 state_t state, deps_t dc, void *tc, rtx last_scheduled_insn, 
                 VEC(rtx, gc) *executing_insns, int *ready_ticks, 
                 int ready_ticks_size, rtx sched_next, int cycle, 
!                int cycle_issued_insns, int issue_rate, 
! 	       bool starts_cycle_p, bool after_stall_p)
  {
    fence_t f = flist_lookup (FLIST_TAIL_HEAD (new_fences), insn);
  
*************** add_to_fences (flist_tail_t new_fences, 
*** 807,813 ****
        flist_add (FLIST_TAIL_TAILP (new_fences), insn, state, dc, tc,
  		 last_scheduled_insn, executing_insns, ready_ticks, 
                   ready_ticks_size, sched_next, cycle, cycle_issued_insns,
! 		 starts_cycle_p, after_stall_p);
  
        FLIST_TAIL_TAILP (new_fences)
  	= &FLIST_NEXT (*FLIST_TAIL_TAILP (new_fences));
--- 813,819 ----
        flist_add (FLIST_TAIL_TAILP (new_fences), insn, state, dc, tc,
  		 last_scheduled_insn, executing_insns, ready_ticks, 
                   ready_ticks_size, sched_next, cycle, cycle_issued_insns,
! 		 issue_rate, starts_cycle_p, after_stall_p);
  
        FLIST_TAIL_TAILP (new_fences)
  	= &FLIST_NEXT (*FLIST_TAIL_TAILP (new_fences));
*************** add_to_fences (flist_tail_t new_fences, 
*** 816,822 ****
      {
        merge_fences (f, insn, state, dc, tc, last_scheduled_insn, 
                      executing_insns, ready_ticks, ready_ticks_size, 
!                     sched_next, cycle, after_stall_p);
      }
  }
  
--- 822,828 ----
      {
        merge_fences (f, insn, state, dc, tc, last_scheduled_insn, 
                      executing_insns, ready_ticks, ready_ticks_size, 
!                     sched_next, cycle, issue_rate, after_stall_p);
      }
  }
  
*************** move_fence_to_fences (flist_t old_fences
*** 835,841 ****
        merge_fences (f, old->insn, old->state, old->dc, old->tc,
                      old->last_scheduled_insn, old->executing_insns,
                      old->ready_ticks, old->ready_ticks_size,
!                     old->sched_next, old->cycle, 
                      old->after_stall_p);
      }
    else
--- 841,847 ----
        merge_fences (f, old->insn, old->state, old->dc, old->tc,
                      old->last_scheduled_insn, old->executing_insns,
                      old->ready_ticks, old->ready_ticks_size,
!                     old->sched_next, old->cycle, old->issue_more,
                      old->after_stall_p);
      }
    else
*************** add_clean_fence_to_fences (flist_tail_t 
*** 861,867 ****
                   NULL_RTX, NULL, 
                   XCNEWVEC (int, ready_ticks_size), ready_ticks_size,
                   NULL_RTX, FENCE_CYCLE (fence) + 1,
!                  0, 1, FENCE_AFTER_STALL_P (fence));
  }
  
  /* Add a new fence to NEW_FENCES list and initialize all of its data 
--- 867,873 ----
                   NULL_RTX, NULL, 
                   XCNEWVEC (int, ready_ticks_size), ready_ticks_size,
                   NULL_RTX, FENCE_CYCLE (fence) + 1,
!                  0, issue_rate, 1, FENCE_AFTER_STALL_P (fence));
  }
  
  /* Add a new fence to NEW_FENCES list and initialize all of its data 
*************** add_dirty_fence_to_fences (flist_tail_t 
*** 885,890 ****
--- 891,897 ----
                   FENCE_SCHED_NEXT (fence),
                   FENCE_CYCLE (fence),
                   FENCE_ISSUED_INSNS (fence),
+ 		 FENCE_ISSUE_MORE (fence),
                   FENCE_STARTS_CYCLE_P (fence),
                   FENCE_AFTER_STALL_P (fence));
  }
Index: gcc/sel-sched-ir.h
===================================================================
*** gcc/sel-sched-ir.h	(revision 140752)
--- gcc/sel-sched-ir.h	(working copy)
*************** struct _fence
*** 296,301 ****
--- 296,304 ----
    /* Insn, which has been scheduled last on this fence.  */
    rtx last_scheduled_insn;
  
+   /* The last value of can_issue_more variable on this fence.  */
+   int issue_more;
+ 
    /* If non-NULL force the next scheduled insn to be SCHED_NEXT.  */
    rtx sched_next;
  
*************** typedef struct _fence *fence_t;
*** 325,330 ****
--- 328,334 ----
  #define FENCE_DC(F) ((F)->dc)
  #define FENCE_TC(F) ((F)->tc)
  #define FENCE_LAST_SCHEDULED_INSN(F) ((F)->last_scheduled_insn)
+ #define FENCE_ISSUE_MORE(F) ((F)->issue_more)
  #define FENCE_EXECUTING_INSNS(F) ((F)->executing_insns)
  #define FENCE_READY_TICKS(F) ((F)->ready_ticks)
  #define FENCE_READY_TICKS_SIZE(F) ((F)->ready_ticks_size)

Fix selective scheduling failures on power6 [3/3]

[Andrey Belevantsev]

[-- Attachment #1: Type: text/plain, Size: 644 bytes --]

Hello,

This patch just makes use of the increase_insn_priority function in the 
rs6000 backend instead of direct modification of INSN_PRIORITY.  Using 
the function means that the backend can change insn priority for 
selective scheduler as well as it does for Haifa scheduler.  The patch 
doesn't fix a bug by itself, but it establishes the ground for further 
tuning of the selective scheduler on power by respecting backend's 
changes of priority.

OK for trunk?
Andrey

2008-09-29  Andrey Belevantsev  <abel@ispras.ru>

	* config/rs6000/rs6000.c (rs6000_sched_reorder2):
	Do not test for sel_sched_p, use increase_insn_priority instead.
	

[-- Attachment #2: fix-rs6000-priority.diff --]
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Index: gcc/config/rs6000/rs6000.c
===================================================================
*** gcc/config/rs6000/rs6000.c	(revision 140752)
--- gcc/config/rs6000/rs6000.c	(working copy)
*************** rs6000_sched_reorder2 (FILE *dump, int s
*** 19501,19509 ****
                      ready[i] = ready[i + 1];
                    ready[*pn_ready-1] = tmp;
  
!                   if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
!                     INSN_PRIORITY (tmp)++;
!                   break;
                  }
                pos--;
              }
--- 19501,19508 ----
                      ready[i] = ready[i + 1];
                    ready[*pn_ready-1] = tmp;
  
! 		  increase_insn_priority (tmp, 1);
! 		  break;
                  }
                pos--;
              }
*************** rs6000_sched_reorder2 (FILE *dump, int s
*** 19517,19527 ****
  
            while (pos >= 0)
              {
!               if (is_load_insn (ready[pos])
!                   && !sel_sched_p ()
! 		  && INSN_PRIORITY_KNOWN (ready[pos]))
                  {
!                   INSN_PRIORITY (ready[pos])++;
  
                    /* Adjust the pendulum to account for the fact that a load
                       was found and increased in priority.  This is to prevent
--- 19516,19524 ----
  
            while (pos >= 0)
              {
!               if (is_load_insn (ready[pos]))
                  {
! 		  increase_insn_priority (ready[pos], 1);
  
                    /* Adjust the pendulum to account for the fact that a load
                       was found and increased in priority.  This is to prevent
*************** rs6000_sched_reorder2 (FILE *dump, int s
*** 19562,19569 ****
                          ready[i] = ready[i + 1];
                        ready[*pn_ready-1] = tmp;
  
!                       if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
!                         INSN_PRIORITY (tmp)++;
  
                        first_store_pos = -1;
  
--- 19559,19565 ----
                          ready[i] = ready[i + 1];
                        ready[*pn_ready-1] = tmp;
  
! 		      increase_insn_priority (tmp, 1);
  
                        first_store_pos = -1;
  
*************** rs6000_sched_reorder2 (FILE *dump, int s
*** 19583,19590 ****
                for (i=first_store_pos; i<*pn_ready-1; i++)
                  ready[i] = ready[i + 1];
                ready[*pn_ready-1] = tmp;
!               if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
!                 INSN_PRIORITY (tmp)++;
              }
          }
        else if (load_store_pendulum == 2)
--- 19579,19585 ----
                for (i=first_store_pos; i<*pn_ready-1; i++)
                  ready[i] = ready[i + 1];
                ready[*pn_ready-1] = tmp;
! 	      increase_insn_priority (tmp, 1);
              }
          }
        else if (load_store_pendulum == 2)
*************** rs6000_sched_reorder2 (FILE *dump, int s
*** 19596,19606 ****
  
            while (pos >= 0)
              {
!               if (is_store_insn (ready[pos])
!                   && !sel_sched_p ()
! 		  && INSN_PRIORITY_KNOWN (ready[pos]))
                  {
!                   INSN_PRIORITY (ready[pos])++;
  
                    /* Adjust the pendulum to account for the fact that a store
                       was found and increased in priority.  This is to prevent
--- 19591,19599 ----
  
            while (pos >= 0)
              {
!               if (is_store_insn (ready[pos]))
                  {
! 		  increase_insn_priority (ready[pos], 1);
  
                    /* Adjust the pendulum to account for the fact that a store
                       was found and increased in priority.  This is to prevent

[PING] [Sched/middle-end] Fix selective scheduling failures on power6 [1/3]

[Andrey Belevantsev]

Andrey Belevantsev wrote:
> This patch fixes a failure when compiling perl from SPEC CPU2k.  The
>  problem was that when the chosen destination register for an
> expression is the same as the existing register, we short-circuited
> the checks for validity of all insns that originated this expression
> with the chosen register.  Obviously not all of the original insns
> will have the same register as the expression -- some of them can
> have different registers, and the check should still be made.
> 
> The fix is actually shorter than the explanation.  There is a test 
> reduced from SPEC code, I will include it in the commit if this is 
> acceptable.
> 
> OK for trunk?
I'm pinging this patch -- it needs a scheduler or middle-end maintainer.

Andrey

[PING][Sched/middle-end] Fix selective scheduling failures on power6 [2/3]

[Andrey Belevantsev]

Andrey Belevantsev wrote:
> Hello,
> 
> This patch fixes quite rare situation when can_issue_more variable 
> retains incorrect value while switching between the fences.  It is not 
> initialized to issue_rate only when the fence to which we are switching 
> schedules a USE or something similar with INSN_CODE < 0.  This leads to 
> ICE when we try to issue more insns than possible.  Fixed by saving 
> can_issue_more with other fence-dependent data and restored when 
> starting scheduling on a fence.
> 
> The test is reduced from apsi, and I have the same licensing concerns 
> about it.
> 
> OK for trunk?
> Andrey
Same here -- this patch needs a scheduler or middle-end maintainer.

Andrey

Re: Fix selective scheduling failures on power6 [1/3]

[Vladimir Makarov]

Andrey Belevantsev wrote:
> Hello,
>
> This patch fixes a failure when compiling perl from SPEC CPU2k.  The 
> problem was that when the chosen destination register for an 
> expression is the same as the existing register, we short-circuited 
> the checks for validity of all insns that originated this expression 
> with the chosen register.  Obviously not all of the original insns 
> will have the same register as the expression -- some of them can have 
> different registers, and the check should still be made.
>
> The fix is actually shorter than the explanation.  There is a test 
> reduced from SPEC code, I will include it in the commit if this is 
> acceptable.
>
> OK for trunk?
> Andrey
>
> 2008-09-29  Andrey Belevantsev  <abel@ispras.ru>
>
>     * sel-sched.c (try_replace_dest_reg): When chosen register
>     and original register is the same, do not bail out early, but
>     still check all original insns for validity of replacing destination
>     register.  Set EXPR_TARGET_AVAILABLE to 1 before leaving function
>     in this case.
>
>
>
Andrey, the patch is ok to commit into the mainline.

Thanks.

Re: Fix selective scheduling failures on power6 [2/3]

[Vladimir Makarov]

Andrey Belevantsev wrote:
> Hello,
>
> This patch fixes quite rare situation when can_issue_more variable 
> retains incorrect value while switching between the fences.  It is not 
> initialized to issue_rate only when the fence to which we are 
> switching schedules a USE or something similar with INSN_CODE < 0.  
> This leads to ICE when we try to issue more insns than possible.  
> Fixed by saving can_issue_more with other fence-dependent data and 
> restored when starting scheduling on a fence.
>
> The test is reduced from apsi, and I have the same licensing concerns 
> about it.
>
> OK for trunk?
> Andrey
>
> 2008-09-29  Andrey Belevantsev  <abel@ispras.ru>
>
>     * sel-sched.c (advance_one_cycle): Set FENCE_ISSUE_MORE
>     to can_issue_more.
>     (advance_state_on_fence): Likewise.
>     (sel_target_adjust_priority): Print debug output only when
>     sched_verbose >= 4, not 2.
>     (get_expr_cost): Do not issue all unique insns on the next cycle.
>     (fill_insns): Initialize can_issue_more from the value saved
>     with the fence.
>     * sel-sched-ir.c (flist_add): New parameter issue_more.
>     Init FENCE_ISSUE_MORE with it.
>     (merge_fences): Likewise.
>     (init_fences): Update call to flist_add.
>     (add_to_fences, add_clean_fence_to_fences,
>     add_dirty_fence_to_fences): Likewise.
>     (move_fence_to_fences): Update call to merge_fences.
>     * sel-sched-ir.h (struct _fence): New field issue_more.
>     (FENCE_ISSUE_MORE): New accessor macro.
>
>
Andrey, the patch is ok to commit into the mainline.

Thanks.