* [PATCH 1/2] RISC-V/testsuite: Add RTL pr105314.c testcase variants
[not found] <alpine.DEB.2.20.2401241102150.14163@tpp.orcam.me.uk>
@ 2024-01-24 11:16 ` Maciej W. Rozycki
2024-01-24 17:09 ` Jeff Law
2024-01-24 11:16 ` [PATCH 2/2] RISC-V/testsuite: Add RTL cset-sext.c " Maciej W. Rozycki
1 sibling, 1 reply; 4+ messages in thread
From: Maciej W. Rozycki @ 2024-01-24 11:16 UTC (permalink / raw)
To: gcc-patches; +Cc: Andrew Waterman, Jim Wilson, Kito Cheng, Palmer Dabbelt
Add a pair of RTL tests, for RV64 and RV32 respectively, corresponding
to the existing pr105314.c test. They have been produced from RTL code
as at the entry of the "ce1" pass for pr105314.c compiled at -O3.
gcc/testsuite/
* gcc.target/riscv/pr105314-rtl.c: New file.
* gcc.target/riscv/pr105314-rtl32.c: New file.
---
gcc/testsuite/gcc.target/riscv/pr105314-rtl.c | 78 ++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c | 78 ++++++++++++++++++++++++
2 files changed, 156 insertions(+)
gcc-test-riscv-pr105314-rtl.diff
Index: gcc/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c
@@ -0,0 +1,78 @@
+/* PR rtl-optimization/105314 */
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-flto" } } */
+/* { dg-options "-fdump-rtl-ce1" } */
+
+long __RTL (startwith ("ce1"))
+foo (long a, long b, long c)
+{
+(function "foo"
+ (param "a"
+ (DECL_RTL (reg/v:DI <1> [ a ]))
+ (DECL_RTL_INCOMING (reg:DI a0 [ a ])))
+ (param "b"
+ (DECL_RTL (reg/v:DI <2> [ b ]))
+ (DECL_RTL_INCOMING (reg:DI a1 [ b ])))
+ (param "c"
+ (DECL_RTL (reg/v:DI <3> [ c ]))
+ (DECL_RTL_INCOMING (reg:DI a2 [ c ])))
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 8 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 2 (set (reg/v:DI <1> [ a ])
+ (reg:DI a0 [ a ])) "pr105314.c":8:1
+ (expr_list:REG_DEAD (reg:DI a0 [ a ])))
+ (cinsn 4 (set (reg/v:DI <3> [ c ])
+ (reg:DI a2 [ c ])) "pr105314.c":8:1
+ (expr_list:REG_DEAD (reg:DI a2 [ c ])))
+ (cnote 5 NOTE_INSN_FUNCTION_BEG)
+ (cjump_insn 10 (set (pc)
+ (if_then_else (ne (reg/v:DI <3> [ c ])
+ (const_int 0))
+ (label_ref:DI 23)
+ (pc))) "pr105314.c":9:6
+ (expr_list:REG_DEAD (reg/v:DI <3> [ c ])
+ (int_list:REG_BR_PROB 536870916)))
+ (edge-to 4)
+ (edge-to 3 (flags "FALLTHRU"))
+ ) ;; block 2
+ (block 3
+ (edge-from 2 (flags "FALLTHRU"))
+ (cnote 11 [bb 3] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 6 (set (reg/v:DI <0> [ <retval> ])
+ (reg/v:DI <1> [ a ])) "pr105314.c":9:6
+ (expr_list:REG_DEAD (reg/v:DI <1> [ a ])))
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 3
+ (block 4
+ (edge-from 2)
+ (clabel 23 3)
+ (cnote 22 [bb 4] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 7 (set (reg/v:DI <0> [ <retval> ])
+ (const_int 0)) "pr105314.c":10:7)
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 4
+ (block 5
+ (edge-from 4 (flags "FALLTHRU"))
+ (edge-from 3 (flags "FALLTHRU"))
+ (clabel 16 1)
+ (cnote 19 [bb 5] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 17 (set (reg/i:DI a0)
+ (reg/v:DI <0> [ <retval> ])) "pr105314.c":12:1
+ (expr_list:REG_DEAD (reg/v:DI <0> [ <retval> ])))
+ (cinsn 18 (use (reg/i:DI a0)) "pr105314.c":12:1)
+ (edge-to exit (flags "FALLTHRU"))
+ ) ;; block 5
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:DI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "foo"
+}
+
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_store_flag_mask" 1 "ce1" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c
@@ -0,0 +1,78 @@
+/* PR rtl-optimization/105314 */
+/* { dg-do compile } */
+/* { dg-require-effective-target rv32 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-flto" } } */
+/* { dg-options "-fdump-rtl-ce1" } */
+
+long __RTL (startwith ("ce1"))
+foo (long a, long b, long c)
+{
+(function "foo"
+ (param "a"
+ (DECL_RTL (reg/v:SI <1> [ a ]))
+ (DECL_RTL_INCOMING (reg:SI a0 [ a ])))
+ (param "b"
+ (DECL_RTL (reg/v:SI <2> [ b ]))
+ (DECL_RTL_INCOMING (reg:SI a1 [ b ])))
+ (param "c"
+ (DECL_RTL (reg/v:SI <3> [ c ]))
+ (DECL_RTL_INCOMING (reg:SI a2 [ c ])))
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 8 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 2 (set (reg/v:SI <1> [ a ])
+ (reg:SI a0 [ a ])) "pr105314.c":8:1
+ (expr_list:REG_DEAD (reg:SI a0 [ a ])))
+ (cinsn 4 (set (reg/v:SI <3> [ c ])
+ (reg:SI a2 [ c ])) "pr105314.c":8:1
+ (expr_list:REG_DEAD (reg:SI a2 [ c ])))
+ (cnote 5 NOTE_INSN_FUNCTION_BEG)
+ (cjump_insn 10 (set (pc)
+ (if_then_else (ne (reg/v:SI <3> [ c ])
+ (const_int 0))
+ (label_ref:SI 23)
+ (pc))) "pr105314.c":9:6
+ (expr_list:REG_DEAD (reg/v:SI <3> [ c ])
+ (int_list:REG_BR_PROB 536870916)))
+ (edge-to 4)
+ (edge-to 3 (flags "FALLTHRU"))
+ ) ;; block 2
+ (block 3
+ (edge-from 2 (flags "FALLTHRU"))
+ (cnote 11 [bb 3] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 6 (set (reg/v:SI <0> [ <retval> ])
+ (reg/v:SI <1> [ a ])) "pr105314.c":9:6
+ (expr_list:REG_DEAD (reg/v:SI <1> [ a ])))
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 3
+ (block 4
+ (edge-from 2)
+ (clabel 23 3)
+ (cnote 22 [bb 4] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 7 (set (reg/v:SI <0> [ <retval> ])
+ (const_int 0)) "pr105314.c":10:7)
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 4
+ (block 5
+ (edge-from 4 (flags "FALLTHRU"))
+ (edge-from 3 (flags "FALLTHRU"))
+ (clabel 16 1)
+ (cnote 19 [bb 5] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 17 (set (reg/i:SI a0)
+ (reg/v:SI <0> [ <retval> ])) "pr105314.c":12:1
+ (expr_list:REG_DEAD (reg/v:SI <0> [ <retval> ])))
+ (cinsn 18 (use (reg/i:SI a0)) "pr105314.c":12:1)
+ (edge-to exit (flags "FALLTHRU"))
+ ) ;; block 5
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:SI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "foo"
+}
+
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_store_flag_mask" 1 "ce1" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH 2/2] RISC-V/testsuite: Add RTL cset-sext.c testcase variants
[not found] <alpine.DEB.2.20.2401241102150.14163@tpp.orcam.me.uk>
2024-01-24 11:16 ` [PATCH 1/2] RISC-V/testsuite: Add RTL pr105314.c testcase variants Maciej W. Rozycki
@ 2024-01-24 11:16 ` Maciej W. Rozycki
2024-01-24 17:10 ` Jeff Law
1 sibling, 1 reply; 4+ messages in thread
From: Maciej W. Rozycki @ 2024-01-24 11:16 UTC (permalink / raw)
To: gcc-patches; +Cc: Andrew Waterman, Jim Wilson, Kito Cheng, Palmer Dabbelt
Add RTL tests, for RV64 and RV32 where appropriate, corresponding to the
existing cset-sext.c tests. They have been produced from RTL code as at
the entry of the "ce1" pass for the respective cset-sext.c tests built
at -O3.
gcc/testsuite/
* gcc.target/riscv/cset-sext-rtl.c: New file.
* gcc.target/riscv/cset-sext-rtl32.c: New file.
* gcc.target/riscv/cset-sext-sfb-rtl.c: New file.
* gcc.target/riscv/cset-sext-sfb-rtl32.c: New file.
* gcc.target/riscv/cset-sext-thead-rtl.c: New file.
* gcc.target/riscv/cset-sext-ventana-rtl.c: New file.
* gcc.target/riscv/cset-sext-zicond-rtl.c: New file.
* gcc.target/riscv/cset-sext-zicond-rtl32.c: New file.
---
gcc/testsuite/gcc.target/riscv/cset-sext-rtl.c | 87 +++++++++++++++
gcc/testsuite/gcc.target/riscv/cset-sext-rtl32.c | 84 +++++++++++++++
gcc/testsuite/gcc.target/riscv/cset-sext-sfb-rtl.c | 88 ++++++++++++++++
gcc/testsuite/gcc.target/riscv/cset-sext-sfb-rtl32.c | 85 +++++++++++++++
gcc/testsuite/gcc.target/riscv/cset-sext-thead-rtl.c | 86 +++++++++++++++
gcc/testsuite/gcc.target/riscv/cset-sext-ventana-rtl.c | 86 +++++++++++++++
gcc/testsuite/gcc.target/riscv/cset-sext-zicond-rtl.c | 86 +++++++++++++++
gcc/testsuite/gcc.target/riscv/cset-sext-zicond-rtl32.c | 83 +++++++++++++++
8 files changed, 685 insertions(+)
gcc-test-riscv-cset-sext-rtl.diff
Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-rtl.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-rtl.c
@@ -0,0 +1,87 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-flto" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */
+
+int __RTL (startwith ("ce1"))
+foo (long a, long b)
+{
+(function "foo"
+ (param "a"
+ (DECL_RTL (reg/v:DI <2> [ a ]))
+ (DECL_RTL_INCOMING (reg:DI a0 [ a ])))
+ (param "b"
+ (DECL_RTL (reg/v:DI <3> [ b ]))
+ (DECL_RTL_INCOMING (reg:DI a1 [ b ])))
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 2 (set (reg/v:DI <2> [ a ])
+ (reg:DI a0 [ a ])) "cset-sext.c":8:1
+ (expr_list:REG_DEAD (reg:DI a0 [ a ])))
+ (cinsn 3 (set (reg/v:DI <3> [ b ])
+ (reg:DI a1 [ b ])) "cset-sext.c":8:1
+ (expr_list:REG_DEAD (reg:DI a1 [ b ])))
+ (cnote 4 NOTE_INSN_FUNCTION_BEG)
+ (cjump_insn 8 (set (pc)
+ (if_then_else (eq (reg/v:DI <3> [ b ])
+ (const_int 0))
+ (label_ref:DI 24)
+ (pc))) "cset-sext.c":9:6
+ (expr_list:REG_DEAD (reg/v:DI <3> [ b ])
+ (int_list:REG_BR_PROB 365072228)))
+ (edge-to 4)
+ (edge-to 3 (flags "FALLTHRU"))
+ ) ;; block 2
+ (block 3
+ (edge-from 2 (flags "FALLTHRU"))
+ (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 10 (set (reg:SI <5>)
+ (ne:SI (reg/v:DI <2> [ a ])
+ (const_int 0))) "cset-sext.c":11:11
+ (expr_list:REG_DEAD (reg/v:DI <2> [ a ])))
+ (cinsn 11 (set (reg:DI <1> [ <retval> ])
+ (sign_extend:DI (reg:SI <5>))) "cset-sext.c":11:11
+ (expr_list:REG_DEAD (reg:SI <5>)))
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 3
+ (block 4
+ (edge-from 2)
+ (clabel 24 3)
+ (cnote 23 [bb 4] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 5 (set (reg:DI <1> [ <retval> ])
+ (const_int 0)) "cset-sext.c":10:12)
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 4
+ (block 5
+ (edge-from 4 (flags "FALLTHRU"))
+ (edge-from 3 (flags "FALLTHRU"))
+ (clabel 12 2)
+ (cnote 13 [bb 5] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 18 (set (reg/i:DI a0)
+ (reg:DI <1> [ <retval> ])) "cset-sext.c":15:1
+ (expr_list:REG_DEAD (reg:DI <1> [ <retval> ])))
+ (cinsn 19 (use (reg/i:DI a0)) "cset-sext.c":15:1)
+ (edge-to exit (flags "FALLTHRU"))
+ ) ;; block 5
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:DI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "foo"
+}
+
+/* Expect branchless assembly like:
+
+ snez a1,a1
+ neg a1,a1
+ snez a0,a0
+ and a0,a1,a0
+ */
+
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssnez\\s" 2 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-rtl32.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-rtl32.c
@@ -0,0 +1,84 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv32 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-flto" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */
+
+int __RTL (startwith ("ce1"))
+foo (long a, long b)
+{
+(function "foo"
+ (param "a"
+ (DECL_RTL (reg/v:SI <2> [ a ]))
+ (DECL_RTL_INCOMING (reg:SI a0 [ a ])))
+ (param "b"
+ (DECL_RTL (reg/v:SI <3> [ b ]))
+ (DECL_RTL_INCOMING (reg:SI a1 [ b ])))
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 2 (set (reg/v:SI <2> [ a ])
+ (reg:SI a0 [ a ])) "cset-sext.c":8:1
+ (expr_list:REG_DEAD (reg:SI a0 [ a ])))
+ (cinsn 3 (set (reg/v:SI <3> [ b ])
+ (reg:SI a1 [ b ])) "cset-sext.c":8:1
+ (expr_list:REG_DEAD (reg:SI a1 [ b ])))
+ (cnote 4 NOTE_INSN_FUNCTION_BEG)
+ (cjump_insn 8 (set (pc)
+ (if_then_else (eq (reg/v:SI <3> [ b ])
+ (const_int 0))
+ (label_ref:SI 23)
+ (pc))) "cset-sext.c":9:6
+ (int_list:REG_BR_PROB 365072228))
+ (edge-to 4)
+ (edge-to 3 (flags "FALLTHRU"))
+ ) ;; block 2
+ (block 3
+ (edge-from 2 (flags "FALLTHRU"))
+ (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 10 (set (reg:SI <1> [ <retval> ])
+ (ne:SI (reg/v:SI <2> [ a ])
+ (const_int 0))) "cset-sext.c":11:11
+ (expr_list:REG_DEAD (reg/v:SI <2> [ a ])))
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 3
+ (block 4
+ (edge-from 2)
+ (clabel 23 3)
+ (cnote 22 [bb 4] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 5 (set (reg:SI <1> [ <retval> ])
+ (const_int 0)) "cset-sext.c":10:12
+ (expr_list:REG_DEAD (reg/v:SI <3> [ b ])))
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 4
+ (block 5
+ (edge-from 4 (flags "FALLTHRU"))
+ (edge-from 3 (flags "FALLTHRU"))
+ (clabel 16 1)
+ (cnote 19 [bb 5] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 17 (set (reg/i:SI a0)
+ (reg:SI <1> [ <retval> ])) "cset-sext.c":15:1
+ (expr_list:REG_DEAD (reg:SI <1> [ <retval> ])))
+ (cinsn 18 (use (reg/i:SI a0)) "cset-sext.c":15:1)
+ (edge-to exit (flags "FALLTHRU"))
+ ) ;; block 5
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:SI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "foo"
+}
+
+/* Expect branchless assembly like:
+
+ snez a1,a1
+ neg a1,a1
+ snez a0,a0
+ and a0,a1,a0
+ */
+
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssnez\\s" 2 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-sfb-rtl.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-sfb-rtl.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-flto" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+int __RTL (startwith ("ce1"))
+foo (long a, long b)
+{
+(function "foo"
+ (param "a"
+ (DECL_RTL (reg/v:DI <2> [ a ]))
+ (DECL_RTL_INCOMING (reg:DI a0 [ a ])))
+ (param "b"
+ (DECL_RTL (reg/v:DI <3> [ b ]))
+ (DECL_RTL_INCOMING (reg:DI a1 [ b ])))
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 2 (set (reg/v:DI <2> [ a ])
+ (reg:DI a0 [ a ])) "cset-sext-sfb.c":8:1
+ (expr_list:REG_DEAD (reg:DI a0 [ a ])))
+ (cinsn 3 (set (reg/v:DI <3> [ b ])
+ (reg:DI a1 [ b ])) "cset-sext-sfb.c":8:1
+ (expr_list:REG_DEAD (reg:DI a1 [ b ])))
+ (cnote 4 NOTE_INSN_FUNCTION_BEG)
+ (cjump_insn 8 (set (pc)
+ (if_then_else (eq (reg/v:DI <3> [ b ])
+ (const_int 0))
+ (label_ref:DI 24)
+ (pc))) "cset-sext-sfb.c":9:6
+ (expr_list:REG_DEAD (reg/v:DI <3> [ b ])
+ (int_list:REG_BR_PROB 365072228)))
+ (edge-to 4)
+ (edge-to 3 (flags "FALLTHRU"))
+ ) ;; block 2
+ (block 3
+ (edge-from 2 (flags "FALLTHRU"))
+ (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 10 (set (reg:SI <5>)
+ (ne:SI (reg/v:DI <2> [ a ])
+ (const_int 0))) "cset-sext-sfb.c":11:11
+ (expr_list:REG_DEAD (reg/v:DI <2> [ a ])))
+ (cinsn 11 (set (reg:DI <1> [ <retval> ])
+ (sign_extend:DI (reg:SI <5>))) "cset-sext-sfb.c":11:11
+ (expr_list:REG_DEAD (reg:SI <5>)))
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 3
+ (block 4
+ (edge-from 2)
+ (clabel 24 3)
+ (cnote 23 [bb 4] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 5 (set (reg:DI <1> [ <retval> ])
+ (const_int 0)) "cset-sext-sfb.c":10:12)
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 4
+ (block 5
+ (edge-from 4 (flags "FALLTHRU"))
+ (edge-from 3 (flags "FALLTHRU"))
+ (clabel 12 2)
+ (cnote 13 [bb 5] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 18 (set (reg/i:DI a0)
+ (reg:DI <1> [ <retval> ])) "cset-sext-sfb.c":15:1
+ (expr_list:REG_DEAD (reg:DI <1> [ <retval> ])))
+ (cinsn 19 (use (reg/i:DI a0)) "cset-sext-sfb.c":15:1)
+ (edge-to exit (flags "FALLTHRU"))
+ ) ;; block 5
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:DI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "foo"
+}
+
+/* Expect short forward branch assembly like:
+
+ snez a0,a0
+ bne a1,zero,1f # movcc
+ mv a0,zero
+1:
+ */
+
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssnez\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sbne\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\sbeq\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-sfb-rtl32.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-sfb-rtl32.c
@@ -0,0 +1,85 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv32 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-flto" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+int __RTL (startwith ("ce1"))
+foo (long a, long b)
+{
+(function "foo"
+ (param "a"
+ (DECL_RTL (reg/v:SI <2> [ a ]))
+ (DECL_RTL_INCOMING (reg:SI a0 [ a ])))
+ (param "b"
+ (DECL_RTL (reg/v:SI <3> [ b ]))
+ (DECL_RTL_INCOMING (reg:SI a1 [ b ])))
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 2 (set (reg/v:SI <2> [ a ])
+ (reg:SI a0 [ a ])) "cset-sext-sfb.c":8:1
+ (expr_list:REG_DEAD (reg:SI a0 [ a ])))
+ (cinsn 3 (set (reg/v:SI <3> [ b ])
+ (reg:SI a1 [ b ])) "cset-sext-sfb.c":8:1
+ (expr_list:REG_DEAD (reg:SI a1 [ b ])))
+ (cnote 4 NOTE_INSN_FUNCTION_BEG)
+ (cjump_insn 8 (set (pc)
+ (if_then_else (eq (reg/v:SI <3> [ b ])
+ (const_int 0))
+ (label_ref:SI 23)
+ (pc))) "cset-sext-sfb.c":9:6
+ (int_list:REG_BR_PROB 365072228))
+ (edge-to 4)
+ (edge-to 3 (flags "FALLTHRU"))
+ ) ;; block 2
+ (block 3
+ (edge-from 2 (flags "FALLTHRU"))
+ (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 10 (set (reg:SI <1> [ <retval> ])
+ (ne:SI (reg/v:SI <2> [ a ])
+ (const_int 0))) "cset-sext-sfb.c":11:11
+ (expr_list:REG_DEAD (reg/v:SI <2> [ a ])))
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 3
+ (block 4
+ (edge-from 2)
+ (clabel 23 3)
+ (cnote 22 [bb 4] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 5 (set (reg:SI <1> [ <retval> ])
+ (const_int 0)) "cset-sext-sfb.c":10:12
+ (expr_list:REG_DEAD (reg/v:SI <3> [ b ])))
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 4
+ (block 5
+ (edge-from 4 (flags "FALLTHRU"))
+ (edge-from 3 (flags "FALLTHRU"))
+ (clabel 16 1)
+ (cnote 19 [bb 5] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 17 (set (reg/i:SI a0)
+ (reg:SI <1> [ <retval> ])) "cset-sext-sfb.c":15:1
+ (expr_list:REG_DEAD (reg:SI <1> [ <retval> ])))
+ (cinsn 18 (use (reg/i:SI a0)) "cset-sext-sfb.c":15:1)
+ (edge-to exit (flags "FALLTHRU"))
+ ) ;; block 5
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:SI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "foo"
+}
+
+/* Expect short forward branch assembly like:
+
+ snez a0,a0
+ bne a1,zero,1f # movcc
+ mv a0,zero
+1:
+ */
+
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssnez\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sbne\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\sbeq\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-thead-rtl.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-thead-rtl.c
@@ -0,0 +1,86 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-flto" } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+int __RTL (startwith ("ce1"))
+foo (long a, long b)
+{
+(function "foo"
+ (param "a"
+ (DECL_RTL (reg/v:DI <2> [ a ]))
+ (DECL_RTL_INCOMING (reg:DI a0 [ a ])))
+ (param "b"
+ (DECL_RTL (reg/v:DI <3> [ b ]))
+ (DECL_RTL_INCOMING (reg:DI a1 [ b ])))
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 2 (set (reg/v:DI <2> [ a ])
+ (reg:DI a0 [ a ])) "cset-sext-thead.c":8:1
+ (expr_list:REG_DEAD (reg:DI a0 [ a ])))
+ (cinsn 3 (set (reg/v:DI <3> [ b ])
+ (reg:DI a1 [ b ])) "cset-sext-thead.c":8:1
+ (expr_list:REG_DEAD (reg:DI a1 [ b ])))
+ (cnote 4 NOTE_INSN_FUNCTION_BEG)
+ (cjump_insn 8 (set (pc)
+ (if_then_else (eq (reg/v:DI <3> [ b ])
+ (const_int 0))
+ (label_ref:DI 24)
+ (pc))) "cset-sext-thead.c":9:6
+ (expr_list:REG_DEAD (reg/v:DI <3> [ b ])
+ (int_list:REG_BR_PROB 365072228)))
+ (edge-to 4)
+ (edge-to 3 (flags "FALLTHRU"))
+ ) ;; block 2
+ (block 3
+ (edge-from 2 (flags "FALLTHRU"))
+ (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 10 (set (reg:SI <5>)
+ (ne:SI (reg/v:DI <2> [ a ])
+ (const_int 0))) "cset-sext-thead.c":11:11
+ (expr_list:REG_DEAD (reg/v:DI <2> [ a ])))
+ (cinsn 11 (set (reg:DI <1> [ <retval> ])
+ (sign_extend:DI (reg:SI <5>))) "cset-sext-thead.c":11:11
+ (expr_list:REG_DEAD (reg:SI <5>)))
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 3
+ (block 4
+ (edge-from 2)
+ (clabel 24 3)
+ (cnote 23 [bb 4] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 5 (set (reg:DI <1> [ <retval> ])
+ (const_int 0)) "cset-sext-thead.c":10:12)
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 4
+ (block 5
+ (edge-from 4 (flags "FALLTHRU"))
+ (edge-from 3 (flags "FALLTHRU"))
+ (clabel 12 2)
+ (cnote 13 [bb 5] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 18 (set (reg/i:DI a0)
+ (reg:DI <1> [ <retval> ])) "cset-sext-thead.c":15:1
+ (expr_list:REG_DEAD (reg:DI <1> [ <retval> ])))
+ (cinsn 19 (use (reg/i:DI a0)) "cset-sext-thead.c":15:1)
+ (edge-to exit (flags "FALLTHRU"))
+ ) ;; block 5
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:DI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "foo"
+}
+
+/* Expect branchless assembly like:
+
+ snez a0,a0
+ th.mveqz a0,zero,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssnez\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-ventana-rtl.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-ventana-rtl.c
@@ -0,0 +1,86 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-flto" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
+
+int __RTL (startwith ("ce1"))
+foo (long a, long b)
+{
+(function "foo"
+ (param "a"
+ (DECL_RTL (reg/v:DI <2> [ a ]))
+ (DECL_RTL_INCOMING (reg:DI a0 [ a ])))
+ (param "b"
+ (DECL_RTL (reg/v:DI <3> [ b ]))
+ (DECL_RTL_INCOMING (reg:DI a1 [ b ])))
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 2 (set (reg/v:DI <2> [ a ])
+ (reg:DI a0 [ a ])) "cset-sext-ventana.c":8:1
+ (expr_list:REG_DEAD (reg:DI a0 [ a ])))
+ (cinsn 3 (set (reg/v:DI <3> [ b ])
+ (reg:DI a1 [ b ])) "cset-sext-ventana.c":8:1
+ (expr_list:REG_DEAD (reg:DI a1 [ b ])))
+ (cnote 4 NOTE_INSN_FUNCTION_BEG)
+ (cjump_insn 8 (set (pc)
+ (if_then_else (eq (reg/v:DI <3> [ b ])
+ (const_int 0))
+ (label_ref:DI 24)
+ (pc))) "cset-sext-ventana.c":9:6
+ (expr_list:REG_DEAD (reg/v:DI <3> [ b ])
+ (int_list:REG_BR_PROB 365072228)))
+ (edge-to 4)
+ (edge-to 3 (flags "FALLTHRU"))
+ ) ;; block 2
+ (block 3
+ (edge-from 2 (flags "FALLTHRU"))
+ (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 10 (set (reg:SI <5>)
+ (ne:SI (reg/v:DI <2> [ a ])
+ (const_int 0))) "cset-sext-ventana.c":11:11
+ (expr_list:REG_DEAD (reg/v:DI <2> [ a ])))
+ (cinsn 11 (set (reg:DI <1> [ <retval> ])
+ (sign_extend:DI (reg:SI <5>))) "cset-sext-ventana.c":11:11
+ (expr_list:REG_DEAD (reg:SI <5>)))
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 3
+ (block 4
+ (edge-from 2)
+ (clabel 24 3)
+ (cnote 23 [bb 4] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 5 (set (reg:DI <1> [ <retval> ])
+ (const_int 0)) "cset-sext-ventana.c":10:12)
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 4
+ (block 5
+ (edge-from 4 (flags "FALLTHRU"))
+ (edge-from 3 (flags "FALLTHRU"))
+ (clabel 12 2)
+ (cnote 13 [bb 5] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 18 (set (reg/i:DI a0)
+ (reg:DI <1> [ <retval> ])) "cset-sext-ventana.c":15:1
+ (expr_list:REG_DEAD (reg:DI <1> [ <retval> ])))
+ (cinsn 19 (use (reg/i:DI a0)) "cset-sext-ventana.c":15:1)
+ (edge-to exit (flags "FALLTHRU"))
+ ) ;; block 5
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:DI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "foo"
+}
+
+/* Expect branchless assembly like:
+
+ snez a0,a0
+ vt.maskc a0,a0,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssnez\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-zicond-rtl.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-zicond-rtl.c
@@ -0,0 +1,86 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-flto" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
+
+int __RTL (startwith ("ce1"))
+foo (long a, long b)
+{
+(function "foo"
+ (param "a"
+ (DECL_RTL (reg/v:DI <2> [ a ]))
+ (DECL_RTL_INCOMING (reg:DI a0 [ a ])))
+ (param "b"
+ (DECL_RTL (reg/v:DI <3> [ b ]))
+ (DECL_RTL_INCOMING (reg:DI a1 [ b ])))
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 2 (set (reg/v:DI <2> [ a ])
+ (reg:DI a0 [ a ])) "cset-sext-zicond.c":8:1
+ (expr_list:REG_DEAD (reg:DI a0 [ a ])))
+ (cinsn 3 (set (reg/v:DI <3> [ b ])
+ (reg:DI a1 [ b ])) "cset-sext-zicond.c":8:1
+ (expr_list:REG_DEAD (reg:DI a1 [ b ])))
+ (cnote 4 NOTE_INSN_FUNCTION_BEG)
+ (cjump_insn 8 (set (pc)
+ (if_then_else (eq (reg/v:DI <3> [ b ])
+ (const_int 0))
+ (label_ref:DI 24)
+ (pc))) "cset-sext-zicond.c":9:6
+ (expr_list:REG_DEAD (reg/v:DI <3> [ b ])
+ (int_list:REG_BR_PROB 365072228)))
+ (edge-to 4)
+ (edge-to 3 (flags "FALLTHRU"))
+ ) ;; block 2
+ (block 3
+ (edge-from 2 (flags "FALLTHRU"))
+ (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 10 (set (reg:SI <5>)
+ (ne:SI (reg/v:DI <2> [ a ])
+ (const_int 0))) "cset-sext-zicond.c":11:11
+ (expr_list:REG_DEAD (reg/v:DI <2> [ a ])))
+ (cinsn 11 (set (reg:DI <1> [ <retval> ])
+ (sign_extend:DI (reg:SI <5>))) "cset-sext-zicond.c":11:11
+ (expr_list:REG_DEAD (reg:SI <5>)))
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 3
+ (block 4
+ (edge-from 2)
+ (clabel 24 3)
+ (cnote 23 [bb 4] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 5 (set (reg:DI <1> [ <retval> ])
+ (const_int 0)) "cset-sext-zicond.c":10:12)
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 4
+ (block 5
+ (edge-from 4 (flags "FALLTHRU"))
+ (edge-from 3 (flags "FALLTHRU"))
+ (clabel 12 2)
+ (cnote 13 [bb 5] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 18 (set (reg/i:DI a0)
+ (reg:DI <1> [ <retval> ])) "cset-sext-zicond.c":15:1
+ (expr_list:REG_DEAD (reg:DI <1> [ <retval> ])))
+ (cinsn 19 (use (reg/i:DI a0)) "cset-sext-zicond.c":15:1)
+ (edge-to exit (flags "FALLTHRU"))
+ ) ;; block 5
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:DI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "foo"
+}
+
+/* Expect branchless assembly like:
+
+ snez a0,a0
+ czero.eqz a0,a0,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssnez\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/cset-sext-zicond-rtl32.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/cset-sext-zicond-rtl32.c
@@ -0,0 +1,83 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv32 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-flto" } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
+
+int __RTL (startwith ("ce1"))
+foo (long a, long b)
+{
+(function "foo"
+ (param "a"
+ (DECL_RTL (reg/v:SI <2> [ a ]))
+ (DECL_RTL_INCOMING (reg:SI a0 [ a ])))
+ (param "b"
+ (DECL_RTL (reg/v:SI <3> [ b ]))
+ (DECL_RTL_INCOMING (reg:SI a1 [ b ])))
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 6 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 2 (set (reg/v:SI <2> [ a ])
+ (reg:SI a0 [ a ])) "cset-sext-zicond.c":8:1
+ (expr_list:REG_DEAD (reg:SI a0 [ a ])))
+ (cinsn 3 (set (reg/v:SI <3> [ b ])
+ (reg:SI a1 [ b ])) "cset-sext-zicond.c":8:1
+ (expr_list:REG_DEAD (reg:SI a1 [ b ])))
+ (cnote 4 NOTE_INSN_FUNCTION_BEG)
+ (cjump_insn 8 (set (pc)
+ (if_then_else (eq (reg/v:SI <3> [ b ])
+ (const_int 0))
+ (label_ref:SI 23)
+ (pc))) "cset-sext-zicond.c":9:6
+ (int_list:REG_BR_PROB 365072228))
+ (edge-to 4)
+ (edge-to 3 (flags "FALLTHRU"))
+ ) ;; block 2
+ (block 3
+ (edge-from 2 (flags "FALLTHRU"))
+ (cnote 9 [bb 3] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 10 (set (reg:SI <1> [ <retval> ])
+ (ne:SI (reg/v:SI <2> [ a ])
+ (const_int 0))) "cset-sext-zicond.c":11:11
+ (expr_list:REG_DEAD (reg/v:SI <2> [ a ])))
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 3
+ (block 4
+ (edge-from 2)
+ (clabel 23 3)
+ (cnote 22 [bb 4] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 5 (set (reg:SI <1> [ <retval> ])
+ (const_int 0)) "cset-sext-zicond.c":10:12
+ (expr_list:REG_DEAD (reg/v:SI <3> [ b ])))
+ (edge-to 5 (flags "FALLTHRU"))
+ ) ;; block 4
+ (block 5
+ (edge-from 4 (flags "FALLTHRU"))
+ (edge-from 3 (flags "FALLTHRU"))
+ (clabel 16 1)
+ (cnote 19 [bb 5] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 17 (set (reg/i:SI a0)
+ (reg:SI <1> [ <retval> ])) "cset-sext-zicond.c":15:1
+ (expr_list:REG_DEAD (reg:SI <1> [ <retval> ])))
+ (cinsn 18 (use (reg/i:SI a0)) "cset-sext-zicond.c":15:1)
+ (edge-to exit (flags "FALLTHRU"))
+ ) ;; block 5
+ ) ;; insn-chain
+ (crtl
+ (return_rtx
+ (reg/i:SI a0)
+ ) ;; return_rtx
+ ) ;; crtl
+) ;; function "foo"
+}
+
+/* Expect branchless assembly like:
+
+ snez a0,a0
+ czero.eqz a0,a0,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove_arith" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssnez\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
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