From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id F30403857C5A; Mon, 13 Jul 2020 06:30:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org F30403857C5A Received: from pps.filterd (m0127361.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06D63lIR057259; Mon, 13 Jul 2020 02:30:39 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 327u1g70nh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 13 Jul 2020 02:30:39 -0400 Received: from m0127361.ppops.net (m0127361.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 06D649QE058337; Mon, 13 Jul 2020 02:30:38 -0400 Received: from ppma05fra.de.ibm.com (6c.4a.5195.ip4.static.sl-reverse.com [149.81.74.108]) by mx0a-001b2d01.pphosted.com with ESMTP id 327u1g70my-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 13 Jul 2020 02:30:38 -0400 Received: from pps.filterd (ppma05fra.de.ibm.com [127.0.0.1]) by ppma05fra.de.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 06D6KuV5031448; Mon, 13 Jul 2020 06:30:36 GMT Received: from b06cxnps3074.portsmouth.uk.ibm.com (d06relay09.portsmouth.uk.ibm.com [9.149.109.194]) by ppma05fra.de.ibm.com with ESMTP id 327q2y0jrr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 13 Jul 2020 06:30:36 +0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 06D6UXaL57737354 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 13 Jul 2020 06:30:33 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4313142041; Mon, 13 Jul 2020 06:30:33 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 13E9842042; Mon, 13 Jul 2020 06:30:31 +0000 (GMT) Received: from luoxhus-MacBook-Pro.local (unknown [9.197.226.61]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 13 Jul 2020 06:30:30 +0000 (GMT) Subject: Re: [PATCH] rs6000: Define movsf_from_si2 to extract high part SF element from DImode[PR89310] To: Segher Boessenkool Cc: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com, wschmidt@linux.ibm.com, guojiufu@linux.ibm.com, linkw@gcc.gnu.org References: <20200706021757.1118129-1-luoxhu@linux.ibm.com> <20200707001803.GR3598@gate.crashing.org> <66c7b5d6-afa6-53d7-704d-44834ff00311@linux.ibm.com> <20200707213116.GU3598@gate.crashing.org> <66faac54-0620-5ee0-ff48-5609ad9e3fa7@linux.ibm.com> <20200708224334.GY3598@gate.crashing.org> <20200709192515.GO3598@gate.crashing.org> <472e0dc4-6fc6-8d0b-2c0c-259dccd29a89@linux.ibm.com> <20200711005438.GE30544@gate.crashing.org> From: luoxhu Message-ID: <49363e95-d454-d9af-24aa-45f641da29fa@linux.ibm.com> Date: Mon, 13 Jul 2020 14:30:28 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200711005438.GE30544@gate.crashing.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-13_03:2020-07-10, 2020-07-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 spamscore=0 priorityscore=1501 clxscore=1015 mlxlogscore=999 suspectscore=0 phishscore=0 bulkscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007130046 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 13 Jul 2020 06:30:42 -0000 Hi, On 2020/7/11 08:54, Segher Boessenkool wrote: > Hi! > > On Fri, Jul 10, 2020 at 09:39:40AM +0800, luoxhu wrote: >> OK, seems the md file needs a format tool too... > > Heh. Just make sure it looks good (that is, does what it looks like), > looks like the rest, etc. It's hard to do anything nice with unspecs, > [ ] lists do not format well. > >>>> + "TARGET_NO_SF_SUBREG" >>>> + "#" >>>> + "&& vsx_reg_sfsubreg_ok (operands[0], SFmode)" >>> >>> Put this in the insn condition? And since this is just a predicate, >>> you can just use it instead of gpc_reg_operand. >>> >>> (The split condition becomes "&& 1" then, not ""). >> >> OK, this seems a bit strange as movsi_from_sf, movsf_from_si and >> movdi_from_sf_zero_ext all use it as condition... > > Since in your case you *always* split, the split condition should be > "always". There are no alternatives that do not split here. > >> And why vsx_reg_sfsubreg_ok allows "SF SUBREGS" and TARGET_NO_SF_SUBREG >> "avoid (SUBREG:SF (REG:SI)", I guess they are not the same meaning? (The >> TARGET_NO_SF_SUBREG is also copied from other similar defines.) Thanks. > > Good question. I do not know. > > Well... Since this define_insn* requires p8 *anyway*, we do not need > any of these sf_subreg things? We always know for each one if it should > be true or false. Yes, removed the vsx_reg_sfsubreg_ok check. > >> + "TARGET_NO_SF_SUBREG" > > But here we should require p8 some other way, then. TARGET_NO_SF_SUBREG is defined to TARGET_DIRECT_MOVE_64BIT, and TARGET_DIRECT_MOVE_64BIT is TARGET_DIRECT_MOVE && TARGET_P8_VECTOR && TARGET_POWERPC64 which means TARGET_P8_VECTOR must be true for TARGET_NO_SF_SUBREG. > >> + (set_attr "isa" "p8v")]) > > (This isn't enough, unfortunately). > Updated patch to removed the vsx_reg_sfsubreg_ok and ICE fix: For extracting high part element from DImode register like: {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;} split it before reload with "and mask" to avoid generating shift right 32 bit then shift left 32 bit. This pattern also exists in PR42475 and PR67741, etc. srdi 3,3,32 sldi 9,3,32 mtvsrd 1,9 xscvspdpn 1,1 => rldicr 3,3,0,31 mtvsrd 1,3 xscvspdpn 1,1 Bootstrap and regression tested pass on Power8-LE. gcc/ChangeLog: 2020-07-13 Xionghu Luo PR rtl-optimization/89310 * config/rs6000/rs6000.md (movsf_from_si2): New define_insn_and_split. gcc/testsuite/ChangeLog: 2020-07-13 Xionghu Luo PR rtl-optimization/89310 * gcc.target/powerpc/pr89310.c: New test. --- gcc/config/rs6000/rs6000.md | 31 ++++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr89310.c | 17 ++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr89310.c diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 4fcd6a94022..480385ed4d2 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7593,6 +7593,37 @@ (define_insn_and_split "movsf_from_si" "*, *, p9v, p8v, *, *, p8v, p8v, p8v, *")]) +;; For extracting high part element from DImode register like: +;; {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;} +;; split it before reload with "and mask" to avoid generating shift right +;; 32 bit then shift left 32 bit. +(define_insn_and_split "movsf_from_si2" + [(set (match_operand:SF 0 "gpc_reg_operand" "=wa") + (unspec:SF + [(subreg:SI + (ashiftrt:DI + (match_operand:DI 1 "input_operand" "r") + (const_int 32)) + 0)] + UNSPEC_SF_FROM_SI)) + (clobber (match_scratch:DI 2 "=r"))] + "TARGET_NO_SF_SUBREG" + "#" + "&& 1" + [(const_int 0)] +{ + if (GET_CODE (operands[2]) == SCRATCH) + operands[2] = gen_reg_rtx (DImode); + + rtx mask = GEN_INT (HOST_WIDE_INT_M1U << 32); + emit_insn (gen_anddi3 (operands[2], operands[1], mask)); + emit_insn (gen_p8_mtvsrd_sf (operands[0], operands[2])); + emit_insn (gen_vsx_xscvspdpn_directmove (operands[0], operands[0])); + DONE; +} + [(set_attr "length" "12") + (set_attr "type" "vecfloat") + (set_attr "isa" "p8v")]) ;; Move 64-bit binary/decimal floating point (define_expand "mov" diff --git a/gcc/testsuite/gcc.target/powerpc/pr89310.c b/gcc/testsuite/gcc.target/powerpc/pr89310.c new file mode 100644 index 00000000000..15e78509246 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr89310.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +struct s { + int i; + float f; +}; + +float +foo (struct s arg) +{ + return arg.f; +} + +/* { dg-final { scan-assembler-not {\msrdi\M} } } */ +/* { dg-final { scan-assembler-not {\msldi\M} } } */ +/* { dg-final { scan-assembler-times {\mrldicr\M} 1 } } */ -- 2.21.0.777.g83232e3864