* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f
@ 2012-10-18 19:28 Dominique Dhumieres
2012-10-18 20:32 ` Mike Stump
2012-10-18 22:31 ` Michael Meissner
0 siblings, 2 replies; 13+ messages in thread
From: Dominique Dhumieres @ 2012-10-18 19:28 UTC (permalink / raw)
To: gcc-patches; +Cc: ebotcazou, meissner
> 2012-10-17 Michael Meissner <meissner@linux.vnet.ibm.com>
>
> * config/rs6000/rs6000.opt (rs6000_isa_flags): New flag word to
> replace target_flags that gives us 63 possible switches.
> (x_rs6000_isa_flags): Save area for rs6000_isa_flags.
> (x_rs6000_isa_flags_explicit): Save area for
> ...
Bootstrap failed on powerpc-apple-darwin9 with
/opt/gcc/darwin_buildw/./prev-gcc/g++ -B/opt/gcc/darwin_buildw/./prev-gcc/ -B/opt/gcc/gcc4.8w/powerpc-apple-darwin9.8.0/bin/ -nostdinc++ -B/opt/gcc/darwin_buildw/prev-powerpc-apple-darwin9.8.0/libstdc++-v3/src/.libs -B/opt/gcc/darwin_buildw/prev-powerpc-apple-darwin9.8.0/libstdc++-v3/libsupc++/.libs -I/opt/gcc/darwin_buildw/prev-powerpc-apple-darwin9.8.0/libstdc++-v3/include/powerpc-apple-darwin9.8.0 -I/opt/gcc/darwin_buildw/prev-powerpc-apple-darwin9.8.0/libstdc++-v3/include -I/opt/gcc/work/libstdc++-v3/libsupc++ -L/opt/gcc/darwin_buildw/prev-powerpc-apple-darwin9.8.0/libstdc++-v3/src/.libs -L/opt/gcc/darwin_buildw/prev-powerpc-apple-darwin9.8.0/libstdc++-v3/libsupc++/.libs -c -g -O2 -mdynamic-no-pic -gtoggle -DIN_GCC -fno-exceptions -fno-rtti -fasynchronous-unwind-tables -W -Wall -Wno-narrowing -Wwrite-strings -Wcast-qual -Wmissing-format-attribute -pedantic -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -Werror -fno-common -DHAVE_CONFIG_H -I. -I. -I../../work/gcc -I../../work/gcc/. -I../../work/gcc/../include -I./../intl -I../../work/gcc/../libcpp/include -I/opt/mp/include -I../../work/gcc/../libdecnumber -I../../work/gcc/../libdecnumber/dpd -I../libdecnumber -I../../work/gcc/../libbacktrace -DCLOOG_INT_GMP -I/opt/mp/include \
../../work/gcc/config/rs6000/rs6000.c -o rs6000.o
../../work/gcc/config/rs6000/rs6000.c:1126:0: error: "MASK_STRICT_ALIGN" redefined [-Werror]
#define MASK_STRICT_ALIGN 0
^
In file included from ./tm.h:15:0,
from ../../work/gcc/config/rs6000/rs6000.c:24:
../../work/gcc/config/rs6000/rs6000.h:490:0: note: this is the location of the previous definition
#define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
^
cc1plus: all warnings being treated as errors
The following patch allowed the bootstrap to complete:
--- gcc/config/rs6000/rs6000.c 2012-10-18 00:34:51.000000000 +0200
+++ ../work/gcc/config/rs6000/rs6000.c 2012-10-18 08:55:28.000000000 +0200
@@ -1123,6 +1123,7 @@ static const struct attribute_spec rs600
#ifndef OPTION_MASK_STRICT_ALIGN
#define OPTION_MASK_STRICT_ALIGN 0
+#undef MASK_STRICT_ALIGN
#define MASK_STRICT_ALIGN 0
#endif
#ifndef TARGET_PROFILE_KERNEL
I don't know if it is the RIGHT FIX, but it worked.
TIA
Dominique
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f 2012-10-18 19:28 [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f Dominique Dhumieres @ 2012-10-18 20:32 ` Mike Stump 2012-10-18 22:31 ` Michael Meissner 1 sibling, 0 replies; 13+ messages in thread From: Mike Stump @ 2012-10-18 20:32 UTC (permalink / raw) To: Dominique Dhumieres; +Cc: gcc-patches, ebotcazou, meissner On Oct 18, 2012, at 12:08 PM, Dominique Dhumieres <dominiq@lps.ens.fr> wrote: > --- gcc/config/rs6000/rs6000.c 2012-10-18 00:34:51.000000000 +0200 > +++ ../work/gcc/config/rs6000/rs6000.c 2012-10-18 08:55:28.000000000 +0200 > @@ -1123,6 +1123,7 @@ static const struct attribute_spec rs600 > > > #ifndef OPTION_MASK_STRICT_ALIGN > #define OPTION_MASK_STRICT_ALIGN 0 > +#undef MASK_STRICT_ALIGN > #define MASK_STRICT_ALIGN 0 > #endif > #ifndef TARGET_PROFILE_KERNEL > > I don't know if it is the RIGHT FIX, but it worked. Given the context, I'd guess #ifndef MASK_STRICT_ALIGN would be the incantation people want. ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f 2012-10-18 19:28 [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f Dominique Dhumieres 2012-10-18 20:32 ` Mike Stump @ 2012-10-18 22:31 ` Michael Meissner 2012-10-19 0:40 ` Michael Meissner 1 sibling, 1 reply; 13+ messages in thread From: Michael Meissner @ 2012-10-18 22:31 UTC (permalink / raw) To: Dominique Dhumieres; +Cc: gcc-patches, ebotcazou, meissner On Thu, Oct 18, 2012 at 09:08:34PM +0200, Dominique Dhumieres wrote: > > 2012-10-17 Michael Meissner <meissner@linux.vnet.ibm.com> > > > > * config/rs6000/rs6000.opt (rs6000_isa_flags): New flag word to > > replace target_flags that gives us 63 possible switches. > > (x_rs6000_isa_flags): Save area for rs6000_isa_flags. > > (x_rs6000_isa_flags_explicit): Save area for > > ... > > Bootstrap failed on powerpc-apple-darwin9 with Just to let you know, I'm iterating on a patch right now. There were 3 bugs with my checkin: 1) The libobjc/encoding.c issue that Eric ran into. The file encoding.c includes compiler tm.h files, and then redefines stuff so that it doesn't need the target option structure. I have a bandaid to redefine TARGET_VSX, TARGET_ALTIVEC, and TARGET_64BIT, but this file really cries out for an Objective C user to reengineer and rewrite it so that it doesn't have to include compiler internal files. 2) The redefinition problem that Dominique found. This was caused by moving POWERPC_MASKS from rs6000.c to rs6000-cpus.def, where it more logically belongs. I think the right solution is to move the #ifdef to rs6000-cpus.def instead of keeping it in rs6000.c. 3) I forgot to update the -mdebug=reg support so it prints out the current options once I swtiched from using target_flags to rs6000_isa_flags. I discovered this today, when doing some future work (that needs new options). I'll send out the patch if my bootstrap finishes. -- Michael Meissner, IBM 5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA meissner@linux.vnet.ibm.com fax +1 (978) 399-6899 ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f 2012-10-18 22:31 ` Michael Meissner @ 2012-10-19 0:40 ` Michael Meissner 2012-10-19 3:40 ` David Edelsohn 2012-10-19 9:45 ` Eric Botcazou 0 siblings, 2 replies; 13+ messages in thread From: Michael Meissner @ 2012-10-19 0:40 UTC (permalink / raw) To: Michael Meissner, Dominique Dhumieres, gcc-patches, ebotcazou, David Edelsohn [-- Attachment #1: Type: text/plain, Size: 2888 bytes --] On Thu, Oct 18, 2012 at 05:35:39PM -0400, Michael Meissner wrote: > On Thu, Oct 18, 2012 at 09:08:34PM +0200, Dominique Dhumieres wrote: > > > 2012-10-17 Michael Meissner <meissner@linux.vnet.ibm.com> > > > > > > * config/rs6000/rs6000.opt (rs6000_isa_flags): New flag word to > > > replace target_flags that gives us 63 possible switches. > > > (x_rs6000_isa_flags): Save area for rs6000_isa_flags. > > > (x_rs6000_isa_flags_explicit): Save area for > > > ... > > > > Bootstrap failed on powerpc-apple-darwin9 with > > Just to let you know, I'm iterating on a patch right now. There were 3 bugs > with my checkin: > > 1) The libobjc/encoding.c issue that Eric ran into. The file encoding.c > includes compiler tm.h files, and then redefines stuff so that it doesn't > need the target option structure. I have a bandaid to redefine TARGET_VSX, > TARGET_ALTIVEC, and TARGET_64BIT, but this file really cries out for an > Objective C user to reengineer and rewrite it so that it doesn't have to > include compiler internal files. > > 2) The redefinition problem that Dominique found. This was caused by moving > POWERPC_MASKS from rs6000.c to rs6000-cpus.def, where it more logically > belongs. I think the right solution is to move the #ifdef to > rs6000-cpus.def instead of keeping it in rs6000.c. > > 3) I forgot to update the -mdebug=reg support so it prints out the current > options once I swtiched from using target_flags to rs6000_isa_flags. I > discovered this today, when doing some future work (that needs new > options). > > I'll send out the patch if my bootstrap finishes. The patch builds in 32-bit on my powerpc64-linux system (which showed up Eric's problem). I can't test the patch for Dominique's problem, since it needs a non-linux system to show up. I verified the debug problem: Eric and Dominique could you try it on your respective systems? Thanks in advance. [gcc] 2012-10-18 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Don't assume OPTION_MASK_STRICT_ALIGN is defined. (MASK_STRICT_ALIGN): If OPTION_MASK_STRICT_ALIGN is not defined, define this to 0 for the 3 ports that use it. * config/rs6000/rs6000.c (OPTION_MASK_STRICT_ALIGN): Don't do check for ports not having -mstrict-align here, move test to rs6000-cpus.def. (MASK_STRICT_ALIGN): Likewise. (rs6000_debug_reg_global): Print out correct target flag words if -mdebug=reg. [libobjc] 2012-10-18 Michael Meissner <meissner@linux.vnet.ibm.com> * encoding.c (TARGET_VSX): Provide definitions based on the current compilation options, and not based off the target options structure. (TARGET_ALTIVEC): Likewise. (TARGET_64BIT): Likewise. -- Michael Meissner, IBM 5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA meissner@linux.vnet.ibm.com fax +1 (978) 399-6899 [-- Attachment #2: gcc-power7.patch367b --] [-- Type: text/plain, Size: 3101 bytes --] Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 192545) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -1121,10 +1121,6 @@ static const struct attribute_spec rs600 { NULL, 0, 0, false, false, false, NULL, false } }; \f -#ifndef OPTION_MASK_STRICT_ALIGN -#define OPTION_MASK_STRICT_ALIGN 0 -#define MASK_STRICT_ALIGN 0 -#endif #ifndef TARGET_PROFILE_KERNEL #define TARGET_PROFILE_KERNEL 0 #endif @@ -1805,10 +1801,11 @@ rs6000_debug_reg_global (void) fprintf (stderr, DEBUG_FMT_S, "tune", "<none>"); cl_target_option_save (&cl_opts, &global_options); - rs6000_print_isa_options (stderr, 0, "target_flags", target_flags); + rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags", + rs6000_isa_flags); - rs6000_print_isa_options (stderr, 0, "target_flags_explicit", - target_flags_explicit); + rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit", + rs6000_isa_flags_explicit); rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask", rs6000_builtin_mask); Index: gcc/config/rs6000/rs6000-cpus.def =================================================================== --- gcc/config/rs6000/rs6000-cpus.def (revision 192545) +++ gcc/config/rs6000/rs6000-cpus.def (working copy) @@ -46,6 +46,14 @@ #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) +/* Deal with ports that do not have -mstrict-align. */ +#ifdef OPTION_MASK_STRICT_ALIGN +#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN +#else +#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0 +#define MASK_STRICT_ALIGN 0 +#endif + /* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ | OPTION_MASK_CMPB \ @@ -64,7 +72,7 @@ | OPTION_MASK_PPC_GPOPT \ | OPTION_MASK_RECIP_PRECISION \ | OPTION_MASK_SOFT_FLOAT \ - | OPTION_MASK_STRICT_ALIGN \ + | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ | OPTION_MASK_VSX) #endif Index: libobjc/encoding.c =================================================================== --- libobjc/encoding.c (revision 192545) +++ libobjc/encoding.c (working copy) @@ -112,6 +112,32 @@ static int __attribute__ ((__unused__)) #undef ALTIVEC_VECTOR_MODE #define ALTIVEC_VECTOR_MODE(MODE) (0) +/* Replace TARGET_VSX, TARGET_ALTIVEC, and TARGET_64BIT with constants based on + the current switches, rather than looking in the options structure. */ +#ifdef _ARCH_PPC +#undef TARGET_VSX +#undef TARGET_ALTIVEC +#undef TARGET_64BIT + +#ifdef __VSX__ +#define TARGET_VSX 1 +#else +#define TARGET_VSX 0 +#endif + +#ifdef __ALTIVEC__ +#define TARGET_ALTIVEC 1 +#else +#define TARGET_ALTIVEC 0 +#endif + +#ifdef _ARCH_PPC64 +#define TARGET_64BIT 1 +#else +#define TARGET_64BIT 0 +#endif +#endif + /* Furthermore, some (powerpc) targets also use TARGET_ALIGN_NATURAL in their alignment macros. Currently[4.5/6], rs6000.h points this to a static variable, initialized by target overrides. This is reset ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f 2012-10-19 0:40 ` Michael Meissner @ 2012-10-19 3:40 ` David Edelsohn 2012-10-19 9:45 ` Eric Botcazou 1 sibling, 0 replies; 13+ messages in thread From: David Edelsohn @ 2012-10-19 3:40 UTC (permalink / raw) To: Michael Meissner, Dominique Dhumieres, gcc-patches, ebotcazou On Thu, Oct 18, 2012 at 7:06 PM, Michael Meissner <meissner@linux.vnet.ibm.com> wrote: > 2012-10-18 Michael Meissner <meissner@linux.vnet.ibm.com> > > * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Don't assume > OPTION_MASK_STRICT_ALIGN is defined. > (MASK_STRICT_ALIGN): If OPTION_MASK_STRICT_ALIGN is not defined, > define this to 0 for the 3 ports that use it. > > * config/rs6000/rs6000.c (OPTION_MASK_STRICT_ALIGN): Don't do > check for ports not having -mstrict-align here, move test to > rs6000-cpus.def. > (MASK_STRICT_ALIGN): Likewise. > (rs6000_debug_reg_global): Print out correct target flag words if > -mdebug=reg. > > [libobjc] > 2012-10-18 Michael Meissner <meissner@linux.vnet.ibm.com> > > * encoding.c (TARGET_VSX): Provide definitions based on the > current compilation options, and not based off the target options > structure. > (TARGET_ALTIVEC): Likewise. > (TARGET_64BIT): Likewise. This is okay if it passes. Ah, yes, that Objective C issue again... Thanks, David ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f 2012-10-19 0:40 ` Michael Meissner 2012-10-19 3:40 ` David Edelsohn @ 2012-10-19 9:45 ` Eric Botcazou 2012-10-19 14:30 ` Dominique Dhumieres 1 sibling, 1 reply; 13+ messages in thread From: Eric Botcazou @ 2012-10-19 9:45 UTC (permalink / raw) To: Michael Meissner; +Cc: gcc-patches, Dominique Dhumieres, David Edelsohn > The patch builds in 32-bit on my powerpc64-linux system (which showed up > Eric's problem). I can't test the patch for Dominique's problem, since it > needs a non-linux system to show up. I verified the debug problem: > > Eric and Dominique could you try it on your respective systems? Thanks in > advance. It works for me, thanks. -- Eric Botcazou ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f 2012-10-19 9:45 ` Eric Botcazou @ 2012-10-19 14:30 ` Dominique Dhumieres 2012-10-19 19:52 ` Michael Meissner 0 siblings, 1 reply; 13+ messages in thread From: Dominique Dhumieres @ 2012-10-19 14:30 UTC (permalink / raw) To: meissner, ebotcazou; +Cc: gcc-patches, dominiq, dje.gcc > > Eric and Dominique could you try it on your respective systems? Thanks in > > advance. > > It works for me, thanks. It does not for me: In file included from ../../work/gcc/config/rs6000/rs6000.c:1475:0: ../../work/gcc/config/rs6000/rs6000-cpus.def:54:0: error: "MASK_STRICT_ALIGN" redefined [-Werror] #define MASK_STRICT_ALIGN 0 ^ In file included from ./tm.h:15:0, from ../../work/gcc/config/rs6000/rs6000.c:24: ../../work/gcc/config/rs6000/rs6000.h:490:0: note: this is the location of the previous definition #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN ^ cc1plus: all warnings being treated as errors I had to use the following modified patch --- ../_gcc_clean/gcc/config/rs6000/rs6000-cpus.def 2012-10-18 00:34:51.000000000 +0200 +++ ../work/gcc/config/rs6000/rs6000-cpus.def 2012-10-19 14:14:59.000000000 +0200 @@ -46,6 +46,17 @@ #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) +/* Deal with ports that do not have -mstrict-align. */ +#ifdef OPTION_MASK_STRICT_ALIGN +#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN +#else +#define OPTION_MASK_STRICT_ALIGN 0 +#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0 +#ifndef MASK_STRICT_ALIGN +#define MASK_STRICT_ALIGN 0 +#endif +#endif + /* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ | OPTION_MASK_CMPB \ @@ -64,7 +75,7 @@ | OPTION_MASK_PPC_GPOPT \ | OPTION_MASK_RECIP_PRECISION \ | OPTION_MASK_SOFT_FLOAT \ - | OPTION_MASK_STRICT_ALIGN \ + | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ | OPTION_MASK_VSX) #endif in order to recompile gcc (not a clean bootstrap), i.e., +#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0 and +#ifndef MASK_STRICT_ALIGN +#define MASK_STRICT_ALIGN 0 +#endif I think this patch could be simplied as +#ifndef OPTION_MASK_STRICT_ALIGN +#define OPTION_MASK_STRICT_ALIGN 0 +#ifndef MASK_STRICT_ALIGN +#define MASK_STRICT_ALIGN 0 +#endif +#endif #define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN Apparently #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN defines MASK_STRICT_ALIGN (to which value?) even if OPTION_MASK_STRICT_ALIGN is not defined. Dominique ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f 2012-10-19 14:30 ` Dominique Dhumieres @ 2012-10-19 19:52 ` Michael Meissner 2012-10-20 6:42 ` Mike Stump 0 siblings, 1 reply; 13+ messages in thread From: Michael Meissner @ 2012-10-19 19:52 UTC (permalink / raw) To: Dominique Dhumieres; +Cc: meissner, ebotcazou, gcc-patches, dje.gcc I checked in your patch along with my patches into the trunk. [gcc] 2012-10-19 Michael Meissner <meissner@linux.vnet.ibm.com> Dominique Dhumieres <dominiq@lps.ens.fr> * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Don't assume OPTION_MASK_STRICT_ALIGN is defined. (MASK_STRICT_ALIGN): If OPTION_MASK_STRICT_ALIGN is not defined, define this to 0 for the 3 ports that use it. * config/rs6000/rs6000.c (OPTION_MASK_STRICT_ALIGN): Don't do check for ports not having -mstrict-align here, move test to rs6000-cpus.def. (MASK_STRICT_ALIGN): Likewise. (rs6000_debug_reg_global): Print out correct target flag words if -mdebug=reg. [libobjc] 2012-10-19 Michael Meissner <meissner@linux.vnet.ibm.com> * encoding.c (TARGET_VSX): Provide definitions based on the current compilation options, and not based off the target options structure. (TARGET_ALTIVEC): Likewise. (TARGET_64BIT): Likewise. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 192622) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -1121,10 +1121,6 @@ static const struct attribute_spec rs600 { NULL, 0, 0, false, false, false, NULL, false } }; \f -#ifndef OPTION_MASK_STRICT_ALIGN -#define OPTION_MASK_STRICT_ALIGN 0 -#define MASK_STRICT_ALIGN 0 -#endif #ifndef TARGET_PROFILE_KERNEL #define TARGET_PROFILE_KERNEL 0 #endif @@ -1805,10 +1801,11 @@ rs6000_debug_reg_global (void) fprintf (stderr, DEBUG_FMT_S, "tune", "<none>"); cl_target_option_save (&cl_opts, &global_options); - rs6000_print_isa_options (stderr, 0, "target_flags", target_flags); + rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags", + rs6000_isa_flags); - rs6000_print_isa_options (stderr, 0, "target_flags_explicit", - target_flags_explicit); + rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit", + rs6000_isa_flags_explicit); rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask", rs6000_builtin_mask); Index: gcc/config/rs6000/rs6000-cpus.def =================================================================== --- gcc/config/rs6000/rs6000-cpus.def (revision 192622) +++ gcc/config/rs6000/rs6000-cpus.def (working copy) @@ -46,6 +46,17 @@ #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) +/* Deal with ports that do not have -mstrict-align. */ +#ifdef OPTION_MASK_STRICT_ALIGN +#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN +#else +#define OPTION_MASK_STRICT_ALIGN 0 +#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0 +#ifndef MASK_STRICT_ALIGN +#define MASK_STRICT_ALIGN 0 +#endif +#endif + /* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ | OPTION_MASK_CMPB \ @@ -64,7 +75,7 @@ | OPTION_MASK_PPC_GPOPT \ | OPTION_MASK_RECIP_PRECISION \ | OPTION_MASK_SOFT_FLOAT \ - | OPTION_MASK_STRICT_ALIGN \ + | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ | OPTION_MASK_VSX) #endif Index: libobjc/encoding.c =================================================================== --- libobjc/encoding.c (revision 192622) +++ libobjc/encoding.c (working copy) @@ -112,6 +112,32 @@ static int __attribute__ ((__unused__)) #undef ALTIVEC_VECTOR_MODE #define ALTIVEC_VECTOR_MODE(MODE) (0) +/* Replace TARGET_VSX, TARGET_ALTIVEC, and TARGET_64BIT with constants based on + the current switches, rather than looking in the options structure. */ +#ifdef _ARCH_PPC +#undef TARGET_VSX +#undef TARGET_ALTIVEC +#undef TARGET_64BIT + +#ifdef __VSX__ +#define TARGET_VSX 1 +#else +#define TARGET_VSX 0 +#endif + +#ifdef __ALTIVEC__ +#define TARGET_ALTIVEC 1 +#else +#define TARGET_ALTIVEC 0 +#endif + +#ifdef _ARCH_PPC64 +#define TARGET_64BIT 1 +#else +#define TARGET_64BIT 0 +#endif +#endif + /* Furthermore, some (powerpc) targets also use TARGET_ALIGN_NATURAL in their alignment macros. Currently[4.5/6], rs6000.h points this to a static variable, initialized by target overrides. This is reset Index: libobjc/ChangeLog =================================================================== --- libobjc/ChangeLog (revision 192622) +++ libobjc/ChangeLog (working copy) @@ -1,3 +1,11 @@ +2012-10-19 Michael Meissner <meissner@linux.vnet.ibm.com> + + * encoding.c (TARGET_VSX): Provide definitions based on the + current compilation options, and not based off the target options + structure. + (TARGET_ALTIVEC): Likewise. + (TARGET_64BIT): Likewise. + 2012-09-14 David Edelsohn <dje.gcc@gmail.com> * configure: Regenerated. -- Michael Meissner, IBM 5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA meissner@linux.vnet.ibm.com fax +1 (978) 399-6899 ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f 2012-10-19 19:52 ` Michael Meissner @ 2012-10-20 6:42 ` Mike Stump 0 siblings, 0 replies; 13+ messages in thread From: Mike Stump @ 2012-10-20 6:42 UTC (permalink / raw) To: Michael Meissner Cc: Dominique Dhumieres, meissner, ebotcazou, gcc-patches, dje.gcc Thanks. ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] Rs6000 infrastructure cleanup (switches) @ 2012-09-12 22:44 Michael Meissner 2012-09-17 19:52 ` [PATCH] Rs6000 infrastructure cleanup (switches), revised patch Michael Meissner 0 siblings, 1 reply; 13+ messages in thread From: Michael Meissner @ 2012-09-12 22:44 UTC (permalink / raw) To: gcc-patches, dje.gcc, bergner, segher [-- Attachment #1: Type: text/plain, Size: 7537 bytes --] The following patches tackle an issue that David and I have been encountering and working around for 15 years or so in the rs6000 port. The basic problem is that we have long ago overflowed the 31 bits you get in target_flags, and different options have been moved to external variables. I encountered it again with some work for future products, and the other powerpc hackers have run into from time to time. So I figured it was time to fix it 'the right way'. This patch moves all of the target_flags options to a 64-bit flag word (rs6000_isa_flags), and added two more sets of flags (rs6000_misc_flags and rs6000_debug_flags) for the options that don't need to be specified as ISA bits. I have most of the remaining options converted to use these three flag words, but there are still some options unconverted. At the moment, we are using 35 bits in rs6000_isa_flags, 14 bits in rs6000_misc_flags, and 8 bits in rs6000_debug_flags. I have done a bootstrap test with no regressions on a SLES 11SP1 powerpc linux64 system. It would be nice to know if this doesn't break the other ppc environments (AIX, Darwin) before I commit it. Are there any problems with this patch? I have a little cleanup I want to do (fix rs6000-cpus.def so it uses OPTION_MASK_<xxx> consistantly, rather than the old MASK_<xxx> names, and maybe tackle the other switches), but I could check in the current patches and then work on the cleanup. 2012-09-12 Michael Meissner <meissner@linux.vnet.ibm.com> * common/config/rs6000/rs6000-common.c (rs6000_handle_option): Move all switches that set target_flags to set rs6000_isa_flags, and make it HOST_WIDE_INT. Make SPE/paired floating point ISA bits once again. Move other switches that were previously separate variables back as option bits, and add rs6000_misc_flags and rs6000_debug_flags. Save/restore new option words. Change MASK_<xxx> to OPTION_MASK_<xxx>. Add TARGET_<xxx> maps for OPTION_<xxx>. Move -mdebug=xxx handling to rs6000.opt file. Add rs6000-cpus.def as rs6000.o dependency. Use rs6000_isa_options for all builtins. Print more debug output for -mdebug=reg. Move masks for different cpu levels to rs6000-cpus.def. Move branch hint, align branch targets, and schedule groups to tune flags in rs6000-cpus.def. * config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/linux.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * config/rs6000/t-rs6000 (rs6000.o): Likewise. * config/rs6000/eabi.h (TARGET_DEFAULT): Likewise. * config/rs6000/eabispe.h (TARGET_DEFAULT): Likewise. * config/rs6000/eabialtivec.h (TARGET_DEFAULT): Likewise. * config/rs6000/darwin64.h (TARGET_DEFAULT): Likewise. * config/rs6000/default64.h (TARGET_DEFAULT): Likewise. * config/rs6000/linuxaltivec.h (TARGET_DEFAULT): Likewise. * config/rs6000/darwin.h (TARGET_DEFAULT): Likewise. * config/rs6000/sysv4le.h (TARGET_DEFAULT): Likewis.e * config/rs6000/xfpu.h (TARGET_DEFAULT): Likewise. * config/rs6000/eabispe.h (TARGET_DEFAULT): Likewise. * config/rs6000/vxworks.h (TARGET_DEFAULT): Likewise. * config/rs6000/rs6000.opt (most options): Likewise. * config/rs6000/sysv4.opt (most options): Likewise. * config/rs6000/darwin64.opt (most options): Likewise. * config/rs6000/aix64.opt (most options): Likewise. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. (rs6000_cpu_cpp_builtins): Likewise. * config/rs6000/rs6000-builtin.def (all BU_* macros): Likewise. * config/rs6000/linux64.h (DEFAULT_ARCH64_P): Likewise. (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/freebsd64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/rs6000.c (struct builtin_description): Likewise. (rs6000_target_modify_macros_ptr): Likewise. (struct processor_costs): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (ISA_2_6_MASKS_EMBEDDED): Likewise. (ISA_2_6_MASKS_SERVER): Likewise. (struct rs6000_ptt): Likewise. (DEBUG_FMT_LX): Likewise. (DEBUG_FMT_LX2): Likewise. (rs6000_debug_reg_global): Likewise. (darwin_rs6000_override_options): Likewise. (rs6000_builtin_mask_calculate): Likewise. (rs6000_operand_tuning_flag): Likewise. (rs6000_option_override_internal): Likewise. (altivec_expand_dst_builtin): Likewise. (paired_expand_builtin): Likewise. (bdesc_2arg_spe): Likewise. (spe_expand_builtin): Likewise. (rs6000_invalid_builtin): Likewise. (rs6000_expand_builtin): Likewise. (rs6000_builtin_decl): Likewise. (rs0600_common_init_builtins): Likewise. (rs6000_darwin_file_start): Likewise. (rs6000_final_prescan_insn): Likewise. (rs6000_opt_masks): Likewise. (rs6000_opt_vars): Likewise. (rs6000_inner_target_options): Likewise. (rs6000_pragma_target_parse): Likewise. (rs6000_function_specific_save): Likewise. (rs6000_function_specific_resotre): Likewise. (rs6000_function_specific_print): Likewise. (rs6000_print_isa_options): Likewise. (rs6000_print_isa_vars): Likewise. (rs6000_can_inline_p): Likewise. * config/rs6000/750cl.h (TARGET_PAIRED_FLOAT): Likewise. (TARGET_USES_PAIRED_FLOAT): Likewise. * config/rs6000/rs6000.h (TARGET_*): Likewise. (MASK_DEBUG_*): Likewise. (ALL_DEBUG_MASKS): Likewise. (RS6000_BTM_*): Likewise. * config/rs6000/aix64.opt (-maix64): Likewise. (-maix32): Likewise. * config/rs6000/rs6000-cpus.def (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (ISA_2_6_MASKS_EMBEDDED): Likewise. (ISA_2_6_MASKS_SERVER): Likewise. (POWER_BASE_MASK): Likewise. (POWER4_ISA_MASK): Likewise. (POWER4_TUNE_MASK): Likewsie. (POWER5_ISA_MASK): Likewise. (POWER5P_ISA_MASK): Likewise. (POWER5_TUNE_MASK): Likewsie. (POWER6_ISA_MASK): Likewise. (POWER6X_ISA_MASK): Likewise. (POWER6_TUNE_MASK): Likewsie. (POWER7_ISA_MASK): Likewise. (POWER7_TUNE_MASK): Likewsie. (MASK_*): Likewise. (476 cpu): Likewise. (476fp cpu): Likewise. (8540 cpu): Likewise. (8548 cpu): Likewise. (a2 cpu): Likewise. (e500mc cpu): Likewise. (e500mc64 cpu): Likewise. (e5500 cpu): Likewise. (e6500 cpu): Likewise. (970 cpu): Likewise. (cell cpu): Likewise. (G5 cpu): Likewise. (power4 cpu): Likewise. (power5 cpu): Likewise. (power5+ cpu): Likewise. (power6 cpu): Likewise. (power6x cpu): Likewise. (power7 cpu): Likewise. * config/rs6000/e500.h (TARGET_USES_SPE): Likewise. (TARGET_SPE): Likewise. * config/rs6000/option-defaults.h (OPTION_MASK_64BIT): Likewise. * config/rs6000/rs6000-protos.h (rs6000_builtin_mask_calculate): Likewise. (rs6000_target_modify_macros): Likewise. (rs6000_target_modify_macros_ptr): Likewise. * config/rs6000/sysv4.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (TARGET_OS_SYSV_CPP_BUILTINS): Likewise. -- Michael Meissner, IBM 5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA meissner@linux.vnet.ibm.com fax +1 (978) 399-6899 [-- Attachment #2: gcc-power7.patch349b --] [-- Type: text/plain, Size: 132616 bytes --] Index: gcc/common/config/rs6000/rs6000-common.c =================================================================== --- gcc/common/config/rs6000/rs6000-common.c (revision 191198) +++ gcc/common/config/rs6000/rs6000-common.c (working copy) @@ -74,7 +74,6 @@ rs6000_handle_option (struct gcc_options location_t loc) { enum fpu_type_t fpu_type = FPU_NONE; - char *p, *q; size_t code = decoded->opt_index; const char *arg = decoded->arg; int value = decoded->value; @@ -82,23 +81,23 @@ rs6000_handle_option (struct gcc_options switch (code) { case OPT_mfull_toc: - opts->x_target_flags &= ~MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_MINIMAL_TOC; opts->x_TARGET_NO_FP_IN_TOC = 0; opts->x_TARGET_NO_SUM_IN_TOC = 0; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; #ifdef TARGET_USES_SYSV4_OPT /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be just the same as -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; #endif break; #ifdef TARGET_USES_SYSV4_OPT case OPT_mtoc: /* Make -mtoc behave like -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; break; #endif @@ -107,9 +106,10 @@ rs6000_handle_option (struct gcc_options #else case OPT_m64: #endif - opts->x_target_flags |= MASK_POWERPC64; - opts->x_target_flags |= ~opts_set->x_target_flags & MASK_PPC_GFXOPT; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; + opts->x_rs6000_isa_flags |= (~opts_set->x_rs6000_isa_flags + & OPTION_MASK_PPC_GFXOPT); + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; #ifdef TARGET_USES_AIX64_OPT @@ -117,8 +117,8 @@ rs6000_handle_option (struct gcc_options #else case OPT_m32: #endif - opts->x_target_flags &= ~MASK_POWERPC64; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_POWERPC64; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; case OPT_mminimal_toc: @@ -129,60 +129,12 @@ rs6000_handle_option (struct gcc_options } break; - case OPT_mpowerpc_gpopt: - case OPT_mpowerpc_gfxopt: - break; - - case OPT_mdebug_: - p = ASTRDUP (arg); - opts->x_rs6000_debug = 0; - - while ((q = strtok (p, ",")) != NULL) - { - unsigned mask = 0; - bool invert; - - p = NULL; - if (*q == '!') - { - invert = true; - q++; - } - else - invert = false; - - if (! strcmp (q, "all")) - mask = MASK_DEBUG_ALL; - else if (! strcmp (q, "stack")) - mask = MASK_DEBUG_STACK; - else if (! strcmp (q, "arg")) - mask = MASK_DEBUG_ARG; - else if (! strcmp (q, "reg")) - mask = MASK_DEBUG_REG; - else if (! strcmp (q, "addr")) - mask = MASK_DEBUG_ADDR; - else if (! strcmp (q, "cost")) - mask = MASK_DEBUG_COST; - else if (! strcmp (q, "target")) - mask = MASK_DEBUG_TARGET; - else if (! strcmp (q, "builtin")) - mask = MASK_DEBUG_BUILTIN; - else - error_at (loc, "unknown -mdebug-%s switch", q); - - if (invert) - opts->x_rs6000_debug &= ~mask; - else - opts->x_rs6000_debug |= mask; - } - break; - #ifdef TARGET_USES_SYSV4_OPT case OPT_mrelocatable: if (value == 1) { - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; opts->x_TARGET_NO_FP_IN_TOC = 1; } break; @@ -190,14 +142,16 @@ rs6000_handle_option (struct gcc_options case OPT_mrelocatable_lib: if (value == 1) { - opts->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); + opts_set->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); opts->x_TARGET_NO_FP_IN_TOC = 1; } else { - opts->x_target_flags &= ~MASK_RELOCATABLE; - opts_set->x_target_flags |= MASK_RELOCATABLE; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_RELOCATABLE; } break; #endif @@ -207,9 +161,11 @@ rs6000_handle_option (struct gcc_options opts->x_rs6000_spe_abi = 0; break; +#if TARGET_USES_SPE case OPT_mabi_spe: opts->x_rs6000_altivec_abi = 0; break; +#endif case OPT_mlong_double_: if (value != 64 && value != 128) @@ -227,15 +183,15 @@ rs6000_handle_option (struct gcc_options "-msingle-float option equivalent to -mhard-float"); /* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_double_float = 0; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_mdouble_float: /* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_single_float = 1; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_msimple_fpu: @@ -259,9 +215,12 @@ rs6000_handle_option (struct gcc_options { /* If -mfpu is not none, then turn off SOFT_FLOAT, turn on HARD_FLOAT. */ - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; - opts->x_rs6000_xilinx_fpu = 1; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; +#if TARGET_USES_XILINX_FPU + opts->x_rs6000_isa_flags |= OPTION_MASK_XILINX_FPU; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_XILINX_FPU; +#endif if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL) opts->x_rs6000_single_float = 1; if (fpu_type == FPU_DF_LITE || fpu_type == FPU_DF_FULL) @@ -272,8 +231,8 @@ rs6000_handle_option (struct gcc_options else { /* -mfpu=none is equivalent to -msoft-float. */ - opts->x_target_flags |= MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0; } break; @@ -281,6 +240,31 @@ rs6000_handle_option (struct gcc_options case OPT_mrecip: opts->x_rs6000_recip_name = (value) ? "default" : "none"; break; + + /* Note, the compiler must be configured explicitly for spe, paired, and + xilinx support. */ +#if !TARGET_USES_SPE + case OPT_mabi_no_spe: + case OPT_mabi_spe: + error ("not configured for SPE ABI"); + break; + + case OPT_mspe: + error ("not configured for SPE instruction set"); + break; +#endif + +#if !TARGET_USES_PAIRED_FLOAT + case OPT_mpaired: + error ("not configured for the 750CL paired floating point"); + break; +#endif + +#if !TARGET_USES_XILINX_FPU + case OPT_mxilinx_fpu: + error ("not configured for the xilinx_fpu"); + break; +#endif } return true; } @@ -297,8 +281,4 @@ rs6000_handle_option (struct gcc_options #undef TARGET_OPTION_OPTIMIZATION_TABLE #define TARGET_OPTION_OPTIMIZATION_TABLE rs6000_option_optimization_table -#undef TARGET_DEFAULT_TARGET_FLAGS -#define TARGET_DEFAULT_TARGET_FLAGS \ - (TARGET_DEFAULT) - struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; Index: gcc/config/rs6000/aix53.h =================================================================== --- gcc/config/rs6000/aix53.h (revision 191198) +++ gcc/config/rs6000/aix53.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/linux.h =================================================================== --- gcc/config/rs6000/linux.h (revision 191198) +++ gcc/config/rs6000/linux.h (working copy) @@ -109,7 +109,7 @@ -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #define TARGET_POSIX_IO Index: gcc/config/rs6000/eabi.h =================================================================== --- gcc/config/rs6000/eabi.h (revision 191198) +++ gcc/config/rs6000/eabi.h (working copy) @@ -21,7 +21,7 @@ /* Add -meabi to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_EABI +#define TARGET_DEFAULT OPTION_MASK_EABI /* Invoke an initializer function to set up the GOT. */ #define NAME__MAIN "__eabi" Index: gcc/config/rs6000/t-rs6000 =================================================================== --- gcc/config/rs6000/t-rs6000 (revision 191198) +++ gcc/config/rs6000/t-rs6000 (working copy) @@ -26,7 +26,9 @@ rs6000.o: $(CONFIG_H) $(SYSTEM_H) corety $(OBSTACK_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) except.h function.h \ output.h dbxout.h $(BASIC_BLOCK_H) toplev.h $(GGC_H) $(HASHTAB_H) \ $(TM_P_H) $(TARGET_H) $(TARGET_DEF_H) langhooks.h reload.h gt-rs6000.h \ - cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) + cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) \ + $(srcdir)/config/rs6000/rs6000-builtin.def \ + $(srcdir)/config/rs6000/rs6000-cpus.def rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.c \ $(srcdir)/config/rs6000/rs6000-protos.h \ Index: gcc/config/rs6000/linuxspe.h =================================================================== --- gcc/config/rs6000/linuxspe.h (revision 191198) +++ gcc/config/rs6000/linuxspe.h (working copy) @@ -21,7 +21,7 @@ /* Override rs6000.h and sysv4.h definition. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_STRICT_ALIGN +#define TARGET_DEFAULT OPTION_MASK_STRICT_ALIGN #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc -mspe -me500" Index: gcc/config/rs6000/eabialtivec.h =================================================================== --- gcc/config/rs6000/eabialtivec.h (revision 191198) +++ gcc/config/rs6000/eabialtivec.h (working copy) @@ -21,7 +21,7 @@ /* Add -meabi and -maltivec to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_EABI | MASK_ALTIVEC) +#define TARGET_DEFAULT (OPTION_MASK_EABI | OPTION_MASK_ALTIVEC) #undef SUBSUBTARGET_OVERRIDE_OPTIONS #define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1 Index: gcc/config/rs6000/aix43.h =================================================================== --- gcc/config/rs6000/aix43.h (revision 191198) +++ gcc/config/rs6000/aix43.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/darwin64.h =================================================================== --- gcc/config/rs6000/darwin64.h (revision 191198) +++ gcc/config/rs6000/darwin64.h (working copy) @@ -19,8 +19,8 @@ <http://www.gnu.org/licenses/>. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \ - | MASK_MULTIPLE | MASK_PPC_GFXOPT) +#define TARGET_DEFAULT (OPTION_MASK_POWERPC64 | OPTION_MASK_64BIT \ + | OPTION_MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT) #undef DARWIN_ARCH_SPEC #define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}" Index: gcc/config/rs6000/default64.h =================================================================== --- gcc/config/rs6000/default64.h (revision 191198) +++ gcc/config/rs6000/default64.h (working copy) @@ -19,4 +19,5 @@ along with GCC; see the file COPYING3. <http://www.gnu.org/licenses/>. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_64BIT) +#define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_POWERPC64 \ + | OPTION_MASK_64BIT) Index: gcc/config/rs6000/darwin.opt =================================================================== --- gcc/config/rs6000/darwin.opt (revision 191198) +++ gcc/config/rs6000/darwin.opt (working copy) @@ -34,9 +34,9 @@ findirect-data Driver RejectNegative Alias(mfix-and-continue) m64 -Target RejectNegative Negative(m32) Mask(64BIT) +Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target RejectNegative Negative(m64) InverseMask(64BIT) +Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code Index: gcc/config/rs6000/rs6000.opt =================================================================== --- gcc/config/rs6000/rs6000.opt (revision 191198) +++ gcc/config/rs6000/rs6000.opt (working copy) @@ -22,6 +22,39 @@ HeaderInclude config/rs6000/rs6000-opts.h +;; ISA flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags + +;; Miscellaneous flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags_explicit + +;; Miscellaneous flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_misc_flags = TARGET_MISC_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_misc_flags + +;; Miscellaneous flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_misc_flags_explicit + +;; Debug flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_debug_flags = TARGET_DEBUG_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_debug_flags + +;; Debug flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_debug_flags_explicit + ;; Current processor TargetVariable enum processor_type rs6000_cpu = PROCESSOR_PPC603 @@ -80,161 +113,161 @@ unsigned int rs6000_recip_control ;; Mask of what builtin functions are allowed TargetVariable -unsigned int rs6000_builtin_mask +HOST_WIDE_INT rs6000_builtin_mask ;; Debug flags TargetVariable unsigned int rs6000_debug -;; Save for target_flags_explicit -TargetSave -int rs6000_target_flags_explicit - ;; This option existed in the past, but now is always on. mpowerpc Target RejectNegative Undocumented Ignore mpowerpc64 -Target Report Mask(POWERPC64) +Target Report Mask(POWERPC64) Var(rs6000_isa_flags) Use PowerPC-64 instruction set mpowerpc-gpopt -Target Report Mask(PPC_GPOPT) Save +Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) Use PowerPC General Purpose group optional instructions mpowerpc-gfxopt -Target Report Mask(PPC_GFXOPT) Save +Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) Use PowerPC Graphics group optional instructions mmfcrf -Target Report Mask(MFCRF) Save +Target Report Mask(MFCRF) Var(rs6000_isa_flags) Use PowerPC V2.01 single field mfcr instruction mpopcntb -Target Report Mask(POPCNTB) Save +Target Report Mask(POPCNTB) Var(rs6000_isa_flags) Use PowerPC V2.02 popcntb instruction mfprnd -Target Report Mask(FPRND) Save +Target Report Mask(FPRND) Var(rs6000_isa_flags) Use PowerPC V2.02 floating point rounding instructions mcmpb -Target Report Mask(CMPB) Save +Target Report Mask(CMPB) Var(rs6000_isa_flags) Use PowerPC V2.05 compare bytes instruction mmfpgpr -Target Report Mask(MFPGPR) Save +Target Report Mask(MFPGPR) Var(rs6000_isa_flags) Use extended PowerPC V2.05 move floating point to/from GPR instructions maltivec -Target Report Mask(ALTIVEC) Save +Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) Use AltiVec instructions mhard-dfp -Target Report Mask(DFP) Save +Target Report Mask(DFP) Var(rs6000_isa_flags) Use decimal floating point instructions mmulhw -Target Report Mask(MULHW) Save +Target Report Mask(MULHW) Var(rs6000_isa_flags) Use 4xx half-word multiply instructions mdlmzb -Target Report Mask(DLMZB) Save +Target Report Mask(DLMZB) Var(rs6000_isa_flags) Use 4xx string-search dlmzb instruction mmultiple -Target Report Mask(MULTIPLE) Save +Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) Generate load/store multiple instructions mstring -Target Report Mask(STRING) Save +Target Report Mask(STRING) Var(rs6000_isa_flags) Generate string instructions for block moves msoft-float -Target Report RejectNegative Mask(SOFT_FLOAT) +Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) Do not use hardware floating point mhard-float -Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) +Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) Use hardware floating point mpopcntd -Target Report Mask(POPCNTD) Save +Target Report Mask(POPCNTD) Var(rs6000_isa_flags) Use PowerPC V2.06 popcntd instruction +mno-friz +Target Report RejectNegative Mask(NO_FRIZ) Var(rs6000_isa_flags) +Under -ffast-math, do not generate a FRIZ instruction for (double)(long long) conversions + mfriz -Target Report Var(TARGET_FRIZ) Init(-1) Save +Target Report RejectNegative InverseMask(NO_FRIZ, FRIZ) Var(rs6000_isa_flags) Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions +mcell-builtins +Target Undocumented Report Mask(CELL_BUILTIN) Var(rs6000_isa_flags) +; Enable cell builtins + mveclibabi= Target RejectNegative Joined Var(rs6000_veclibabi_name) Vector library ABI to use mvsx -Target Report Mask(VSX) Save +Target Report Mask(VSX) Var(rs6000_isa_flags) Use vector/scalar (VSX) instructions mvsx-scalar-double -Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1) +Target Report Undocumented Mask(VSX_SCALAR_DOUBLE) Var(rs6000_misc_flags) ; If -mvsx, use VSX arithmetic instructions for scalar double (on by default) mvsx-scalar-memory -Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY) +Target Report Undocumented Mask(VSX_SCALAR_MEMORY) Var(rs6000_misc_flags) ; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default) mvsx-align-128 -Target Undocumented Report Var(TARGET_VSX_ALIGN_128) +Target Report Undocumented Mask(VSX_ALIGN_128) Var(rs6000_misc_flags) ; If -mvsx, set alignment to 128 bits instead of 32/64 mallow-movmisalign -Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) +Target Report Undocumented Mask(ALLOW_MOVMISALIGN) Var(rs6000_misc_flags) ; Allow/disallow the movmisalign in DF/DI vectors -mallow-df-permute -Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) -; Allow/disallow permutation of DF/DI vectors - msched-groups -Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) +Target Undocumented Report Mask(SCHED_GROUPS) Var(rs6000_isa_flags) ; Explicitly set/unset whether rs6000_sched_groups is set malways-hint -Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) +Target Undocumented Report InverseMask(NO_HINT) Var(rs6000_isa_flags) ; Explicitly set/unset whether rs6000_always_hint is set malign-branch-targets -Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) +Target Undocumented Report Mask(ALIGN_BRANCH_TARGETS) Var(rs6000_isa_flags) ; Explicitly set/unset whether rs6000_align_branch_targets is set mvectorize-builtins -Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) +Target Undocumented Report Mask(VECTORIZE_BUILTINS) Var(rs6000_misc_flags) ; Explicitly control whether we vectorize the builtins or not. mno-update -Target Report RejectNegative Mask(NO_UPDATE) Save +Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) Do not generate load/store with update instructions mupdate -Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) +Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) Generate load/store with update instructions msingle-pic-base -Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0) +Target Report Mask(SINGLE_PIC_BASE) Var(rs6000_misc_flags) Do not load the PIC register in function prologues mavoid-indexed-addresses -Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save +Target Report Mask(AVOID_XFORM) Var(rs6000_isa_flags) Avoid generation of indexed load/store instructions when possible mtls-markers -Target Report Var(tls_markers) Init(1) Save +Target Report Mask(TLS_MARKERS) Var(rs6000_misc_flags) Mark __tls_get_addr calls with argument info msched-epilog -Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save +Target Report Undocumented Mask(SCHED_PROLOG) Var(rs6000_misc_flags) msched-prolog -Target Report Var(TARGET_SCHED_PROLOG) Save +Target Report Mask(SCHED_PROLOG) Var(rs6000_misc_flags) Schedule the start and end of the procedure maix-struct-return @@ -246,7 +279,7 @@ Target Report RejectNegative Var(aix_str Return small structures in registers (SVR4 default) mxl-compat -Target Report Var(TARGET_XL_COMPAT) Save +Target Report Mask(XL_COMPAT) Var(rs6000_misc_flags) Conform more closely to IBM XLC semantics mrecip @@ -258,7 +291,7 @@ Target Report RejectNegative Joined Var( Generate software reciprocal divide and square root for better throughput. mrecip-precision -Target Report Mask(RECIP_PRECISION) Save +Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) Assume that the reciprocal estimate instructions provide more accuracy. mno-fp-in-toc @@ -285,7 +318,7 @@ Place symbol+offset constants in TOC ; This is at the cost of having 2 extra loads and one extra store per ; function, and one less allocable register. mminimal-toc -Target Report Mask(MINIMAL_TOC) +Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) Use only one TOC entry per procedure mfull-toc @@ -293,7 +326,7 @@ Target Report Put everything in the regular TOC mvrsave -Target Report Var(TARGET_ALTIVEC_VRSAVE) Save +Target Report Mask(ALTIVEC_VRSAVE) Var(rs6000_misc_flags) Generate VRSAVE instructions when generating AltiVec code mvrsave=no @@ -309,7 +342,7 @@ Target Report Var(rs6000_block_move_inli Specify how many bytes should be moved inline before calling out to memcpy/memmove misel -Target Report Mask(ISEL) Save +Target Report Mask(ISEL) Var(rs6000_isa_flags) Generate isel instructions misel=no @@ -321,13 +354,9 @@ Target RejectNegative Alias(misel) Deprecated option. Use -misel instead mspe -Target Var(rs6000_spe) Save +Target Report Mask(SPE) Var(rs6000_isa_flags) Generate SPE SIMD instructions on E500 -mpaired -Target Var(rs6000_paired_float) Save -Generate PPC750CL paired-single instructions - mspe=no Target RejectNegative Alias(mspe) NegativeAlias Deprecated option. Use -mno-spe instead @@ -336,9 +365,54 @@ mspe=yes Target RejectNegative Alias(mspe) Deprecated option. Use -mspe instead -mdebug= -Target RejectNegative Joined --mdebug= Enable debug output +mpaired +Target Report Mask(PAIRED_FLOAT) Var(rs6000_isa_flags) +Generate PPC750CL paired-single instructions + +mdebug=all +Target Report RejectNegative Undocumented Mask(DEBUG_ALL) Var(rs6000_debug_flags) + +mdebug=addr +Target Report RejectNegative Undocumented Mask(DEBUG_ADDR) Var(rs6000_debug_flags) + +mdebug=noaddr +Target Report RejectNegative Undocumented InverseMask(DEBUG_ADDR) Var(rs6000_debug_flags) + +mdebug=arg +Target Report RejectNegative Undocumented Mask(DEBUG_ARG) Var(rs6000_debug_flags) + +mdebug=noarg +Target Report RejectNegative Undocumented InverseMask(DEBUG_ARG) Var(rs6000_debug_flags) + +mdebug=builtin +Target Report RejectNegative Undocumented Mask(DEBUG_BUILTIN) Var(rs6000_debug_flags) + +mdebug=nobuiltin +Target Report RejectNegative Undocumented InverseMask(DEBUG_BUILTIN) Var(rs6000_debug_flags) + +mdebug=cost +Target Report RejectNegative Undocumented Mask(DEBUG_COST) Var(rs6000_debug_flags) + +mdebug=nocost +Target Report RejectNegative Undocumented InverseMask(DEBUG_COST) Var(rs6000_debug_flags) + +mdebug=reg +Target Report RejectNegative Undocumented Mask(DEBUG_REG) Var(rs6000_debug_flags) + +mdebug=noreg +Target Report RejectNegative Undocumented InverseMask(DEBUG_REG) Var(rs6000_debug_flags) + +mdebug=stack +Target Report RejectNegative Undocumented Mask(DEBUG_STACK) Var(rs6000_debug_flags) + +mdebug=nostack +Target Report RejectNegative Undocumented InverseMask(DEBUG_STACK) Var(rs6000_debug_flags) + +mdebug=target +Target Report RejectNegative Undocumented Mask(DEBUG_TARGET) Var(rs6000_debug_flags) + +mdebug=notarget +Target Report RejectNegative Undocumented InverseMask(DEBUG_TARGET) Var(rs6000_debug_flags) mabi=altivec Target RejectNegative Var(rs6000_altivec_abi) Save @@ -497,13 +571,13 @@ EnumValue Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL) mxilinx-fpu -Target Var(rs6000_xilinx_fpu) Save +Target Report Var(rs6000_isa_flags) Mask(XILINX_FPU) Specify Xilinx FPU. mpointers-to-nested-functions -Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save +Target Report Mask(POINTERS_TO_NESTED_FUNCTIONS) Var(rs6000_misc_flags) Use/do not use r11 to hold the static link in calls to functions via pointers. msave-toc-indirect -Target Report Var(TARGET_SAVE_TOC_INDIRECT) Save +Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_misc_flags) Control whether we save the TOC in the prologue for indirect calls or generate the save inline Index: gcc/config/rs6000/rs6000-c.c =================================================================== --- gcc/config/rs6000/rs6000-c.c (revision 191198) +++ gcc/config/rs6000/rs6000-c.c (working copy) @@ -285,38 +285,38 @@ rs6000_define_or_undefine_macro (bool de have both the target flags and the builtin flags as arguments. */ void -rs6000_target_modify_macros (bool define_p, int flags, unsigned bu_mask) +rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) { if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) - fprintf (stderr, "rs6000_target_modify_macros (%s, 0x%x, 0x%x)\n", + fprintf (stderr, "rs6000_target_modify_macros (%s, 0x%lx)\n", (define_p) ? "define" : "undef", - (unsigned) flags, bu_mask); + (unsigned long) flags); - /* target_flags based options. */ + /* rs6000_isa_flags based options. */ rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); - if ((flags & MASK_PPC_GPOPT) != 0) + if ((flags & OPTION_MASK_PPC_GPOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ"); - if ((flags & MASK_PPC_GFXOPT) != 0) + if ((flags & OPTION_MASK_PPC_GFXOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR"); - if ((flags & MASK_POWERPC64) != 0) + if ((flags & OPTION_MASK_POWERPC64) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"); - if ((flags & MASK_MFCRF) != 0) + if ((flags & OPTION_MASK_MFCRF) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4"); - if ((flags & MASK_POPCNTB) != 0) + if ((flags & OPTION_MASK_POPCNTB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5"); - if ((flags & MASK_FPRND) != 0) + if ((flags & OPTION_MASK_FPRND) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X"); - if ((flags & MASK_CMPB) != 0) + if ((flags & OPTION_MASK_CMPB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); - if ((flags & MASK_MFPGPR) != 0) + if ((flags & OPTION_MASK_MFPGPR) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X"); - if ((flags & MASK_POPCNTD) != 0) + if ((flags & OPTION_MASK_POPCNTD) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); - if ((flags & MASK_SOFT_FLOAT) != 0) + if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); - if ((flags & MASK_RECIP_PRECISION) != 0) + if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__"); - if ((flags & MASK_ALTIVEC) != 0) + if ((flags & OPTION_MASK_ALTIVEC) != 0) { const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__"; rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__"); @@ -326,15 +326,15 @@ rs6000_target_modify_macros (bool define if (!flag_iso) rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__"); } - if ((flags & MASK_VSX) != 0) + if ((flags & OPTION_MASK_VSX) != 0) rs6000_define_or_undefine_macro (define_p, "__VSX__"); /* options from the builtin masks. */ - if ((bu_mask & RS6000_BTM_SPE) != 0) + if ((flags & OPTION_MASK_SPE) != 0) rs6000_define_or_undefine_macro (define_p, "__SPE__"); - if ((bu_mask & RS6000_BTM_PAIRED) != 0) + if ((flags & OPTION_MASK_PAIRED_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "__PAIRED__"); - if ((bu_mask & RS6000_BTM_CELL) != 0) + if ((flags & OPTION_MASK_CELL_BUILTIN) != 0) rs6000_define_or_undefine_macro (define_p, "__PPU__"); } @@ -342,8 +342,7 @@ void rs6000_cpu_cpp_builtins (cpp_reader *pfile) { /* Define all of the common macros. */ - rs6000_target_modify_macros (true, target_flags, - rs6000_builtin_mask_calculate ()); + rs6000_target_modify_macros (true, rs6000_isa_flags); if (TARGET_FRE) builtin_define ("__RECIP__"); @@ -463,7 +462,7 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfi builtin_define ("__NO_FPRS__"); /* Generate defines for Xilinx FPU. */ - if (rs6000_xilinx_fpu) + if (TARGET_XILINX_FPU) { builtin_define ("_XFPU"); if (rs6000_single_float && ! rs6000_double_float) Index: gcc/config/rs6000/rs6000-builtin.def =================================================================== --- gcc/config/rs6000/rs6000-builtin.def (revision 191198) +++ gcc/config/rs6000/rs6000-builtin.def (working copy) @@ -90,7 +90,7 @@ #define BU_ALTIVEC_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -98,7 +98,7 @@ #define BU_ALTIVEC_2(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_2 (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -106,7 +106,7 @@ #define BU_ALTIVEC_3(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_3 (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -114,7 +114,7 @@ #define BU_ALTIVEC_A(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_A (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_ABS), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -122,7 +122,7 @@ #define BU_ALTIVEC_D(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_D (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_DST), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -130,7 +130,7 @@ #define BU_ALTIVEC_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_P (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -138,7 +138,7 @@ #define BU_ALTIVEC_X(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -146,8 +146,8 @@ #define BU_ALTIVEC_C(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - (RS6000_BTM_ALTIVEC /* MASK */ \ - | RS6000_BTM_CELL), \ + (OPTION_MASK_ALTIVEC /* MASK */ \ + | OPTION_MASK_CELL_BUILTIN), \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -156,7 +156,7 @@ #define BU_ALTIVEC_OVERLOAD_1(ENUM, NAME) \ RS6000_BUILTIN_1 (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -164,7 +164,7 @@ #define BU_ALTIVEC_OVERLOAD_2(ENUM, NAME) \ RS6000_BUILTIN_2 (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_nothing) /* ICODE */ @@ -172,7 +172,7 @@ #define BU_ALTIVEC_OVERLOAD_3(ENUM, NAME) \ RS6000_BUILTIN_3 (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -180,7 +180,7 @@ #define BU_ALTIVEC_OVERLOAD_A(ENUM, NAME) \ RS6000_BUILTIN_A (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_ABS), \ CODE_FOR_nothing) /* ICODE */ @@ -188,7 +188,7 @@ #define BU_ALTIVEC_OVERLOAD_D(ENUM, NAME) \ RS6000_BUILTIN_D (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_DST), \ CODE_FOR_nothing) /* ICODE */ @@ -196,7 +196,7 @@ #define BU_ALTIVEC_OVERLOAD_P(ENUM, NAME) \ RS6000_BUILTIN_P (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_nothing) /* ICODE */ @@ -204,7 +204,7 @@ #define BU_ALTIVEC_OVERLOAD_X(ENUM, NAME) \ RS6000_BUILTIN_X (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -213,7 +213,7 @@ #define BU_VSX_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -221,7 +221,7 @@ #define BU_VSX_2(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_2 (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -229,7 +229,7 @@ #define BU_VSX_3(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_3 (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -237,7 +237,7 @@ #define BU_VSX_A(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_A (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_ABS), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -245,7 +245,7 @@ #define BU_VSX_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_P (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -253,7 +253,7 @@ #define BU_VSX_X(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -262,7 +262,7 @@ #define BU_VSX_OVERLOAD_1(ENUM, NAME) \ RS6000_BUILTIN_1 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -270,7 +270,7 @@ #define BU_VSX_OVERLOAD_2(ENUM, NAME) \ RS6000_BUILTIN_2 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_nothing) /* ICODE */ @@ -278,7 +278,7 @@ #define BU_VSX_OVERLOAD_3(ENUM, NAME) \ RS6000_BUILTIN_3 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -288,7 +288,7 @@ #define BU_VSX_OVERLOAD_3V(ENUM, NAME) \ RS6000_BUILTIN_3 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -296,7 +296,7 @@ #define BU_VSX_OVERLOAD_X(ENUM, NAME) \ RS6000_BUILTIN_X (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -305,7 +305,7 @@ #define BU_SPE_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -313,7 +313,7 @@ #define BU_SPE_2(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_2 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -321,7 +321,7 @@ #define BU_SPE_3(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_3 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -329,7 +329,7 @@ #define BU_SPE_E(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_E (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_EVSEL), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -337,7 +337,7 @@ #define BU_SPE_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_S (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -345,7 +345,7 @@ #define BU_SPE_X(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -354,7 +354,7 @@ #define BU_PAIRED_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -362,7 +362,7 @@ #define BU_PAIRED_2(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_2 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -370,7 +370,7 @@ #define BU_PAIRED_3(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_3 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -378,7 +378,7 @@ #define BU_PAIRED_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_Q (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -386,7 +386,7 @@ #define BU_PAIRED_X(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -1413,22 +1413,22 @@ BU_SPE_X (MTSPEFSCR, "mtspefscr", \f /* Power7 builtins, that aren't VSX instructions. */ -BU_SPECIAL_X (POWER7_BUILTIN_BPERMD, "__builtin_bpermd", RS6000_BTM_POPCNTD, +BU_SPECIAL_X (POWER7_BUILTIN_BPERMD, "__builtin_bpermd", OPTION_MASK_POPCNTD, RS6000_BTC_CONST) /* Miscellaneous builtins. */ -BU_SPECIAL_X (RS6000_BUILTIN_RECIP, "__builtin_recipdiv", RS6000_BTM_FRE, +BU_SPECIAL_X (RS6000_BUILTIN_RECIP, "__builtin_recipdiv", OPTION_MASK_POPCNTB, RS6000_BTC_FP) -BU_SPECIAL_X (RS6000_BUILTIN_RECIPF, "__builtin_recipdivf", RS6000_BTM_FRES, - RS6000_BTC_FP) +BU_SPECIAL_X (RS6000_BUILTIN_RECIPF, "__builtin_recipdivf", + OPTION_MASK_PPC_GFXOPT, RS6000_BTC_FP) -BU_SPECIAL_X (RS6000_BUILTIN_RSQRT, "__builtin_rsqrt", RS6000_BTM_FRSQRTE, - RS6000_BTC_FP) +BU_SPECIAL_X (RS6000_BUILTIN_RSQRT, "__builtin_rsqrt", + OPTION_MASK_PPC_GFXOPT, RS6000_BTC_FP) -BU_SPECIAL_X (RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf", RS6000_BTM_FRSQRTES, +BU_SPECIAL_X (RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf", OPTION_MASK_POPCNTB, RS6000_BTC_FP) /* Darwin CfString builtin. */ -BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS, +BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", 0, RS6000_BTC_MISC) Index: gcc/config/rs6000/linuxaltivec.h =================================================================== --- gcc/config/rs6000/linuxaltivec.h (revision 191198) +++ gcc/config/rs6000/linuxaltivec.h (working copy) @@ -21,7 +21,7 @@ /* Override rs6000.h and sysv4.h definition. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_ALTIVEC +#define TARGET_DEFAULT OPTION_MASK_ALTIVEC #undef SUBSUBTARGET_OVERRIDE_OPTIONS #define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1 Index: gcc/config/rs6000/linux64.h =================================================================== --- gcc/config/rs6000/linux64.h (revision 191198) +++ gcc/config/rs6000/linux64.h (working copy) @@ -37,7 +37,7 @@ #else -#define DEFAULT_ARCH64_P (TARGET_DEFAULT & MASK_64BIT) +#define DEFAULT_ARCH64_P (TARGET_DEFAULT & OPTION_MASK_64BIT) #define RS6000_BI_ARCH_P 1 #endif @@ -81,7 +81,7 @@ extern int dot_symbols; -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "linux" @@ -103,14 +103,14 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ - if (target_flags & MASK_RELOCATABLE) \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error (INVALID_64BIT, "relocatable"); \ } \ - if (target_flags & MASK_EABI) \ + if (rs6000_isa_flags & OPTION_MASK_EABI) \ { \ - target_flags &= ~MASK_EABI; \ + rs6000_isa_flags &= ~OPTION_MASK_EABI; \ error (INVALID_64BIT, "eabi"); \ } \ if (TARGET_PROTOTYPE) \ @@ -118,12 +118,13 @@ extern int dot_symbols; target_prototype = 0; \ error (INVALID_64BIT, "prototype"); \ } \ - if ((target_flags & MASK_POWERPC64) == 0) \ + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ error ("-m64 requires a PowerPC64 cpu"); \ } \ - if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ + if ((rs6000_isa_flags_explicit \ + & OPTION_MASK_MINIMAL_TOC) != 0) \ { \ if (global_options_set.x_rs6000_current_cmodel \ && rs6000_current_cmodel != CMODEL_SMALL) \ Index: gcc/config/rs6000/darwin.h =================================================================== --- gcc/config/rs6000/darwin.h (revision 191198) +++ gcc/config/rs6000/darwin.h (working copy) @@ -280,7 +280,7 @@ extern int darwin_emit_branch_islands; default as well. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_PPC_GFXOPT) +#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT) /* Darwin always uses IBM long double, never IEEE long double. */ #undef TARGET_IEEEQUAD Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 191198) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -213,7 +213,7 @@ static GTY(()) section *toc_section; struct builtin_description { - const unsigned int mask; + const HOST_WIDE_INT mask; const enum insn_code icode; const char *const name; const enum rs6000_builtins code; @@ -287,7 +287,7 @@ typedef rtx (*gen_2arg_fn_t) (rtx, rtx, /* Pointer to function (in rs6000-c.c) that can define or undefine target macros that have changed. Languages that don't support the preprocessor don't link in rs6000-c.c, so we can't call it directly. */ -void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned); +void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT); \f /* Target cpu costs. */ @@ -893,7 +893,7 @@ struct processor_costs ppca2_cost = { struct rs6000_builtin_info_type { const char *name; const enum insn_code icode; - const unsigned mask; + const HOST_WIDE_INT mask; const unsigned attr; }; @@ -1014,6 +1014,8 @@ bool (*rs6000_cannot_change_mode_class_p = rs6000_cannot_change_mode_class; const int INSN_NOT_AVAILABLE = -1; +static void rs6000_print_isa_options (FILE *, HOST_WIDE_INT); +static void rs6000_print_isa_vars (FILE *, struct cl_target_option *); /* Hash table stuff for keeping track of TOC entries. */ @@ -1115,8 +1117,8 @@ static const struct attribute_spec rs600 { NULL, 0, 0, false, false, false, NULL, false } }; \f -#ifndef MASK_STRICT_ALIGN -#define MASK_STRICT_ALIGN 0 +#ifndef OPTION_MASK_STRICT_ALIGN +#define OPTION_MASK_STRICT_ALIGN 0 #endif #ifndef TARGET_PROFILE_KERNEL #define TARGET_PROFILE_KERNEL 0 @@ -1458,53 +1460,12 @@ static const struct attribute_spec rs600 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok \f -/* Simplifications for entries below. */ - -enum { - POWERPC_7400_MASK = MASK_PPC_GFXOPT | MASK_ALTIVEC -}; - -/* Some OSs don't support saving the high part of 64-bit registers on context - switch. Other OSs don't support saving Altivec registers. On those OSs, we - don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants - either, the user must explicitly specify them and we won't interfere with - the user's specification. */ - -enum { - POWERPC_MASKS = (MASK_PPC_GPOPT | MASK_STRICT_ALIGN - | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC - | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW - | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP - | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE - | MASK_RECIP_PRECISION) -}; - -/* Masks for instructions set at various powerpc ISAs. */ -enum { - ISA_2_1_MASKS = MASK_MFCRF, - ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB), - ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND), - - /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add - ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, - fre, fsqrt, etc. were no longer documented as optional. Group masks by - server and embedded. */ - ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION - | MASK_PPC_GFXOPT | MASK_PPC_GPOPT), - ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP), - - /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but - altivec is a win so enable it. */ - ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD), - ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC - | MASK_VSX) -}; - +/* Processor table. */ struct rs6000_ptt { const char *const name; /* Canonical processor name. */ const enum processor_type processor; /* Processor type enum value. */ - const int target_enable; /* Target flags to enable. */ + const HOST_WIDE_INT target_enable; /* Target flags to enable. */ }; static struct rs6000_ptt const processor_target_table[] = @@ -1717,6 +1678,8 @@ rs6000_debug_reg_print (int first_regno, #define DEBUG_FMT_D "%-32s= %d\n" #define DEBUG_FMT_X "%-32s= 0x%x\n" +#define DEBUG_FMT_LX "%-32s= 0x%lx: " +#define DEBUG_FMT_LX2 "%-32s= 0x%lx\n" #define DEBUG_FMT_S "%-32s= %s\n" /* Print various interesting information with -mdebug=reg. */ @@ -1728,11 +1691,13 @@ rs6000_debug_reg_global (void) int m; char costly_num[20]; char nop_num[20]; + char flags_buffer[40]; const char *costly_str; const char *nop_str; const char *trace_str; const char *abi_str; const char *cmodel_str; + struct cl_target_option cl_opts; /* Map enum rs6000_vector to string. */ static const char *rs6000_debug_vector_unit[] = { @@ -1812,12 +1777,84 @@ rs6000_debug_reg_global (void) } if (rs6000_cpu_index >= 0) - fprintf (stderr, DEBUG_FMT_S, "cpu", - processor_target_table[rs6000_cpu_index].name); + { + const char *name = processor_target_table[rs6000_cpu_index].name; + fprintf (stderr, DEBUG_FMT_S, "cpu", name); + sprintf (flags_buffer, "%s cpu flags", name); + + if (processor_target_table[rs6000_cpu_index].target_enable) + { + HOST_WIDE_INT flags + = processor_target_table[rs6000_cpu_index].target_enable; + fprintf (stderr, DEBUG_FMT_LX, flags_buffer, (long)flags); + rs6000_print_isa_options (stderr, flags); + fputc ('\n', stderr); + } + else + fprintf (stderr, DEBUG_FMT_S, flags_buffer, "<none>"); + } + else + fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>"); if (rs6000_tune_index >= 0) - fprintf (stderr, DEBUG_FMT_S, "tune", - processor_target_table[rs6000_tune_index].name); + { + const char *name = processor_target_table[rs6000_tune_index].name; + fprintf (stderr, DEBUG_FMT_S, "tune", name); + sprintf (flags_buffer, "%s tune flags", name); + + if (processor_target_table[rs6000_tune_index].target_enable) + { + HOST_WIDE_INT flags + = processor_target_table[rs6000_tune_index].target_enable; + fprintf (stderr, DEBUG_FMT_LX, flags_buffer, (long)flags); + rs6000_print_isa_options (stderr, flags); + fputc ('\n', stderr); + } + else + fprintf (stderr, DEBUG_FMT_S, flags_buffer, "<none>"); + } + else + fprintf (stderr, DEBUG_FMT_S, "tune", "<none>"); + + cl_target_option_save (&cl_opts, &global_options); + if (rs6000_isa_flags) + { + fprintf (stderr, DEBUG_FMT_LX, "rs6000_isa_flags", (long)rs6000_isa_flags); + rs6000_print_isa_options (stderr, rs6000_isa_flags); + rs6000_print_isa_vars (stderr, &cl_opts); + fputc ('\n', stderr); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_isa_flags", "<none>"); + + if (rs6000_isa_flags_explicit) + { + fprintf (stderr, DEBUG_FMT_LX, "rs6000_isa_flags_explicit", + (long)rs6000_isa_flags_explicit); + rs6000_print_isa_options (stderr, rs6000_isa_flags_explicit); + rs6000_print_isa_vars (stderr, &cl_opts); + fputc ('\n', stderr); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_isa_flags_explicit", "<none>"); + + fprintf (stderr, DEBUG_FMT_LX2, "rs6000_misc_flags", rs6000_misc_flags); + fprintf (stderr, DEBUG_FMT_LX2, "rs6000_misc_flags_explicit", + rs6000_misc_flags_explicit); + fprintf (stderr, DEBUG_FMT_LX2, "rs6000_debug_flags", rs6000_debug_flags); + fprintf (stderr, DEBUG_FMT_LX2, "rs6000_debug_flags_explicit", + rs6000_debug_flags_explicit); + + if (rs6000_builtin_mask) + { + fprintf (stderr, DEBUG_FMT_LX, "rs6000_builtin_mask", + (long)rs6000_builtin_mask); + rs6000_print_isa_options (stderr, rs6000_builtin_mask); + rs6000_print_isa_vars (stderr, &cl_opts); + fputc ('\n', stderr); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_builtin_mask", "<none>"); switch (rs6000_sched_costly_dep) { @@ -1936,6 +1973,7 @@ rs6000_debug_reg_global (void) fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true"); fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]); + fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]); fprintf (stderr, DEBUG_FMT_S, "align_branch", tf[!!rs6000_align_branch_targets]); fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size); @@ -1947,7 +1985,6 @@ rs6000_debug_reg_global (void) (int)END_BUILTINS); fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins", (int)RS6000_BUILTIN_COUNT); - fprintf (stderr, DEBUG_FMT_X, "Builtin mask", rs6000_builtin_mask); } /* Initialize the various global tables that are based on register size. */ @@ -2302,7 +2339,7 @@ darwin_rs6000_override_options (void) /* The Darwin ABI always includes AltiVec, can't be (validly) turned off. */ rs6000_altivec_abi = 1; - TARGET_ALTIVEC_VRSAVE = 1; + rs6000_misc_flags |= OPTION_MASK_ALTIVEC_VRSAVE; rs6000_current_abi = ABI_DARWIN; if (DEFAULT_ABI == ABI_DARWIN @@ -2311,21 +2348,21 @@ darwin_rs6000_override_options (void) if (TARGET_64BIT && ! TARGET_POWERPC64) { - target_flags |= MASK_POWERPC64; + rs6000_isa_flags |= OPTION_MASK_POWERPC64; warning (0, "-m64 requires PowerPC64 architecture, enabling"); } if (flag_mkernel) { rs6000_default_long_calls = 1; - target_flags |= MASK_SOFT_FLOAT; + rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; } /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes Altivec. */ if (!flag_mkernel && !flag_apple_kext && TARGET_64BIT - && ! (target_flags_explicit & MASK_ALTIVEC)) - target_flags |= MASK_ALTIVEC; + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)) + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; /* Unless the user (not the configurer) has explicitly overridden it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to @@ -2333,10 +2370,10 @@ darwin_rs6000_override_options (void) if (!flag_mkernel && !flag_apple_kext && strverscmp (darwin_macosx_version_min, "10.5") >= 0 - && ! (target_flags_explicit & MASK_ALTIVEC) + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC) && ! global_options_set.x_rs6000_cpu_index) { - target_flags |= MASK_ALTIVEC; + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; } } #endif @@ -2348,26 +2385,25 @@ darwin_rs6000_override_options (void) #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64 #endif -/* Return the builtin mask of the various options used that could affect which - builtins were used. In the past we used target_flags, but we've run out of - bits, and some options like SPE and PAIRED are no longer in - target_flags. */ - -unsigned -rs6000_builtin_mask_calculate (void) -{ - return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) - | ((TARGET_VSX) ? RS6000_BTM_VSX : 0) - | ((TARGET_SPE) ? RS6000_BTM_SPE : 0) - | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0) - | ((TARGET_FRE) ? RS6000_BTM_FRE : 0) - | ((TARGET_FRES) ? RS6000_BTM_FRES : 0) - | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0) - | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0) - | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0) - | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)); +/* Helper function for rs6000_option_override_internal, that returns whether an + option is set in the tuning flags, but allow an override from the switches + if it was set explicitly. */ +static inline HOST_WIDE_INT +rs6000_operand_tuning_flag (HOST_WIDE_INT option_mask) +{ + HOST_WIDE_INT mask = rs6000_isa_flags; + + if (rs6000_tune_index >= 0 && + (rs6000_isa_flags_explicit & option_mask) == 0) + mask = processor_target_table[rs6000_tune_index].target_enable; + + return (mask & option_mask); } + /* Allow the explicit debug switches to override the tuning settings. If no + explicit switch, fall back to the tuning options instead of the cpu + options. */ + /* Override command line options. Mostly we process the processor type and sometimes adjust other TARGET_ options. */ @@ -2380,13 +2416,17 @@ rs6000_option_override_internal (bool gl /* The default cpu requested at configure time, if any. */ const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT; - int set_masks; + HOST_WIDE_INT set_masks; int cpu_index; int tune_index; struct cl_target_option *main_target_opt = ((global_init_p || target_option_default_node == NULL) ? NULL : TREE_TARGET_OPTION (target_option_default_node)); + /* If -mdebug=all, enable all debug options excepct those explicitly set. */ + if (TARGET_DEBUG_ALL) + rs6000_debug_flags |= (ALL_DEBUG_MASKS & ~rs6000_debug_flags_explicit); + /* On 64-bit Darwin, power alignment is ABI-incompatible with some C library functions, so warn about it. The flag may be useful for performance studies from time to time though, so don't disable it @@ -2417,18 +2457,24 @@ rs6000_option_override_internal (bool gl rs6000_pointer_size = 32; } - set_masks = POWERPC_MASKS | MASK_SOFT_FLOAT; + /* Some OSs don't support saving the high part of 64-bit registers on context + switch. Other OSs don't support saving Altivec registers. On those OSs, + we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings; + if the user wants either, the user must explicitly specify them and we + won't interfere with the user's specification. */ + + set_masks = POWERPC_MASKS; #ifdef OS_MISSING_POWERPC64 if (OS_MISSING_POWERPC64) - set_masks &= ~MASK_POWERPC64; + set_masks &= ~OPTION_MASK_POWERPC64; #endif #ifdef OS_MISSING_ALTIVEC if (OS_MISSING_ALTIVEC) - set_masks &= ~MASK_ALTIVEC; + set_masks &= ~OPTION_MASK_ALTIVEC; #endif /* Don't override by the processor default if given explicitly. */ - set_masks &= ~target_flags_explicit; + set_masks &= ~rs6000_isa_flags_explicit; /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed the cpu in a target attribute or pragma, but did not specify a tuning @@ -2457,9 +2503,9 @@ rs6000_option_override_internal (bool gl gcc_assert (cpu_index >= 0); - target_flags &= ~set_masks; - target_flags |= (processor_target_table[cpu_index].target_enable - & set_masks); + rs6000_isa_flags &= ~set_masks; + rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable + & set_masks); if (rs6000_tune_index >= 0) tune_index = rs6000_tune_index; @@ -2485,37 +2531,25 @@ rs6000_option_override_internal (bool gl /* Pick defaults for SPE related control flags. Do this early to make sure that the TARGET_ macros are representative ASAP. */ - { - int spe_capable_cpu = - (rs6000_cpu == PROCESSOR_PPC8540 - || rs6000_cpu == PROCESSOR_PPC8548); - - if (!global_options_set.x_rs6000_spe_abi) - rs6000_spe_abi = spe_capable_cpu; - - if (!global_options_set.x_rs6000_spe) - rs6000_spe = spe_capable_cpu; - - if (!global_options_set.x_rs6000_float_gprs) - rs6000_float_gprs = - (rs6000_cpu == PROCESSOR_PPC8540 ? 1 - : rs6000_cpu == PROCESSOR_PPC8548 ? 2 - : 0); - } + if (rs6000_cpu == PROCESSOR_PPC8540 || rs6000_cpu == PROCESSOR_PPC8548) + { + if (!global_options_set.x_rs6000_spe_abi) + rs6000_spe_abi = 1; + + if ((rs6000_isa_flags_explicit & OPTION_MASK_SPE) == 0) + rs6000_isa_flags |= OPTION_MASK_SPE; + + if (!global_options_set.x_rs6000_float_gprs) + rs6000_float_gprs = (rs6000_cpu == PROCESSOR_PPC8540) ? 1 : 2; + } + else if (!global_options_set.x_rs6000_spe_abi) + rs6000_spe_abi = 0; - if (global_options_set.x_rs6000_spe_abi - && rs6000_spe_abi - && !TARGET_SPE_ABI) - error ("not configured for SPE ABI"); - - if (global_options_set.x_rs6000_spe - && rs6000_spe - && !TARGET_SPE) - error ("not configured for SPE instruction set"); if (main_target_opt != NULL && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi) - || (main_target_opt->x_rs6000_spe != rs6000_spe) + || (((main_target_opt->x_rs6000_isa_flags ^ rs6000_isa_flags) + & OPTION_MASK_SPE) != 0) || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs))) error ("target attribute or pragma changes SPE ABI"); @@ -2544,7 +2578,8 @@ rs6000_option_override_internal (bool gl use instructions that would be microcoded on the Cell, use the load/store multiple and string instructions. */ if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode) - target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); + rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE + | OPTION_MASK_STRING); /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu is a 750, because the hardware doesn't support the @@ -2556,15 +2591,15 @@ rs6000_option_override_internal (bool gl { if (TARGET_MULTIPLE) { - target_flags &= ~MASK_MULTIPLE; - if ((target_flags_explicit & MASK_MULTIPLE) != 0) + rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE; + if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0) warning (0, "-mmultiple is not supported on little endian systems"); } if (TARGET_STRING) { - target_flags &= ~MASK_STRING; - if ((target_flags_explicit & MASK_STRING) != 0) + rs6000_isa_flags &= ~OPTION_MASK_STRING; + if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0) warning (0, "-mstring is not supported on little endian systems"); } } @@ -2576,10 +2611,10 @@ rs6000_option_override_internal (bool gl if (!TARGET_HARD_FLOAT || !TARGET_FPRS || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx requires hardware floating point"); else - target_flags &= ~ MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; } else if (TARGET_PAIRED_FLOAT) msg = N_("-mvsx and -mpaired are incompatible"); @@ -2588,11 +2623,12 @@ rs6000_option_override_internal (bool gl systems at this point. */ else if (!BYTES_BIG_ENDIAN) msg = N_("-mvsx used with little endian code"); - else if (TARGET_AVOID_XFORM > 0) + else if (TARGET_AVOID_XFORM) msg = N_("-mvsx needs indexed addressing"); - else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC)) + else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit + & OPTION_MASK_ALTIVEC)) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx and -mno-altivec are incompatible"); else msg = N_("-mno-altivec disables vsx"); @@ -2601,27 +2637,27 @@ rs6000_option_override_internal (bool gl if (msg) { warning (0, msg); - target_flags &= ~ MASK_VSX; - target_flags_explicit |= MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; + rs6000_isa_flags_explicit |= OPTION_MASK_VSX; } } /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-<option> to disable the code. */ if (TARGET_VSX) - target_flags |= (ISA_2_6_MASKS_SERVER & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit); else if (TARGET_POPCNTD) - target_flags |= (ISA_2_6_MASKS_EMBEDDED & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit); else if (TARGET_DFP) - target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~rs6000_isa_flags_explicit); else if (TARGET_CMPB) - target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit); else if (TARGET_FPRND) - target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_4_MASKS & ~rs6000_isa_flags_explicit); else if (TARGET_POPCNTB) - target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_2_MASKS & ~rs6000_isa_flags_explicit); else if (TARGET_ALTIVEC) - target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit); + rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit); /* E500mc does "better" if we inline more aggressively. Respect the user's opinion, though. */ @@ -2700,7 +2736,8 @@ rs6000_option_override_internal (bool gl unless the altivec ABI was set. This is set by default for 64-bit, but not for 32-bit. */ if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi) - target_flags &= ~((MASK_VSX | MASK_ALTIVEC) & ~target_flags_explicit); + rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC) + & ~rs6000_isa_flags_explicit); /* Enable Altivec ABI for AIX -maltivec. */ if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX)) @@ -2727,8 +2764,8 @@ rs6000_option_override_internal (bool gl } /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */ - if (!global_options_set.x_TARGET_ALTIVEC_VRSAVE) - TARGET_ALTIVEC_VRSAVE = rs6000_altivec_abi; + if ((rs6000_misc_flags_explicit & OPTION_MASK_ALTIVEC_VRSAVE) == 0) + rs6000_misc_flags |= OPTION_MASK_ALTIVEC_VRSAVE; } /* Set the Darwin64 ABI as default for 64-bit Darwin. @@ -2782,14 +2819,14 @@ rs6000_option_override_internal (bool gl rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE; rs6000_double_float = TARGET_E500_DOUBLE; - target_flags &= ~MASK_STRING; + rs6000_isa_flags &= ~OPTION_MASK_STRING; break; default: - if (have_cpu && !(target_flags_explicit & MASK_ISEL)) - target_flags &= ~MASK_ISEL; + if (have_cpu && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL)) + rs6000_isa_flags &= ~OPTION_MASK_ISEL; break; } @@ -2807,38 +2844,14 @@ rs6000_option_override_internal (bool gl /* Detect invalid option combinations with E500. */ CHECK_E500_OPTIONS; - rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4 - && rs6000_cpu != PROCESSOR_POWER5 - && rs6000_cpu != PROCESSOR_POWER6 - && rs6000_cpu != PROCESSOR_POWER7 - && rs6000_cpu != PROCESSOR_PPCA2 - && rs6000_cpu != PROCESSOR_CELL - && rs6000_cpu != PROCESSOR_PPC476); - rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4 - || rs6000_cpu == PROCESSOR_POWER5 - || rs6000_cpu == PROCESSOR_POWER7); - rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4 - || rs6000_cpu == PROCESSOR_POWER5 - || rs6000_cpu == PROCESSOR_POWER6 - || rs6000_cpu == PROCESSOR_POWER7 - || rs6000_cpu == PROCESSOR_PPCE500MC - || rs6000_cpu == PROCESSOR_PPCE500MC64 - || rs6000_cpu == PROCESSOR_PPCE5500 - || rs6000_cpu == PROCESSOR_PPCE6500); - - /* Allow debug switches to override the above settings. These are set to -1 - in rs6000.opt to indicate the user hasn't directly set the switch. */ - if (TARGET_ALWAYS_HINT >= 0) - rs6000_always_hint = TARGET_ALWAYS_HINT; - - if (TARGET_SCHED_GROUPS >= 0) - rs6000_sched_groups = TARGET_SCHED_GROUPS; - - if (TARGET_ALIGN_BRANCH_TARGETS >= 0) - rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS; - - rs6000_sched_restricted_insns_priority - = (rs6000_sched_groups ? 1 : 0); + /* Allow the explicit debug switches to override the tuning settings. If no + explicit switch, fall back to the tuning options instead of the cpu + options. */ + rs6000_always_hint = (rs6000_operand_tuning_flag (OPTION_MASK_NO_HINT) == 0); + rs6000_sched_groups = rs6000_sched_restricted_insns_priority + = (rs6000_operand_tuning_flag (OPTION_MASK_SCHED_GROUPS) != 0); + rs6000_align_branch_targets + = (rs6000_operand_tuning_flag (OPTION_MASK_ALIGN_BRANCH_TARGETS) != 0); /* Handle -msched-costly-dep option. */ rs6000_sched_costly_dep @@ -3104,14 +3117,18 @@ rs6000_option_override_internal (bool gl rs6000_single_float = rs6000_double_float = 1; /* If not explicitly specified via option, decide whether to generate indexed - load/store instructions. */ - if (TARGET_AVOID_XFORM == -1) - /* Avoid indexed addressing when targeting Power6 in order to avoid the - DERAT mispredict penalty. However the LVE and STVE altivec instructions - need indexed accesses and the type used is the scalar type of the element - being loaded or stored. */ - TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB - && !TARGET_ALTIVEC); + load/store instructions. Avoid indexed addressing when targeting Power6 + in order to avoid the DERAT mispredict penalty. However the LVE and STVE + altivec instructions need indexed accesses and the type used is the scalar + type of the element being loaded or stored. */ + + if ((rs6000_isa_flags_explicit & OPTION_MASK_AVOID_XFORM) == 0) + { + if (TARGET_ALTIVEC) + rs6000_isa_flags &= ~OPTION_MASK_AVOID_XFORM; + else if (rs6000_cpu == PROCESSOR_POWER6) + rs6000_isa_flags |= OPTION_MASK_AVOID_XFORM; + } /* Set the -mrecip options. */ if (rs6000_recip_name) @@ -3161,16 +3178,15 @@ rs6000_option_override_internal (bool gl } /* Set the builtin mask of the various options used that could affect which - builtins were used. In the past we used target_flags, but we've run out - of bits, and some options like SPE and PAIRED are no longer in - target_flags. */ - rs6000_builtin_mask = rs6000_builtin_mask_calculate (); + builtins were used. */ + rs6000_builtin_mask = (rs6000_isa_flags & RS6000_BTM_COMMON); if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) - fprintf (stderr, "new builtin mask = 0x%x%s%s%s%s\n", rs6000_builtin_mask, - (rs6000_builtin_mask & RS6000_BTM_ALTIVEC) ? ", altivec" : "", - (rs6000_builtin_mask & RS6000_BTM_VSX) ? ", vsx" : "", - (rs6000_builtin_mask & RS6000_BTM_PAIRED) ? ", paired" : "", - (rs6000_builtin_mask & RS6000_BTM_SPE) ? ", spe" : ""); + { + fprintf (stderr, "new builtin mask = 0x%lx, ", + (long) rs6000_builtin_mask); + rs6000_print_isa_options (stderr, rs6000_builtin_mask); + putc ('\n', stderr); + } /* Initialize all of the registers. */ rs6000_init_hard_regno_mode_ok (global_init_p); @@ -10407,7 +10423,7 @@ altivec_expand_dst_builtin (tree exp, rt bool *expandedp) { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl); tree arg0, arg1, arg2; enum machine_mode mode0, mode1; rtx pat, op0, op1, op2; @@ -10809,7 +10825,7 @@ static rtx paired_expand_builtin (tree exp, rtx target, bool * expandedp) { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl); const struct builtin_description *d; size_t i; @@ -10840,28 +10856,28 @@ paired_expand_builtin (tree exp, rtx tar automagically by rs6000_expand_binop_builtin. */ static const struct builtin_description bdesc_2arg_spe[] = { - { RS6000_BTM_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } + { OPTION_MASK_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, + { OPTION_MASK_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, + { OPTION_MASK_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } }; /* Expand the builtin in EXP and store the result in TARGET. Store @@ -10874,7 +10890,7 @@ spe_expand_builtin (tree exp, rtx target { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); tree arg1, arg0; - unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl); enum insn_code icode; enum machine_mode tmode, mode0; rtx pat, op0; @@ -11239,19 +11255,23 @@ rs6000_invalid_builtin (enum rs6000_buil { size_t uns_fncode = (size_t)fncode; const char *name = rs6000_builtin_info[uns_fncode].name; - unsigned fnmask = rs6000_builtin_info[uns_fncode].mask; + HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask; gcc_assert (name != NULL); - if ((fnmask & RS6000_BTM_CELL) != 0) + if ((fnmask & OPTION_MASK_CELL_BUILTIN) != 0) error ("Builtin function %s is only valid for the cell processor", name); - else if ((fnmask & RS6000_BTM_VSX) != 0) + else if ((fnmask & OPTION_MASK_VSX) != 0) error ("Builtin function %s requires the -mvsx option", name); - else if ((fnmask & RS6000_BTM_ALTIVEC) != 0) + else if ((fnmask & OPTION_MASK_ALTIVEC) != 0) error ("Builtin function %s requires the -maltivec option", name); - else if ((fnmask & RS6000_BTM_PAIRED) != 0) + else if ((fnmask & OPTION_MASK_PAIRED_FLOAT) != 0) error ("Builtin function %s requires the -mpaired option", name); - else if ((fnmask & RS6000_BTM_SPE) != 0) + else if ((fnmask & OPTION_MASK_SPE) != 0) error ("Builtin function %s requires the -mspe option", name); + else if ((fnmask & OPTION_MASK_POPCNTB) != 0) + error ("Builtin function %s requires the -mpopcntb option", name); + else if ((fnmask & OPTION_MASK_PPC_GFXOPT) != 0) + error ("Builtin function %s requires the -mpowerpc-gfxopt option", name); else error ("Builtin function %s is not supported with the current options", name); @@ -11276,7 +11296,7 @@ rs6000_expand_builtin (tree exp, rtx tar size_t i; rtx ret; bool success; - unsigned mask = rs6000_builtin_info[uns_fcode].mask; + HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask; bool func_valid_p = ((rs6000_builtin_mask & mask) == mask); if (TARGET_DEBUG_BUILTIN) @@ -11637,7 +11657,7 @@ rs6000_init_builtins (void) static tree rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) { - unsigned fnmask; + HOST_WIDE_INT fnmask; if (code >= RS6000_BUILTIN_COUNT) return error_mark_node; @@ -12509,7 +12529,7 @@ rs6000_common_init_builtins (void) tree v2si_ftype_qi = NULL_TREE; tree v2si_ftype_v2si_qi = NULL_TREE; tree v2si_ftype_int_qi = NULL_TREE; - unsigned builtin_mask = rs6000_builtin_mask; + HOST_WIDE_INT builtin_mask = rs6000_builtin_mask; if (!TARGET_PAIRED_FLOAT) { @@ -12531,7 +12551,7 @@ rs6000_common_init_builtins (void) for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) { tree type; - unsigned mask = d->mask; + HOST_WIDE_INT mask = d->mask; if ((mask & builtin_mask) != mask) { @@ -12572,7 +12592,7 @@ rs6000_common_init_builtins (void) { enum machine_mode mode0, mode1, mode2; tree type; - unsigned mask = d->mask; + HOST_WIDE_INT mask = d->mask; if ((mask & builtin_mask) != mask) { @@ -12635,7 +12655,7 @@ rs6000_common_init_builtins (void) { enum machine_mode mode0, mode1; tree type; - unsigned mask = d->mask; + HOST_WIDE_INT mask = d->mask; if ((mask & builtin_mask) != mask) { @@ -25208,14 +25228,15 @@ rs6000_darwin_file_start (void) { const char *arg; const char *name; - int if_set; + HOST_WIDE_INT if_set; } mapping[] = { - { "ppc64", "ppc64", MASK_64BIT }, - { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, + { "ppc64", "ppc64", OPTION_MASK_64BIT }, + { "970", "ppc970", (OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF + | OPTION_MASK_POWERPC64) }, { "power4", "ppc970", 0 }, { "G5", "ppc970", 0 }, { "7450", "ppc7450", 0 }, - { "7400", "ppc7400", MASK_ALTIVEC }, + { "7400", "ppc7400", OPTION_MASK_ALTIVEC }, { "G4", "ppc7400", 0 }, { "750", "ppc750", 0 }, { "740", "ppc750", 0 }, @@ -25247,7 +25268,7 @@ rs6000_darwin_file_start (void) i = 0; while (mapping[i].arg != NULL && strcmp (mapping[i].arg, cpu_id) != 0 - && (mapping[i].if_set & target_flags) == 0) + && (mapping[i].if_set & rs6000_isa_flags) == 0) i++; fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name); @@ -27341,70 +27362,62 @@ rs6000_final_prescan_insn (rtx insn, rtx struct rs6000_opt_mask { const char *name; /* option name */ - int mask; /* mask to set */ + HOST_WIDE_INT mask; /* mask to set */ bool invert; /* invert sense of mask */ bool valid_target; /* option is a target option */ }; static struct rs6000_opt_mask const rs6000_opt_masks[] = { - { "altivec", MASK_ALTIVEC, false, true }, - { "cmpb", MASK_CMPB, false, true }, - { "dlmzb", MASK_DLMZB, false, true }, - { "fprnd", MASK_FPRND, false, true }, - { "hard-dfp", MASK_DFP, false, true }, - { "isel", MASK_ISEL, false, true }, - { "mfcrf", MASK_MFCRF, false, true }, - { "mfpgpr", MASK_MFPGPR, false, true }, - { "mulhw", MASK_MULHW, false, true }, - { "multiple", MASK_MULTIPLE, false, true }, - { "update", MASK_NO_UPDATE, true , true }, - { "popcntb", MASK_POPCNTB, false, true }, - { "popcntd", MASK_POPCNTD, false, true }, - { "powerpc-gfxopt", MASK_PPC_GFXOPT, false, true }, - { "powerpc-gpopt", MASK_PPC_GPOPT, false, true }, - { "recip-precision", MASK_RECIP_PRECISION, false, true }, - { "string", MASK_STRING, false, true }, - { "vsx", MASK_VSX, false, true }, -#ifdef MASK_64BIT + { "altivec", OPTION_MASK_ALTIVEC, false, true }, + { "avoid-indexed-addresses", OPTION_MASK_AVOID_XFORM, false, true }, + { "cmpb", OPTION_MASK_CMPB, false, true }, + { "dlmzb", OPTION_MASK_DLMZB, false, true }, + { "fprnd", OPTION_MASK_FPRND, false, true }, + { "friz", OPTION_MASK_NO_FRIZ, true, true }, + { "hard-dfp", OPTION_MASK_DFP, false, true }, + { "isel", OPTION_MASK_ISEL, false, true }, + { "mfcrf", OPTION_MASK_MFCRF, false, true }, + { "mfpgpr", OPTION_MASK_MFPGPR, false, true }, + { "mulhw", OPTION_MASK_MULHW, false, true }, + { "multiple", OPTION_MASK_MULTIPLE, false, true }, + { "update", OPTION_MASK_NO_UPDATE, true , true }, + { "popcntb", OPTION_MASK_POPCNTB, false, true }, + { "popcntd", OPTION_MASK_POPCNTD, false, true }, + { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true }, + { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true }, + { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true }, + { "string", OPTION_MASK_STRING, false, true }, + { "vsx", OPTION_MASK_VSX, false, true }, +#ifdef OPTION_MASK_64BIT #if TARGET_AIX_OS - { "aix64", MASK_64BIT, false, false }, - { "aix32", MASK_64BIT, true, false }, + { "aix64", OPTION_MASK_64BIT, false, false }, + { "aix32", OPTION_MASK_64BIT, true, false }, #else - { "64", MASK_64BIT, false, false }, - { "32", MASK_64BIT, true, false }, -#endif -#endif -#ifdef MASK_EABI - { "eabi", MASK_EABI, false, false }, + { "64", OPTION_MASK_64BIT, false, false }, + { "32", OPTION_MASK_64BIT, true, false }, #endif -#ifdef MASK_LITTLE_ENDIAN - { "little", MASK_LITTLE_ENDIAN, false, false }, - { "big", MASK_LITTLE_ENDIAN, true, false }, #endif -#ifdef MASK_RELOCATABLE - { "relocatable", MASK_RELOCATABLE, false, false }, +#ifdef OPTION_MASK_EABI + { "eabi", OPTION_MASK_EABI, false, false }, #endif -#ifdef MASK_STRICT_ALIGN - { "strict-align", MASK_STRICT_ALIGN, false, false }, -#endif - { "soft-float", MASK_SOFT_FLOAT, false, false }, - { "string", MASK_STRING, false, false }, -}; - -/* Builtin mask mapping for printing the flags. */ -static struct rs6000_opt_mask const rs6000_builtin_mask_names[] = -{ - { "altivec", RS6000_BTM_ALTIVEC, false, false }, - { "vsx", RS6000_BTM_VSX, false, false }, - { "spe", RS6000_BTM_SPE, false, false }, - { "paired", RS6000_BTM_PAIRED, false, false }, - { "fre", RS6000_BTM_FRE, false, false }, - { "fres", RS6000_BTM_FRES, false, false }, - { "frsqrte", RS6000_BTM_FRSQRTE, false, false }, - { "frsqrtes", RS6000_BTM_FRSQRTES, false, false }, - { "popcntd", RS6000_BTM_POPCNTD, false, false }, - { "cell", RS6000_BTM_CELL, false, false }, +#ifdef OPTION_MASK_LITTLE_ENDIAN + { "little", OPTION_MASK_LITTLE_ENDIAN, false, false }, + { "big", OPTION_MASK_LITTLE_ENDIAN, true, false }, +#endif +#ifdef OPTION_MASK_RELOCATABLE + { "relocatable", OPTION_MASK_RELOCATABLE, false, false }, +#endif +#ifdef OPTION_MASK_STRICT_ALIGN + { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false }, +#endif + { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false }, + { "string", OPTION_MASK_STRING, false, false }, + { "spe", OPTION_MASK_SPE, false, false }, + { "paired", OPTION_MASK_PAIRED_FLOAT, false, false }, + { "sched-groups", OPTION_MASK_SCHED_GROUPS, false, true }, + { "always-hint", OPTION_MASK_NO_HINT, true, true }, + { "align-branch", OPTION_MASK_ALIGN_BRANCH_TARGETS,false, true }, }; /* Option variables that we want to support inside attribute((target)) and @@ -27418,15 +27431,6 @@ struct rs6000_opt_var { static struct rs6000_opt_var const rs6000_opt_vars[] = { - { "friz", - offsetof (struct gcc_options, x_TARGET_FRIZ), - offsetof (struct cl_target_option, x_TARGET_FRIZ), }, - { "avoid-indexed-addresses", - offsetof (struct gcc_options, x_TARGET_AVOID_XFORM), - offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) }, - { "paired", - offsetof (struct gcc_options, x_rs6000_paired_float), - offsetof (struct cl_target_option, x_rs6000_paired_float), }, { "longcall", offsetof (struct gcc_options, x_rs6000_default_long_calls), offsetof (struct cl_target_option, x_rs6000_default_long_calls), }, @@ -27493,27 +27497,27 @@ rs6000_inner_target_options (tree args, for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++) if (strcmp (r, rs6000_opt_masks[i].name) == 0) { - int mask = rs6000_opt_masks[i].mask; + HOST_WIDE_INT mask = rs6000_opt_masks[i].mask; if (!rs6000_opt_masks[i].valid_target) not_valid_p = true; else { error_p = false; - target_flags_explicit |= mask; + rs6000_isa_flags_explicit |= mask; /* VSX needs altivec, so -mvsx automagically sets altivec. */ - if (mask == MASK_VSX && !invert) - mask |= MASK_ALTIVEC; + if (mask == OPTION_MASK_VSX && !invert) + mask |= OPTION_MASK_ALTIVEC; if (rs6000_opt_masks[i].invert) invert = !invert; if (invert) - target_flags &= ~mask; + rs6000_isa_flags &= ~mask; else - target_flags |= mask; + rs6000_isa_flags |= mask; } break; } @@ -27717,8 +27721,7 @@ rs6000_pragma_target_parse (tree args, t tree prev_tree = build_target_option_node (); tree cur_tree; struct cl_target_option *prev_opt, *cur_opt; - unsigned prev_bumask, cur_bumask, diff_bumask; - int prev_flags, cur_flags, diff_flags; + HOST_WIDE_INT prev_flags, cur_flags, diff_flags; if (TARGET_DEBUG_TARGET) { @@ -27767,27 +27770,20 @@ rs6000_pragma_target_parse (tree args, t if (rs6000_target_modify_macros_ptr) { prev_opt = TREE_TARGET_OPTION (prev_tree); - prev_bumask = prev_opt->x_rs6000_builtin_mask; - prev_flags = prev_opt->x_target_flags; + prev_flags = prev_opt->x_rs6000_isa_flags; cur_opt = TREE_TARGET_OPTION (cur_tree); - cur_flags = cur_opt->x_target_flags; - cur_bumask = cur_opt->x_rs6000_builtin_mask; + cur_flags = cur_opt->x_rs6000_isa_flags; - diff_bumask = (prev_bumask ^ cur_bumask); - diff_flags = (prev_flags ^ cur_flags); + diff_flags = (prev_flags ^ cur_flags); - if ((diff_flags != 0) || (diff_bumask != 0)) + if (diff_flags != 0) { /* Delete old macros. */ - rs6000_target_modify_macros_ptr (false, - prev_flags & diff_flags, - prev_bumask & diff_bumask); + rs6000_target_modify_macros_ptr (false, prev_flags & diff_flags); /* Define new macros. */ - rs6000_target_modify_macros_ptr (true, - cur_flags & diff_flags, - cur_bumask & diff_bumask); + rs6000_target_modify_macros_ptr (true, cur_flags & diff_flags); } } @@ -27878,7 +27874,12 @@ rs6000_set_current_function (tree fndecl static void rs6000_function_specific_save (struct cl_target_option *ptr) { - ptr->rs6000_target_flags_explicit = target_flags_explicit; + ptr->x_rs6000_isa_flags = rs6000_isa_flags; + ptr->x_rs6000_isa_flags_explicit = rs6000_isa_flags_explicit; + ptr->x_rs6000_misc_flags = rs6000_misc_flags; + ptr->x_rs6000_misc_flags_explicit = rs6000_misc_flags_explicit; + ptr->x_rs6000_debug_flags = rs6000_debug_flags; + ptr->x_rs6000_debug_flags_explicit = rs6000_debug_flags_explicit; } /* Restore the current options */ @@ -27886,47 +27887,70 @@ rs6000_function_specific_save (struct cl static void rs6000_function_specific_restore (struct cl_target_option *ptr) { - target_flags_explicit = ptr->rs6000_target_flags_explicit; + rs6000_isa_flags = ptr->x_rs6000_isa_flags; + rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit; + rs6000_misc_flags = ptr->x_rs6000_misc_flags; + rs6000_misc_flags_explicit = ptr->x_rs6000_misc_flags_explicit; + rs6000_debug_flags = ptr->x_rs6000_debug_flags; + rs6000_debug_flags_explicit = ptr->x_rs6000_debug_flags_explicit; (void) rs6000_option_override_internal (false); } -/* Print the current options */ +/* Helper function to print the current options on a line. */ static void -rs6000_function_specific_print (FILE *file, int indent, - struct cl_target_option *ptr) +rs6000_print_isa_options (FILE *file, HOST_WIDE_INT flags) { size_t i; - int flags = ptr->x_target_flags; - unsigned bu_mask = ptr->x_rs6000_builtin_mask; + const char *comma = ""; /* Print the various mask options. */ for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++) if ((flags & rs6000_opt_masks[i].mask) != 0) { flags &= ~ rs6000_opt_masks[i].mask; - fprintf (file, "%*s-m%s%s\n", indent, "", + fprintf (file, "%s%s%s", comma, rs6000_opt_masks[i].invert ? "no-" : "", rs6000_opt_masks[i].name); + comma = ", "; } + if (*comma == '\0') + fputs ("<none>", file); +} + +/* Helper function to print all of the options that are set as variables. */ + +static void +rs6000_print_isa_vars (FILE *file, struct cl_target_option *ptr) +{ + size_t i; + /* Print the various options that are variables. */ for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++) { size_t j = rs6000_opt_vars[i].target_offset; if (((signed char *) ptr)[j]) - fprintf (file, "%*s-m%s\n", indent, "", - rs6000_opt_vars[i].name); + fprintf (file, ", %s", rs6000_opt_vars[i].name); } +} - /* Print the various builtin flags. */ - fprintf (file, "%*sbuiltin mask = 0x%x\n", indent, "", bu_mask); - for (i = 0; i < ARRAY_SIZE (rs6000_builtin_mask_names); i++) - if ((bu_mask & rs6000_builtin_mask_names[i].mask) != 0) - { - fprintf (file, "%*s%s builtins supported\n", indent, "", - rs6000_builtin_mask_names[i].name); - } +/* Print the current options */ + +static void +rs6000_function_specific_print (FILE *file, int indent, + struct cl_target_option *ptr) +{ + fprintf (file, "%*sOptions (0x%lx): ", indent, "", + (long)ptr->x_rs6000_isa_flags); + rs6000_print_isa_options (file, ptr->x_rs6000_isa_flags); + rs6000_print_isa_vars (file, ptr); + fputc ('\n', file); + + fprintf (file, "%*sExplict (0x%lx): ", indent, "", + (long)ptr->x_rs6000_isa_flags_explicit); + rs6000_print_isa_options (file, ptr->x_rs6000_isa_flags_explicit); + fputc ('\n', file); } \f @@ -27956,8 +27980,8 @@ rs6000_can_inline_p (tree caller, tree c /* Callee's options should a subset of the caller's, i.e. a vsx function can inline an altivec function but a non-vsx function can't inline a vsx function. */ - if ((caller_opts->x_target_flags & callee_opts->x_target_flags) - == callee_opts->x_target_flags) + if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags) + == callee_opts->x_rs6000_isa_flags) ret = true; } Index: gcc/config/rs6000/aix52.h =================================================================== --- gcc/config/rs6000/aix52.h (revision 191198) +++ gcc/config/rs6000/aix52.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/750cl.h =================================================================== --- gcc/config/rs6000/750cl.h (revision 191198) +++ gcc/config/rs6000/750cl.h (working copy) @@ -23,7 +23,9 @@ <http://www.gnu.org/licenses/>. */ #undef TARGET_PAIRED_FLOAT -#define TARGET_PAIRED_FLOAT rs6000_paired_float +#define TARGET_PAIRED_FLOAT OPTION_PAIRED_FLOAT + +#define TARGET_USES_PAIRED_FLOAT 1 #undef ASM_CPU_SPEC #define ASM_CPU_SPEC "-m750cl" Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 191198) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -283,7 +283,7 @@ extern const char *host_detect_local_cpu #undef TARGET_TLS_MARKERS #define TARGET_TLS_MARKERS 0 #else -#define TARGET_TLS_MARKERS tls_markers +#define TARGET_TLS_MARKERS OPTION_TLS_MARKERS #endif #ifndef TARGET_SECURE_PLT @@ -325,7 +325,7 @@ extern const char *host_detect_local_cpu /* The option machinery will define this. */ #endif -#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING) +#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE | OPTION_MASK_STRING) /* FPU operations supported. Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must @@ -348,30 +348,6 @@ extern const char *host_detect_local_cpu #define PROCESSOR_DEFAULT PROCESSOR_PPC603 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A -/* Debug support */ -#define MASK_DEBUG_STACK 0x01 /* debug stack applications */ -#define MASK_DEBUG_ARG 0x02 /* debug argument handling */ -#define MASK_DEBUG_REG 0x04 /* debug register handling */ -#define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ -#define MASK_DEBUG_COST 0x10 /* debug rtx codes */ -#define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ -#define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ -#define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ - | MASK_DEBUG_ARG \ - | MASK_DEBUG_REG \ - | MASK_DEBUG_ADDR \ - | MASK_DEBUG_COST \ - | MASK_DEBUG_TARGET \ - | MASK_DEBUG_BUILTIN) - -#define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) -#define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) -#define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) -#define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) -#define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) -#define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) -#define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) - extern enum rs6000_vector rs6000_vector_unit[]; #define VECTOR_UNIT_NONE_P(MODE) \ @@ -465,21 +441,116 @@ extern int rs6000_vector_align[]; #define TARGET_FCTIDUZ TARGET_POPCNTD #define TARGET_FCTIWUZ TARGET_POPCNTD +/* Map OPTION_<xxx> back into TARGET_<xxx> options in rs6000_isa_flags. */ +#define TARGET_64BIT OPTION_64BIT +#define TARGET_ALIGN_BRANCH_TARGETS OPTION_ALIGN_BRANCH_TARGETS +#define TARGET_ALTIVEC OPTION_ALTIVEC +#define TARGET_ALWAYS_HINT OPTION_ALWAYS_HINT +#define TARGET_AVOID_XFORM OPTION_AVOID_XFORM +#define TARGET_CELL_BUILTIN OPTION_CELL_BUILTIN +#define TARGET_CMPB OPTION_CMPB +#define TARGET_DFP OPTION_DFP +#define TARGET_DLMZB OPTION_DLMZB +#define TARGET_EABI OPTION_EABI +#define TARGET_FPRND OPTION_FPRND +#define TARGET_FRIZ OPTION_FRIZ +#define TARGET_HARD_FLOAT OPTION_HARD_FLOAT +#define TARGET_ISEL OPTION_ISEL +#define TARGET_LITTLE_ENDIAN OPTION_LITTLE_ENDIAN +#define TARGET_MFCRF OPTION_MFCRF +#define TARGET_MFPGPR OPTION_MFPGPR +#define TARGET_MULHW OPTION_MULHW +#define TARGET_MULTIPLE OPTION_MULTIPLE +#define TARGET_NO_FRIZ OPTION_NO_FRIZ +#define TARGET_NO_HINT OPTION_NO_HINT +#define TARGET_NO_UPDATE OPTION_NO_UPDATE +#define TARGET_POPCNTB OPTION_POPCNTB +#define TARGET_POPCNTD OPTION_POPCNTD +#define TARGET_PPC_GFXOPT OPTION_PPC_GFXOPT +#define TARGET_PPC_GPOPT OPTION_PPC_GPOPT +#define TARGET_RECIP_PRECISION OPTION_RECIP_PRECISION +#define TARGET_SCHED_GROUPS OPTION_SCHED_GROUPS +#define TARGET_SOFT_FLOAT OPTION_SOFT_FLOAT +#define TARGET_STRICT_ALIGN OPTION_STRICT_ALIGN +#define TARGET_STRING OPTION_STRING +#define TARGET_UPDATE OPTION_UPDATE +#define TARGET_VSX OPTION_VSX + +#ifndef IN_LIBGCC2 +#define TARGET_POWERPC64 OPTION_POWERPC64 +#endif + +#ifdef OPTION_RELOCATABLE +#define TARGET_RELOCATABLE OPTION_RELOCATABLE +#endif + +#ifdef OPTION_MINIMAL_TOC +#define TARGET_MINIMAL_TOC OPTION_MINIMAL_TOC +#endif + +/* Map OPTION_<xxx> back into TARGET_<xxx> options in rs6000_misc_flags. */ +#define TARGET_ALLOW_MOVMISALIGN OPTION_ALLOW_MOVMISALIGN +#define TARGET_ALTIVEC_VRSAVE OPTION_ALTIVEC_VRSAVE +#define TARGET_NO_BITFIELD_TYPE OPTION_NO_BITFIELD_TYPE +#define TARGET_NO_BITFIELD_WORD OPTION_NO_BITFIELD_WORD +#define TARGET_POINTERS_TO_NESTED_FUNCTIONS OPTION_POINTERS_TO_NESTED_FUNCTIONS +#define TARGET_SAVE_TOC_INDIRECT OPTION_SAVE_TOC_INDIRECT +#define TARGET_SINGLE_PIC_BASE OPTION_SINGLE_PIC_BASE +#define TARGET_SCHED_PROLOG OPTION_SCHED_PROLOG +#define TARGET_VECTORIZE_BUILTINS OPTION_VECTORIZE_BUILTINS +#define TARGET_VSX_ALIGN_128 OPTION_VSX_ALIGN_128 +#define TARGET_VSX_SCALAR_DOUBLE OPTION_VSX_SCALAR_DOUBLE +#define TARGET_VSX_SCALAR_MEMORY OPTION_VSX_SCALAR_MEMORY +#define TARGET_XL_COMPAT OPTION_XL_COMPAT + +/* Map OPTION_<xxx> back into TARGET_<xxx> options in rs6000_debug_flags. */ +#define TARGET_DEBUG_ALL OPTION_DEBUG_ALL +#define TARGET_DEBUG_ARG OPTION_DEBUG_ARG +#define TARGET_DEBUG_STACK OPTION_DEBUG_STACK +#define TARGET_DEBUG_ADDR OPTION_DEBUG_ADDR +#define TARGET_DEBUG_BUILTIN OPTION_DEBUG_BUILTIN +#define TARGET_DEBUG_COST OPTION_DEBUG_COST +#define TARGET_DEBUG_REG OPTION_DEBUG_REG +#define TARGET_DEBUG_TARGET OPTION_DEBUG_TARGET + +/* Debug masks. */ +#define ALL_DEBUG_MASKS (OPTION_MASK_DEBUG_ADDR \ + | OPTION_MASK_DEBUG_ARG \ + | OPTION_MASK_DEBUG_BUILTIN \ + | OPTION_MASK_DEBUG_COST \ + | OPTION_MASK_DEBUG_REG \ + | OPTION_MASK_DEBUG_STACK \ + | OPTION_MASK_DEBUG_TARGET) + +/* Explicit ISA options that were set. */ +#define rs6000_isa_flags_explicit global_options_set.x_rs6000_isa_flags +#define rs6000_misc_flags_explicit global_options_set.x_rs6000_misc_flags +#define rs6000_debug_flags_explicit global_options_set.x_rs6000_debug_flags + +/* Miscellaneous/debug flag bits to set. */ +#define TARGET_MISC_DEFAULT (OPTION_MASK_VECTORIZE_BUILTINS \ + | OPTION_MASK_VSX_SCALAR_DOUBLE \ + | OPTION_MASK_ALLOW_MOVMISALIGN \ + | OPTION_MASK_SCHED_PROLOG \ + | OPTION_MASK_TLS_MARKERS \ + | OPTION_MASK_POINTERS_TO_NESTED_FUNCTIONS) + +#define TARGET_DEBUG_DEFAULT 0 + /* For power systems, we want to enable Altivec and VSX builtins even if the user did not use -maltivec or -mvsx to allow the builtins to be used inside of #pragma GCC target or the target attribute to change the code level for a - given system. The SPE and Paired builtins are only enabled if you configure - the compiler for those builtins, and those machines don't support altivec or - VSX. */ - -#define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \ - && ((TARGET_POWERPC64 \ - || TARGET_PPC_GPOPT /* 970/power4 */ \ - || TARGET_POPCNTB /* ISA 2.02 */ \ - || TARGET_CMPB /* ISA 2.05 */ \ - || TARGET_POPCNTD /* ISA 2.06 */ \ - || TARGET_ALTIVEC \ - || TARGET_VSX))) + given system. */ + +#define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \ + || TARGET_PPC_GPOPT /* 970/power4 */ \ + || TARGET_ALTIVEC /* G5/ISA 2.05 */ \ + || TARGET_POPCNTB /* ISA 2.02 */ \ + || TARGET_CMPB /* ISA 2.05 */ \ + || TARGET_POPCNTD /* ISA 2.06 */ \ + || TARGET_VSX /* ISA 2.06 */ \ + || TARGET_PAIRED_FLOAT /* 750CL */ \ + || TARGET_SPE) /* E500 */ /* E500 cores only support plain "sync", not lwsync. */ #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ @@ -654,7 +725,7 @@ extern unsigned char rs6000_recip_bits[] #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size /* Define this to set long double type size to use in libgcc2.c, which can - not depend on target_flags. */ + not depend on rs6000_isa_flags. */ #ifdef __LONG_DOUBLE_128__ #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 #else @@ -2273,29 +2344,15 @@ extern int frame_pointer_needed; #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ -/* Builtin targets. For now, we reuse the masks for those options that are in - target flags, and pick two random bits for SPE and paired which aren't in - target_flags. */ -#define RS6000_BTM_ALWAYS 0 /* Always enabled. */ -#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ -#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ -#define RS6000_BTM_SPE MASK_STRING /* E500 */ -#define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ -#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ -#define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ -#define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ -#define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ -#define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ -#define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ - -#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ - | RS6000_BTM_VSX \ - | RS6000_BTM_FRE \ - | RS6000_BTM_FRES \ - | RS6000_BTM_FRSQRTE \ - | RS6000_BTM_FRSQRTES \ - | RS6000_BTM_POPCNTD \ - | RS6000_BTM_CELL) +/* Options that control builtin targets. */ +#define RS6000_BTM_COMMON (OPTION_MASK_ALTIVEC \ + | OPTION_MASK_VSX \ + | OPTION_MASK_SPE \ + | OPTION_MASK_PAIRED_FLOAT \ + | OPTION_MASK_POPCNTB \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_CELL_BUILTIN) /* Define builtin enum index. */ Index: gcc/config/rs6000/aix64.opt =================================================================== --- gcc/config/rs6000/aix64.opt (revision 191198) +++ gcc/config/rs6000/aix64.opt (working copy) @@ -20,11 +20,11 @@ ; <http://www.gnu.org/licenses/>. maix64 -Target Report RejectNegative Negative(maix32) Mask(64BIT) +Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags) Compile for 64-bit pointers maix32 -Target Report RejectNegative Negative(maix64) InverseMask(64BIT) +Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags) Compile for 32-bit pointers mpe Index: gcc/config/rs6000/sysv4le.h =================================================================== --- gcc/config/rs6000/sysv4le.h (revision 191198) +++ gcc/config/rs6000/sysv4le.h (working copy) @@ -20,7 +20,7 @@ <http://www.gnu.org/licenses/>. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_LITTLE_ENDIAN +#define TARGET_DEFAULT OPTION_MASK_LITTLE_ENDIAN #undef CC1_ENDIAN_DEFAULT_SPEC #define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)" Index: gcc/config/rs6000/xfpu.h =================================================================== --- gcc/config/rs6000/xfpu.h (revision 191198) +++ gcc/config/rs6000/xfpu.h (working copy) @@ -23,4 +23,7 @@ /* Undefine definitions from rs6000.h. */ #undef TARGET_XILINX_FPU -#define TARGET_XILINX_FPU (rs6000_xilinx_fpu) +#define TARGET_XILINX_FPU OPTION_XILINX_FPU + +#define TARGET_USES_XILINX_FPU 1 + Index: gcc/config/rs6000/freebsd64.h =================================================================== --- gcc/config/rs6000/freebsd64.h (revision 191198) +++ gcc/config/rs6000/freebsd64.h (working copy) @@ -57,7 +57,7 @@ extern int dot_symbols; -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "freebsd" @@ -79,14 +79,14 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ - if (target_flags & MASK_RELOCATABLE) \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error (INVALID_64BIT, "relocatable"); \ } \ - if (target_flags & MASK_EABI) \ + if (rs6000_isa_flags & OPTION_MASK_EABI) \ { \ - target_flags &= ~MASK_EABI; \ + rs6000_isa_flags &= ~OPTION_MASK_EABI; \ error (INVALID_64BIT, "eabi"); \ } \ if (TARGET_PROTOTYPE) \ @@ -94,12 +94,13 @@ extern int dot_symbols; target_prototype = 0; \ error (INVALID_64BIT, "prototype"); \ } \ - if ((target_flags & MASK_POWERPC64) == 0) \ + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ error ("-m64 requires a PowerPC64 cpu"); \ } \ - if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ + if ((rs6000_isa_flags_explicit \ + & OPTION_MASK_MINIMAL_TOC) != 0) \ { \ if (global_options_set.x_rs6000_current_cmodel \ && rs6000_current_cmodel != CMODEL_SMALL) \ Index: gcc/config/rs6000/aix61.h =================================================================== --- gcc/config/rs6000/aix61.h (revision 191198) +++ gcc/config/rs6000/aix61.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/sysv4.opt =================================================================== --- gcc/config/rs6000/sysv4.opt (revision 191198) +++ gcc/config/rs6000/sysv4.opt (working copy) @@ -45,16 +45,16 @@ EnumValue Enum(rs6000_tls_size) String(64) Value(64) mbit-align -Target Report Var(TARGET_NO_BITFIELD_TYPE) Save +Target Report Mask(NO_BITFIELD_TYPE) Var(rs6000_misc_flags) Align to the base type of the bit-field mstrict-align -Target Report Mask(STRICT_ALIGN) +Target Report Mask(STRICT_ALIGN) Var(rs6000_isa_flags) Align to the base type of the bit-field Don't assume that unaligned accesses are handled by the system mrelocatable -Target Report Mask(RELOCATABLE) +Target Report Mask(RELOCATABLE) Var(rs6000_isa_flags) Produce code relocatable at runtime mrelocatable-lib @@ -62,19 +62,19 @@ Target Produce code relocatable at runtime mlittle-endian -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code mlittle -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code mbig-endian -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code mbig -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code ;; FIXME: This does nothing. What should be done? @@ -96,11 +96,11 @@ Target RejectNegative no description yet meabi -Target Report Mask(EABI) +Target Report Mask(EABI) Var(rs6000_isa_flags) Use EABI mbit-word -Target Report Var(TARGET_NO_BITFIELD_WORD) Save +Target Report Mask(NO_BITFIELD_WORD) Var(rs6000_misc_flags) Allow bit-fields to cross word boundaries mregnames @@ -138,11 +138,11 @@ Target RejectNegative no description yet m64 -Target Report RejectNegative Negative(m32) Mask(64BIT) +Target Report RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target Report RejectNegative Negative(m64) InverseMask(64BIT) +Target Report RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code mnewlib Index: gcc/config/rs6000/eabispe.h =================================================================== --- gcc/config/rs6000/eabispe.h (revision 191198) +++ gcc/config/rs6000/eabispe.h (working copy) @@ -20,7 +20,7 @@ <http://www.gnu.org/licenses/>. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_STRICT_ALIGN | MASK_EABI) +#define TARGET_DEFAULT (OPTION_MASK_STRICT_ALIGN | OPTION_MASK_EABI) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc -mspe -me500" Index: gcc/config/rs6000/rs6000-cpus.def =================================================================== --- gcc/config/rs6000/rs6000-cpus.def (revision 191198) +++ gcc/config/rs6000/rs6000-cpus.def (working copy) @@ -32,6 +32,128 @@ where the arguments are the fields of struct rs6000_ptt. */ + +/* ISA masks. */ +#ifndef ISA_2_1_MASKS +#define ISA_2_1_MASKS OPTION_MASK_MFCRF +#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB) +#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND) + + /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add + ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, + fre, fsqrt, etc. were no longer documented as optional. Group masks by + server and embedded. */ +#define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT) + +#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP) + + /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but + altivec is a win so enable it. */ +#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD) +#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_ALTIVEC \ + | OPTION_MASK_VSX) + +/* Masks for various processors. */ +#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) + +#define POWER_BASE_MASK (OPTION_MASK_POWERPC64 \ + | OPTION_MASK_PPC_GPOPT \ + | OPTION_MASK_PPC_GFXOPT) \ + +#define POWER4_ISA_MASK (POWER_BASE_MASK | ISA_2_1_MASKS) +#define POWER4_TUNE_MASK (OPTION_MASK_SCHED_GROUPS \ + | OPTION_MASK_NO_HINT \ + | OPTION_MASK_ALIGN_BRANCH_TARGETS) + +#define POWER5_ISA_MASK (POWER_BASE_MASK | ISA_2_2_MASKS) +#define POWER5P_ISA_MASK (POWER_BASE_MASK | ISA_2_4_MASKS) +#define POWER5_TUNE_MASK POWER4_TUNE_MASK + +/* Don't include Altivec on power6 because it is generally not a win. */ +#define POWER6_ISA_MASK (POWER_BASE_MASK | ISA_2_5_MASKS_SERVER) +#define POWER6X_ISA_MASK (POWER6_ISA_MASK | OPTION_MASK_MFPGPR) +#define POWER6_TUNE_MASK (OPTION_MASK_NO_HINT \ + | OPTION_MASK_ALIGN_BRANCH_TARGETS \ + | OPTION_MASK_AVOID_XFORM) + +/* Don't add ISEL by default to power7, since it is generally not a win. */ +#define POWER7_ISA_MASK (POWER_BASE_MASK | ISA_2_6_MASKS_SERVER) +#define POWER7_TUNE_MASK POWER4_TUNE_MASK + +/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ +#define POWERPC_MASKS (OPTION_MASK_ALIGN_BRANCH_TARGETS \ + | OPTION_MASK_ALTIVEC \ + | OPTION_MASK_AVOID_XFORM \ + | OPTION_MASK_CELL_BUILTIN \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_DFP \ + | OPTION_MASK_DLMZB \ + | OPTION_MASK_FPRND \ + | OPTION_MASK_ISEL \ + | OPTION_MASK_MFCRF \ + | OPTION_MASK_MFPGPR \ + | OPTION_MASK_MULHW \ + | OPTION_MASK_NO_FRIZ \ + | OPTION_MASK_NO_HINT \ + | OPTION_MASK_NO_UPDATE \ + | OPTION_MASK_PAIRED_FLOAT \ + | OPTION_MASK_POPCNTB \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_POWERPC64 \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_SCHED_GROUPS \ + | OPTION_MASK_SOFT_FLOAT \ + | OPTION_MASK_SPE \ + | OPTION_MASK_STRICT_ALIGN \ + | OPTION_MASK_VSX \ + | OPTION_MASK_XILINX_FPU) + + +/* Temporarily map OPTION_MASK_<xxx> to MASK_<xxx> in rs6000_isa_flags. */ +#define MASK_64BIT OPTION_MASK_64BIT +#define MASK_ALIGN_BRANCH_TARGETS OPTION_MASK_ALIGN_BRANCH_TARGETS +#define MASK_ALTIVEC OPTION_MASK_ALTIVEC +#define MASK_AVOID_XFORM OPTION_MASK_AVOID_XFORM +#define MASK_CELL_BUILTIN OPTION_MASK_CELL_BUILTIN +#define MASK_CMPB OPTION_MASK_CMPB +#define MASK_DFP OPTION_MASK_DFP +#define MASK_DLMZB OPTION_MASK_DLMZB +#define MASK_EABI OPTION_MASK_EABI +#define MASK_FPRND OPTION_MASK_FPRND +#define MASK_FRIZ OPTION_MASK_FRIZ +#define MASK_ISEL OPTION_MASK_ISEL +#define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN +#define MASK_MFCRF OPTION_MASK_MFCRF +#define MASK_MFPGPR OPTION_MASK_MFPGPR +#define MASK_MULHW OPTION_MASK_MULHW +#define MASK_MULTIPLE OPTION_MASK_MULTIPLE +#define MASK_NO_FRIZ OPTION_MASK_NO_FRIZ +#define MASK_NO_HINT OPTION_MASK_NO_HINT +#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE +#define MASK_PAIRED_FLOAT OPTION_MASK_PAIRED_FLOAT +#define MASK_POPCNTB OPTION_MASK_POPCNTB +#define MASK_POPCNTD OPTION_MASK_POPCNTD +#define MASK_POWERPC64 OPTION_MASK_POWERPC64 +#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT +#define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT +#define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION +#define MASK_SCHED_GROUPS OPTION_MASK_SCHED_GROUPS +#define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT +#define MASK_SPE OPTION_MASK_SPE +#define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN +#define MASK_STRING OPTION_MASK_STRING +#define MASK_VSX OPTION_MASK_VSX +#define MASK_XILINX_FPU OPTION_MASK_XILINX_FPU +#endif + RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT) RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN) RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) @@ -42,10 +164,10 @@ RS6000_CPU ("464", PROCESSOR_PPC440, MAS RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) RS6000_CPU ("476", PROCESSOR_PPC476, MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB - | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB) + | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB | MASK_NO_HINT) RS6000_CPU ("476fp", PROCESSOR_PPC476, MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_MULHW | MASK_DLMZB) + | MASK_CMPB | MASK_MULHW | MASK_DLMZB | MASK_NO_HINT) RS6000_CPU ("505", PROCESSOR_MPCCORE, 0) RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE | MASK_STRING) RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT) @@ -62,48 +184,44 @@ RS6000_CPU ("750", PROCESSOR_PPC750, MAS RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL) -RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL) +RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL | MASK_SPE) +RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL | MASK_SPE) RS6000_CPU ("a2", PROCESSOR_PPCA2, MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB - | MASK_NO_UPDATE) + | MASK_NO_UPDATE | MASK_NO_HINT) RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT) RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0) -RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL) +RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL + | MASK_ALIGN_BRANCH_TARGETS) RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64, - MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) + MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL + | MASK_ALIGN_BRANCH_TARGETS) RS6000_CPU ("e5500", PROCESSOR_PPCE5500, - MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) + MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL + | MASK_ALIGN_BRANCH_TARGETS) RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64 - | MASK_MFCRF | MASK_ISEL) + | MASK_MFCRF | MASK_ISEL | MASK_ALIGN_BRANCH_TARGETS) RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) RS6000_CPU ("970", PROCESSOR_POWER4, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) + POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 + | MASK_SCHED_GROUPS | MASK_NO_HINT | MASK_ALIGN_BRANCH_TARGETS) RS6000_CPU ("cell", PROCESSOR_CELL, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) + POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 + | MASK_CELL_BUILTIN | MASK_NO_HINT) RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT) RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT) RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK) RS6000_CPU ("G5", PROCESSOR_POWER4, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) + POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 + | MASK_SCHED_GROUPS | MASK_NO_HINT | MASK_ALIGN_BRANCH_TARGETS) RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB) RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF) -RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB) -RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND) -RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) -RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION) -RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */ - POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF - | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD - | MASK_VSX | MASK_RECIP_PRECISION) +RS6000_CPU ("power4", PROCESSOR_POWER4, POWER4_ISA_MASK | POWER4_TUNE_MASK) +RS6000_CPU ("power5", PROCESSOR_POWER5, POWER5_ISA_MASK | POWER5_TUNE_MASK) +RS6000_CPU ("power5+", PROCESSOR_POWER5, POWER5P_ISA_MASK | POWER5_TUNE_MASK) +RS6000_CPU ("power6", PROCESSOR_POWER6, POWER6_ISA_MASK | POWER6_TUNE_MASK) +RS6000_CPU ("power6x", PROCESSOR_POWER6, POWER6X_ISA_MASK | POWER6_TUNE_MASK) +RS6000_CPU ("power7", PROCESSOR_POWER7, POWER7_ISA_MASK | POWER7_TUNE_MASK) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) Index: gcc/config/rs6000/e500.h =================================================================== --- gcc/config/rs6000/e500.h (revision 191198) +++ gcc/config/rs6000/e500.h (working copy) @@ -24,8 +24,10 @@ #undef TARGET_E500_DOUBLE #undef CHECK_E500_OPTIONS +#define TARGET_USES_SPE 1 + #define TARGET_SPE_ABI rs6000_spe_abi -#define TARGET_SPE rs6000_spe +#define TARGET_SPE OPTION_SPE #define TARGET_FPRS (rs6000_float_gprs == 0) #define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1) #define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2) Index: gcc/config/rs6000/freebsd.h =================================================================== --- gcc/config/rs6000/freebsd.h (revision 191198) +++ gcc/config/rs6000/freebsd.h (working copy) @@ -72,7 +72,7 @@ -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) Index: gcc/config/rs6000/option-defaults.h =================================================================== --- gcc/config/rs6000/option-defaults.h (revision 191198) +++ gcc/config/rs6000/option-defaults.h (working copy) @@ -35,11 +35,11 @@ #define OPT_32 "m32" #endif -#ifndef MASK_64BIT -#define MASK_64BIT 0 +#ifndef OPTION_MASK_64BIT +#define OPTION_MASK_64BIT 0 #endif -#if TARGET_DEFAULT & MASK_64BIT +#if TARGET_DEFAULT & OPTION_MASK_64BIT #define OPT_ARCH64 "!"OPT_32 #define OPT_ARCH32 OPT_32 #else Index: gcc/config/rs6000/rs6000-protos.h =================================================================== --- gcc/config/rs6000/rs6000-protos.h (revision 191198) +++ gcc/config/rs6000/rs6000-protos.h (working copy) @@ -176,7 +176,6 @@ extern void rs6000_call_indirect_aix (rt extern void rs6000_aix_asm_output_dwarf_table_ref (char *); extern void get_ppc476_thunk_name (char name[32]); extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins); -extern unsigned rs6000_builtin_mask_calculate (void); /* Declare functions in rs6000-c.c */ @@ -185,8 +184,8 @@ extern void rs6000_cpu_cpp_builtins (str #ifdef TREE_CODE extern bool rs6000_pragma_target_parse (tree, tree); #endif -extern void rs6000_target_modify_macros (bool, int, unsigned); -extern void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned); +extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT); +extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT); #if TARGET_MACHO char *output_call (rtx, rtx *, int, int); Index: gcc/config/rs6000/vxworks.h =================================================================== --- gcc/config/rs6000/vxworks.h (revision 191198) +++ gcc/config/rs6000/vxworks.h (working copy) @@ -98,7 +98,7 @@ VXWORKS_ADDITIONAL_CPP_SPEC #undef MULTILIB_DEFAULTS #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_EABI | MASK_STRICT_ALIGN) +#define TARGET_DEFAULT (OPTION_MASK_EABI | OPTION_MASK_STRICT_ALIGN) #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_PPC604 Index: gcc/config/rs6000/aix51.h =================================================================== --- gcc/config/rs6000/aix51.h (revision 191198) +++ gcc/config/rs6000/aix51.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_POWERPC64 && ! TARGET_64BIT) \ Index: gcc/config/rs6000/sysv4.h =================================================================== --- gcc/config/rs6000/sysv4.h (revision 191198) +++ gcc/config/rs6000/sysv4.h (working copy) @@ -40,9 +40,10 @@ #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc" -#define TARGET_TOC ((target_flags & MASK_64BIT) \ - || ((target_flags & (MASK_RELOCATABLE \ - | MASK_MINIMAL_TOC)) \ +#define TARGET_TOC ((rs6000_isa_flags & OPTION_MASK_64BIT) \ + || ((rs6000_isa_flags \ + & (OPTION_MASK_RELOCATABLE \ + | OPTION_MASK_MINIMAL_TOC)) \ && flag_pic > 1) \ || DEFAULT_ABI == ABI_AIX) @@ -77,13 +78,13 @@ do { \ else if (!strcmp (rs6000_abi_name, "sysv-noeabi")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags &= ~ MASK_EABI; \ + rs6000_isa_flags &= ~ OPTION_MASK_EABI; \ } \ else if (!strcmp (rs6000_abi_name, "sysv-eabi") \ || !strcmp (rs6000_abi_name, "eabi")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags |= MASK_EABI; \ + rs6000_isa_flags |= OPTION_MASK_EABI; \ } \ else if (!strcmp (rs6000_abi_name, "aixdesc")) \ rs6000_current_abi = ABI_AIX; \ @@ -102,9 +103,9 @@ do { \ else if (!strcmp (rs6000_abi_name, "i960-old")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags |= (MASK_LITTLE_ENDIAN | MASK_EABI); \ - target_flags &= ~MASK_STRICT_ALIGN; \ - TARGET_NO_BITFIELD_WORD = 1; \ + rs6000_isa_flags |= (OPTION_MASK_LITTLE_ENDIAN | OPTION_MASK_EABI); \ + rs6000_isa_flags &= ~OPTION_MASK_STRICT_ALIGN; \ + rs6000_misc_flags |= OPTION_MASK_NO_BITFIELD_WORD; \ } \ else \ { \ @@ -168,13 +169,13 @@ do { \ \ if (TARGET_RELOCATABLE && !TARGET_MINIMAL_TOC) \ { \ - target_flags |= MASK_MINIMAL_TOC; \ + rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; \ error ("-mrelocatable and -mno-minimal-toc are incompatible"); \ } \ \ if (TARGET_RELOCATABLE && rs6000_current_abi == ABI_AIX) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error ("-mrelocatable and -mcall-%s are incompatible", \ rs6000_abi_name); \ } \ @@ -188,7 +189,7 @@ do { \ \ if (rs6000_current_abi == ABI_AIX && TARGET_LITTLE_ENDIAN) \ { \ - target_flags &= ~MASK_LITTLE_ENDIAN; \ + rs6000_isa_flags &= ~OPTION_MASK_LITTLE_ENDIAN; \ error ("-mcall-aixdesc must be big endian"); \ } \ \ @@ -200,7 +201,7 @@ do { \ /* Treat -fPIC the same as -mrelocatable. */ \ if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX) \ { \ - target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; \ + rs6000_isa_flags |= OPTION_MASK_RELOCATABLE | OPTION_MASK_MINIMAL_TOC; \ TARGET_NO_FP_IN_TOC = 1; \ } \ \ @@ -212,9 +213,9 @@ do { \ #ifndef RS6000_BI_ARCH # define SUBSUBTARGET_OVERRIDE_OPTIONS \ do { \ - if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) \ + if ((TARGET_DEFAULT ^ rs6000_isa_flags) & OPTION_MASK_64BIT) \ error ("-m%s not supported in this configuration", \ - (target_flags & MASK_64BIT) ? "64" : "32"); \ + (rs6000_isa_flags & OPTION_MASK_64BIT) ? "64" : "32"); \ } while (0) #endif @@ -500,8 +501,8 @@ extern int fixuplabelno; #define TARGET_OS_SYSV_CPP_BUILTINS() \ do \ { \ - if (target_flags_explicit \ - & MASK_RELOCATABLE) \ + if (rs6000_isa_flags_explicit \ + & OPTION_MASK_RELOCATABLE) \ builtin_define ("_RELOCATABLE"); \ } \ while (0) ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch 2012-09-12 22:44 [PATCH] Rs6000 infrastructure cleanup (switches) Michael Meissner @ 2012-09-17 19:52 ` Michael Meissner 2012-09-19 0:04 ` David Edelsohn 0 siblings, 1 reply; 13+ messages in thread From: Michael Meissner @ 2012-09-17 19:52 UTC (permalink / raw) To: Michael Meissner, gcc-patches, dje.gcc, bergner, segher, iain, andreast-list [-- Attachment #1: Type: text/plain, Size: 7414 bytes --] This patch has support for all of the additonal cleanups I mentioned in the first patch that I hadn't gotten to. At this point, I am not planning any more enhancements to the patch, and I would like to check it in. On my 64-bit powerpc system, there are 36 options in the main ISA flags fields, 23 options in the miscellaneous flags fields, and 8 options in the debug flag fields. I believe it answers the problems Ian had. I changed all of the debugging fprintf's to use HOST_WIDE_INT_PRINT_HEX to print the numeric value of the flags fields, and I changed the #ifdef TARGET_<xxx> to #ifdef OPTION_<xxx>. It builds and bootstraps fine on my powerpc64 linux system and there were no regressions. It is ok to install? 2012-09-14 Michael Meissner <meissner@linux.vnet.ibm.com> * common/config/rs6000/rs6000-common.c (rs6000_handle_option): Move all switches that set target_flags to set rs6000_isa_flags, and make it HOST_WIDE_INT. Make SPE/paired floating point ISA bits once again. Move other switches that were previously separate variables back as option bits, and add rs6000_misc_flags and rs6000_debug_flags. Save/restore new option words. Change MASK_<xxx> to OPTION_MASK_<xxx>. Add TARGET_<xxx> maps for OPTION_<xxx>. Move -mdebug=xxx handling to rs6000.opt file. Add rs6000-cpus.def as rs6000.o dependency. Use rs6000_isa_options for all builtins. Print more debug output for -mdebug=reg. Move masks for different cpu levels to rs6000-cpus.def. Move branch hint, align branch targets, schedule groups to tune flags in rs6000-cpus.def. Turn off VSX if the assembler doesn't support Altivec. * config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/linux.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * config/rs6000/t-rs6000 (rs6000.o): Likewise. * config/rs6000/eabi.h (TARGET_DEFAULT): Likewise. * config/rs6000/eabispe.h (TARGET_DEFAULT): Likewise. * config/rs6000/eabialtivec.h (TARGET_DEFAULT): Likewise. * config/rs6000/darwin64.h (TARGET_DEFAULT): Likewise. * config/rs6000/default64.h (TARGET_DEFAULT): Likewise. * config/rs6000/linuxaltivec.h (TARGET_DEFAULT): Likewise. * config/rs6000/darwin.h (TARGET_DEFAULT): Likewise. * config/rs6000/sysv4le.h (TARGET_DEFAULT): Likewis.e * config/rs6000/xfpu.h (TARGET_DEFAULT): Likewise. * config/rs6000/eabispe.h (TARGET_DEFAULT): Likewise. * config/rs6000/vxworks.h (TARGET_DEFAULT): Likewise. * config/rs6000/rs6000.opt (most options): Likewise. * config/rs6000/sysv4.opt (most options): Likewise. * config/rs6000/darwin64.opt (most options): Likewise. * config/rs6000/aix64.opt (most options): Likewise. * config/rs6000/linux64.opt (-mprofile-kernel): Likewise. * config/rs6000/476.opt (-mpreserve-link-stack): Likewise. * config/rs6000/476.h (TARGET_LINK_STACK): Likewise. * config/rs6000/secureplt.h (OPTION_MASK_DEFAULT_SECURE_PLT): Likewise. (SET_TARGET_LINK_STACK): Likewise. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. (rs6000_cpu_cpp_builtins): Likewise. * config/rs6000/rs6000-builtin.def (all BU_* macros): Likewise. * config/rs6000/linux64.h (DEFAULT_ARCH64_P): Likewise. (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/freebsd64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. * config/rs6000/rs6000.c (struct builtin_description): Likewise. (rs6000_target_modify_macros_ptr): Likewise. (struct processor_costs): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (ISA_2_6_MASKS_EMBEDDED): Likewise. (ISA_2_6_MASKS_SERVER): Likewise. (struct rs6000_ptt): Likewise. (DEBUG_FMT_LX): Likewise. (DEBUG_FMT_LX2): Likewise. (rs6000_debug_reg_global): Likewise. (darwin_rs6000_override_options): Likewise. (rs6000_builtin_mask_calculate): Likewise. (rs6000_operand_tuning_flag): Likewise. (rs6000_option_override_internal): Likewise. (altivec_expand_dst_builtin): Likewise. (paired_expand_builtin): Likewise. (bdesc_2arg_spe): Likewise. (spe_expand_builtin): Likewise. (rs6000_invalid_builtin): Likewise. (rs6000_expand_builtin): Likewise. (rs6000_init_builtins): Likewise. (rs6000_builtin_decl): Likewise. (rs0600_common_init_builtins): Likewise. (rs6000_handle_altivec_attribute): Likewise. (rs6000_darwin_file_start): Likewise. (rs6000_final_prescan_insn): Likewise. (rs6000_opt_masks): Likewise. (rs6000_opt_vars): Likewise. (rs6000_misc_masks): Likewise. (rs6000_inner_target_options): Likewise. (rs6000_pragma_target_parse): Likewise. (rs6000_function_specific_save): Likewise. (rs6000_function_specific_resotre): Likewise. (rs6000_function_specific_print): Likewise. (rs6000_print_isa_options): Likewise. (rs6000_print_isa_vars): Likewise. (rs6000_can_inline_p): Likewise. * config/rs6000/750cl.h (TARGET_PAIRED_FLOAT): Likewise. (TARGET_USES_PAIRED_FLOAT): Likewise. * config/rs6000/rs6000.h (TARGET_*): Likewise. (MASK_DEBUG_*): Likewise. (ALL_DEBUG_MASKS): Likewise. (RS6000_BTM_*): Likewise. * config/rs6000/aix64.opt (-maix64): Likewise. (-maix32): Likewise. * config/rs6000/rs6000-cpus.def (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (ISA_2_6_MASKS_EMBEDDED): Likewise. (ISA_2_6_MASKS_SERVER): Likewise. (POWER_BASE_MASK): Likewise. (POWER4_ISA_MASK): Likewise. (POWER4_TUNE_MASK): Likewsie. (POWER5_ISA_MASK): Likewise. (POWER5P_ISA_MASK): Likewise. (POWER5_TUNE_MASK): Likewsie. (POWER6_ISA_MASK): Likewise. (POWER6X_ISA_MASK): Likewise. (POWER6_TUNE_MASK): Likewsie. (POWER7_ISA_MASK): Likewise. (POWER7_TUNE_MASK): Likewsie. (MASK_*): Likewise. (476 cpu): Likewise. (476fp cpu): Likewise. (8540 cpu): Likewise. (8548 cpu): Likewise. (a2 cpu): Likewise. (e500mc cpu): Likewise. (e500mc64 cpu): Likewise. (e5500 cpu): Likewise. (e6500 cpu): Likewise. (970 cpu): Likewise. (cell cpu): Likewise. (G5 cpu): Likewise. (power4 cpu): Likewise. (power5 cpu): Likewise. (power5+ cpu): Likewise. (power6 cpu): Likewise. (power6x cpu): Likewise. (power7 cpu): Likewise. * config/rs6000/e500.h (TARGET_USES_SPE): Likewise. (TARGET_SPE): Likewise. * config/rs6000/option-defaults.h (OPTION_MASK_64BIT): Likewise. * config/rs6000/rs6000-protos.h (rs6000_builtin_mask_calculate): Likewise. (rs6000_target_modify_macros): Likewise. (rs6000_target_modify_macros_ptr): Likewise. * config/rs6000/sysv4.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (TARGET_OS_SYSV_CPP_BUILTINS): Likewise. * config/rs6000/predicates.md (cc_reg_not_micro_cr0_operand): Likewise. * config/rs6000/rs6000.md (cell microcode insns): Likewise. -- Michael Meissner, IBM 5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA meissner@linux.vnet.ibm.com fax +1 (978) 399-6899 [-- Attachment #2: gcc-power7.patch351b --] [-- Type: text/plain, Size: 160827 bytes --] Index: gcc/common/config/rs6000/rs6000-common.c =================================================================== --- gcc/common/config/rs6000/rs6000-common.c (revision 191266) +++ gcc/common/config/rs6000/rs6000-common.c (working copy) @@ -74,7 +74,6 @@ rs6000_handle_option (struct gcc_options location_t loc) { enum fpu_type_t fpu_type = FPU_NONE; - char *p, *q; size_t code = decoded->opt_index; const char *arg = decoded->arg; int value = decoded->value; @@ -82,23 +81,25 @@ rs6000_handle_option (struct gcc_options switch (code) { case OPT_mfull_toc: - opts->x_target_flags &= ~MASK_MINIMAL_TOC; - opts->x_TARGET_NO_FP_IN_TOC = 0; - opts->x_TARGET_NO_SUM_IN_TOC = 0; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + rs6000_misc_flags &= ~(OPTION_MASK_NO_FP_IN_TOC + | OPTION_MASK_NO_SUM_IN_TOC); + opts_set->x_rs6000_misc_flags |= (OPTION_MASK_NO_FP_IN_TOC + | OPTION_MASK_NO_SUM_IN_TOC); #ifdef TARGET_USES_SYSV4_OPT /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be just the same as -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; #endif break; #ifdef TARGET_USES_SYSV4_OPT case OPT_mtoc: /* Make -mtoc behave like -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; break; #endif @@ -107,9 +108,10 @@ rs6000_handle_option (struct gcc_options #else case OPT_m64: #endif - opts->x_target_flags |= MASK_POWERPC64; - opts->x_target_flags |= ~opts_set->x_target_flags & MASK_PPC_GFXOPT; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; + opts->x_rs6000_isa_flags |= (~opts_set->x_rs6000_isa_flags + & OPTION_MASK_PPC_GFXOPT); + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; #ifdef TARGET_USES_AIX64_OPT @@ -117,63 +119,17 @@ rs6000_handle_option (struct gcc_options #else case OPT_m32: #endif - opts->x_target_flags &= ~MASK_POWERPC64; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_POWERPC64; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; case OPT_mminimal_toc: if (value == 1) { - opts->x_TARGET_NO_FP_IN_TOC = 0; - opts->x_TARGET_NO_SUM_IN_TOC = 0; - } - break; - - case OPT_mpowerpc_gpopt: - case OPT_mpowerpc_gfxopt: - break; - - case OPT_mdebug_: - p = ASTRDUP (arg); - opts->x_rs6000_debug = 0; - - while ((q = strtok (p, ",")) != NULL) - { - unsigned mask = 0; - bool invert; - - p = NULL; - if (*q == '!') - { - invert = true; - q++; - } - else - invert = false; - - if (! strcmp (q, "all")) - mask = MASK_DEBUG_ALL; - else if (! strcmp (q, "stack")) - mask = MASK_DEBUG_STACK; - else if (! strcmp (q, "arg")) - mask = MASK_DEBUG_ARG; - else if (! strcmp (q, "reg")) - mask = MASK_DEBUG_REG; - else if (! strcmp (q, "addr")) - mask = MASK_DEBUG_ADDR; - else if (! strcmp (q, "cost")) - mask = MASK_DEBUG_COST; - else if (! strcmp (q, "target")) - mask = MASK_DEBUG_TARGET; - else if (! strcmp (q, "builtin")) - mask = MASK_DEBUG_BUILTIN; - else - error_at (loc, "unknown -mdebug-%s switch", q); - - if (invert) - opts->x_rs6000_debug &= ~mask; - else - opts->x_rs6000_debug |= mask; + rs6000_misc_flags &= ~(OPTION_MASK_NO_FP_IN_TOC + | OPTION_MASK_NO_SUM_IN_TOC); + opts_set->x_rs6000_misc_flags |= (OPTION_MASK_NO_FP_IN_TOC + | OPTION_MASK_NO_SUM_IN_TOC); } break; @@ -181,23 +137,27 @@ rs6000_handle_option (struct gcc_options case OPT_mrelocatable: if (value == 1) { - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; - opts->x_TARGET_NO_FP_IN_TOC = 1; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + rs6000_misc_flags |= OPTION_MASK_NO_FP_IN_TOC; + opts_set->x_rs6000_misc_flags |= OPTION_MASK_NO_FP_IN_TOC; } break; case OPT_mrelocatable_lib: if (value == 1) { - opts->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; - opts->x_TARGET_NO_FP_IN_TOC = 1; + opts->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); + opts_set->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); + rs6000_misc_flags |= OPTION_MASK_NO_FP_IN_TOC; + opts_set->x_rs6000_misc_flags |= OPTION_MASK_NO_FP_IN_TOC; } else { - opts->x_target_flags &= ~MASK_RELOCATABLE; - opts_set->x_target_flags |= MASK_RELOCATABLE; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_RELOCATABLE; } break; #endif @@ -207,9 +167,11 @@ rs6000_handle_option (struct gcc_options opts->x_rs6000_spe_abi = 0; break; +#if TARGET_USES_SPE case OPT_mabi_spe: opts->x_rs6000_altivec_abi = 0; break; +#endif case OPT_mlong_double_: if (value != 64 && value != 128) @@ -227,15 +189,15 @@ rs6000_handle_option (struct gcc_options "-msingle-float option equivalent to -mhard-float"); /* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_double_float = 0; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_mdouble_float: /* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_single_float = 1; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_msimple_fpu: @@ -259,9 +221,12 @@ rs6000_handle_option (struct gcc_options { /* If -mfpu is not none, then turn off SOFT_FLOAT, turn on HARD_FLOAT. */ - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; - opts->x_rs6000_xilinx_fpu = 1; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; +#if TARGET_USES_XILINX_FPU + opts->x_rs6000_isa_flags |= OPTION_MASK_XILINX_FPU; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_XILINX_FPU; +#endif if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL) opts->x_rs6000_single_float = 1; if (fpu_type == FPU_DF_LITE || fpu_type == FPU_DF_FULL) @@ -272,8 +237,8 @@ rs6000_handle_option (struct gcc_options else { /* -mfpu=none is equivalent to -msoft-float. */ - opts->x_target_flags |= MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0; } break; @@ -281,6 +246,31 @@ rs6000_handle_option (struct gcc_options case OPT_mrecip: opts->x_rs6000_recip_name = (value) ? "default" : "none"; break; + + /* Note, the compiler must be configured explicitly for spe, paired, and + xilinx support. */ +#if !TARGET_USES_SPE + case OPT_mabi_no_spe: + case OPT_mabi_spe: + error ("not configured for SPE ABI"); + break; + + case OPT_mspe: + error ("not configured for SPE instruction set"); + break; +#endif + +#if !TARGET_USES_PAIRED_FLOAT + case OPT_mpaired: + error ("not configured for the 750CL paired floating point"); + break; +#endif + +#if !TARGET_USES_XILINX_FPU + case OPT_mxilinx_fpu: + error ("not configured for the xilinx_fpu"); + break; +#endif } return true; } @@ -297,8 +287,4 @@ rs6000_handle_option (struct gcc_options #undef TARGET_OPTION_OPTIMIZATION_TABLE #define TARGET_OPTION_OPTIMIZATION_TABLE rs6000_option_optimization_table -#undef TARGET_DEFAULT_TARGET_FLAGS -#define TARGET_DEFAULT_TARGET_FLAGS \ - (TARGET_DEFAULT) - struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; Index: gcc/config/rs6000/aix53.h =================================================================== --- gcc/config/rs6000/aix53.h (revision 191266) +++ gcc/config/rs6000/aix53.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/476.opt =================================================================== --- gcc/config/rs6000/476.opt (revision 191266) +++ gcc/config/rs6000/476.opt (working copy) @@ -20,5 +20,5 @@ ; <http://www.gnu.org/licenses/>. mpreserve-link-stack -Target Var(rs6000_link_stack) Init(-1) Save +Target Report InverseMask(NO_LINK_STACK) Var(rs6000_misc_flags) Preserve the PowerPC 476's link stack by matching up a blr with the bcl/bl insns used for GOT accesses Index: gcc/config/rs6000/linux.h =================================================================== --- gcc/config/rs6000/linux.h (revision 191266) +++ gcc/config/rs6000/linux.h (working copy) @@ -109,7 +109,7 @@ -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #define TARGET_POSIX_IO Index: gcc/config/rs6000/eabi.h =================================================================== --- gcc/config/rs6000/eabi.h (revision 191266) +++ gcc/config/rs6000/eabi.h (working copy) @@ -21,7 +21,7 @@ /* Add -meabi to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_EABI +#define TARGET_DEFAULT OPTION_MASK_EABI /* Invoke an initializer function to set up the GOT. */ #define NAME__MAIN "__eabi" Index: gcc/config/rs6000/t-rs6000 =================================================================== --- gcc/config/rs6000/t-rs6000 (revision 191266) +++ gcc/config/rs6000/t-rs6000 (working copy) @@ -26,7 +26,8 @@ rs6000.o: $(CONFIG_H) $(SYSTEM_H) corety $(OBSTACK_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) except.h function.h \ output.h dbxout.h $(BASIC_BLOCK_H) toplev.h $(GGC_H) $(HASHTAB_H) \ $(TM_P_H) $(TARGET_H) $(TARGET_DEF_H) langhooks.h reload.h gt-rs6000.h \ - cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) + cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) \ + $(srcdir)/config/rs6000/rs6000-cpus.def rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.c \ $(srcdir)/config/rs6000/rs6000-protos.h \ Index: gcc/config/rs6000/secureplt.h =================================================================== --- gcc/config/rs6000/secureplt.h (revision 191266) +++ gcc/config/rs6000/secureplt.h (working copy) @@ -18,3 +18,5 @@ along with GCC; see the file COPYING3. <http://www.gnu.org/licenses/>. */ #define CC1_SECURE_PLT_DEFAULT_SPEC "-msecure-plt" + +#define OPTION_MASK_DEFAULT_SECURE_PLT OPTION_MASK_SECURE_PLT Index: gcc/config/rs6000/linuxspe.h =================================================================== --- gcc/config/rs6000/linuxspe.h (revision 191266) +++ gcc/config/rs6000/linuxspe.h (working copy) @@ -21,7 +21,7 @@ /* Override rs6000.h and sysv4.h definition. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_STRICT_ALIGN +#define TARGET_DEFAULT OPTION_MASK_STRICT_ALIGN #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc -mspe -me500" Index: gcc/config/rs6000/eabialtivec.h =================================================================== --- gcc/config/rs6000/eabialtivec.h (revision 191266) +++ gcc/config/rs6000/eabialtivec.h (working copy) @@ -21,7 +21,7 @@ /* Add -meabi and -maltivec to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_EABI | MASK_ALTIVEC) +#define TARGET_DEFAULT (OPTION_MASK_EABI | OPTION_MASK_ALTIVEC) #undef SUBSUBTARGET_OVERRIDE_OPTIONS #define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1 Index: gcc/config/rs6000/476.h =================================================================== --- gcc/config/rs6000/476.h (revision 191266) +++ gcc/config/rs6000/476.h (working copy) @@ -23,10 +23,18 @@ <http://www.gnu.org/licenses/>. */ #undef TARGET_LINK_STACK -#define TARGET_LINK_STACK (rs6000_link_stack) +#define TARGET_LINK_STACK (! OPTION_NO_LINK_STACK) #undef SET_TARGET_LINK_STACK -#define SET_TARGET_LINK_STACK(X) do { TARGET_LINK_STACK = (X); } while (0) +#define SET_TARGET_LINK_STACK(X) \ +do \ + { \ + if (X) \ + rs6000_misc_flags &= ~OPTION_MASK_NO_LINK_STACK; \ + else \ + rs6000_misc_flags |= OPTION_MASK_NO_LINK_STACK; \ + } \ +while (0) #undef TARGET_ASM_CODE_END #define TARGET_ASM_CODE_END rs6000_code_end Index: gcc/config/rs6000/aix43.h =================================================================== --- gcc/config/rs6000/aix43.h (revision 191266) +++ gcc/config/rs6000/aix43.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/default64.h =================================================================== --- gcc/config/rs6000/default64.h (revision 191266) +++ gcc/config/rs6000/default64.h (working copy) @@ -19,4 +19,5 @@ along with GCC; see the file COPYING3. <http://www.gnu.org/licenses/>. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_64BIT) +#define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_POWERPC64 \ + | OPTION_MASK_64BIT) Index: gcc/config/rs6000/darwin64.h =================================================================== --- gcc/config/rs6000/darwin64.h (revision 191266) +++ gcc/config/rs6000/darwin64.h (working copy) @@ -19,8 +19,8 @@ <http://www.gnu.org/licenses/>. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \ - | MASK_MULTIPLE | MASK_PPC_GFXOPT) +#define TARGET_DEFAULT (OPTION_MASK_POWERPC64 | OPTION_MASK_64BIT \ + | OPTION_MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT) #undef DARWIN_ARCH_SPEC #define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}" Index: gcc/config/rs6000/darwin.opt =================================================================== --- gcc/config/rs6000/darwin.opt (revision 191266) +++ gcc/config/rs6000/darwin.opt (working copy) @@ -34,9 +34,9 @@ findirect-data Driver RejectNegative Alias(mfix-and-continue) m64 -Target RejectNegative Negative(m32) Mask(64BIT) +Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target RejectNegative Negative(m64) InverseMask(64BIT) +Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code Index: gcc/config/rs6000/rs6000-builtin.def =================================================================== --- gcc/config/rs6000/rs6000-builtin.def (revision 191266) +++ gcc/config/rs6000/rs6000-builtin.def (working copy) @@ -90,7 +90,7 @@ #define BU_ALTIVEC_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -98,7 +98,7 @@ #define BU_ALTIVEC_2(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_2 (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -106,7 +106,7 @@ #define BU_ALTIVEC_3(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_3 (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -114,7 +114,7 @@ #define BU_ALTIVEC_A(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_A (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_ABS), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -122,7 +122,7 @@ #define BU_ALTIVEC_D(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_D (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_DST), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -130,7 +130,7 @@ #define BU_ALTIVEC_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_P (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -138,7 +138,7 @@ #define BU_ALTIVEC_X(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -146,8 +146,8 @@ #define BU_ALTIVEC_C(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_altivec_" NAME, /* NAME */ \ - (RS6000_BTM_ALTIVEC /* MASK */ \ - | RS6000_BTM_CELL), \ + (OPTION_MASK_ALTIVEC /* MASK */ \ + | OPTION_MASK_CELL_BUILTIN), \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -156,7 +156,7 @@ #define BU_ALTIVEC_OVERLOAD_1(ENUM, NAME) \ RS6000_BUILTIN_1 (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -164,7 +164,7 @@ #define BU_ALTIVEC_OVERLOAD_2(ENUM, NAME) \ RS6000_BUILTIN_2 (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_nothing) /* ICODE */ @@ -172,7 +172,7 @@ #define BU_ALTIVEC_OVERLOAD_3(ENUM, NAME) \ RS6000_BUILTIN_3 (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -180,7 +180,7 @@ #define BU_ALTIVEC_OVERLOAD_A(ENUM, NAME) \ RS6000_BUILTIN_A (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_ABS), \ CODE_FOR_nothing) /* ICODE */ @@ -188,7 +188,7 @@ #define BU_ALTIVEC_OVERLOAD_D(ENUM, NAME) \ RS6000_BUILTIN_D (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_DST), \ CODE_FOR_nothing) /* ICODE */ @@ -196,7 +196,7 @@ #define BU_ALTIVEC_OVERLOAD_P(ENUM, NAME) \ RS6000_BUILTIN_P (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_nothing) /* ICODE */ @@ -204,7 +204,7 @@ #define BU_ALTIVEC_OVERLOAD_X(ENUM, NAME) \ RS6000_BUILTIN_X (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ + OPTION_MASK_ALTIVEC, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -213,7 +213,7 @@ #define BU_VSX_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -221,7 +221,7 @@ #define BU_VSX_2(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_2 (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -229,7 +229,7 @@ #define BU_VSX_3(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_3 (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -237,7 +237,7 @@ #define BU_VSX_A(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_A (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_ABS), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -245,7 +245,7 @@ #define BU_VSX_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_P (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -253,7 +253,7 @@ #define BU_VSX_X(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -262,7 +262,7 @@ #define BU_VSX_OVERLOAD_1(ENUM, NAME) \ RS6000_BUILTIN_1 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -270,7 +270,7 @@ #define BU_VSX_OVERLOAD_2(ENUM, NAME) \ RS6000_BUILTIN_2 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_nothing) /* ICODE */ @@ -278,7 +278,7 @@ #define BU_VSX_OVERLOAD_3(ENUM, NAME) \ RS6000_BUILTIN_3 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -288,7 +288,7 @@ #define BU_VSX_OVERLOAD_3V(ENUM, NAME) \ RS6000_BUILTIN_3 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_nothing) /* ICODE */ @@ -296,7 +296,7 @@ #define BU_VSX_OVERLOAD_X(ENUM, NAME) \ RS6000_BUILTIN_X (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ + OPTION_MASK_VSX, /* MASK */ \ (RS6000_BTC_OVERLOADED /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -305,7 +305,7 @@ #define BU_SPE_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -313,7 +313,7 @@ #define BU_SPE_2(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_2 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -321,7 +321,7 @@ #define BU_SPE_3(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_3 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -329,7 +329,7 @@ #define BU_SPE_E(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_E (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_EVSEL), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -337,7 +337,7 @@ #define BU_SPE_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_S (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -345,7 +345,7 @@ #define BU_SPE_X(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_spe_" NAME, /* NAME */ \ - RS6000_BTM_SPE, /* MASK */ \ + OPTION_MASK_SPE, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -354,7 +354,7 @@ #define BU_PAIRED_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -362,7 +362,7 @@ #define BU_PAIRED_2(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_2 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_BINARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -370,7 +370,7 @@ #define BU_PAIRED_3(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_3 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -378,7 +378,7 @@ #define BU_PAIRED_P(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_Q (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_PREDICATE), \ CODE_FOR_ ## ICODE) /* ICODE */ @@ -386,7 +386,7 @@ #define BU_PAIRED_X(ENUM, NAME, ATTR) \ RS6000_BUILTIN_X (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_paired_" NAME, /* NAME */ \ - RS6000_BTM_PAIRED, /* MASK */ \ + OPTION_MASK_PAIRED_FLOAT, /* MASK */ \ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ @@ -1413,22 +1413,22 @@ BU_SPE_X (MTSPEFSCR, "mtspefscr", \f /* Power7 builtins, that aren't VSX instructions. */ -BU_SPECIAL_X (POWER7_BUILTIN_BPERMD, "__builtin_bpermd", RS6000_BTM_POPCNTD, +BU_SPECIAL_X (POWER7_BUILTIN_BPERMD, "__builtin_bpermd", OPTION_MASK_POPCNTD, RS6000_BTC_CONST) /* Miscellaneous builtins. */ -BU_SPECIAL_X (RS6000_BUILTIN_RECIP, "__builtin_recipdiv", RS6000_BTM_FRE, +BU_SPECIAL_X (RS6000_BUILTIN_RECIP, "__builtin_recipdiv", OPTION_MASK_POPCNTB, RS6000_BTC_FP) -BU_SPECIAL_X (RS6000_BUILTIN_RECIPF, "__builtin_recipdivf", RS6000_BTM_FRES, - RS6000_BTC_FP) +BU_SPECIAL_X (RS6000_BUILTIN_RECIPF, "__builtin_recipdivf", + OPTION_MASK_PPC_GFXOPT, RS6000_BTC_FP) -BU_SPECIAL_X (RS6000_BUILTIN_RSQRT, "__builtin_rsqrt", RS6000_BTM_FRSQRTE, - RS6000_BTC_FP) +BU_SPECIAL_X (RS6000_BUILTIN_RSQRT, "__builtin_rsqrt", + OPTION_MASK_PPC_GFXOPT, RS6000_BTC_FP) -BU_SPECIAL_X (RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf", RS6000_BTM_FRSQRTES, +BU_SPECIAL_X (RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf", OPTION_MASK_POPCNTB, RS6000_BTC_FP) /* Darwin CfString builtin. */ -BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS, +BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", 0, RS6000_BTC_MISC) Index: gcc/config/rs6000/rs6000-c.c =================================================================== --- gcc/config/rs6000/rs6000-c.c (revision 191266) +++ gcc/config/rs6000/rs6000-c.c (working copy) @@ -41,9 +41,8 @@ where TOGGLE is either 0 or 1. - rs6000_default_long_calls is set to the value of TOGGLE, changing - whether or not new function declarations receive a longcall - attribute by default. */ + TARGET_LONG_CALLS is set to the value of TOGGLE, changing whether or not new + function declarations receive a longcall attribute by default. */ #define SYNTAX_ERROR(gmsgid) do { \ warning (OPT_Wpragmas, gmsgid); \ @@ -72,7 +71,10 @@ rs6000_pragma_longcall (cpp_reader *pfil if (pragma_lex (&x) != CPP_EOF) warning (OPT_Wpragmas, "junk at end of #pragma longcall"); - rs6000_default_long_calls = (n == integer_one_node); + if (n == integer_one_node) + rs6000_isa_flags |= OPTION_MASK_LONG_CALLS; + else + rs6000_isa_flags &= ~OPTION_MASK_LONG_CALLS; } /* Handle defining many CPP flags based on TARGET_xxx. As a general @@ -285,38 +287,38 @@ rs6000_define_or_undefine_macro (bool de have both the target flags and the builtin flags as arguments. */ void -rs6000_target_modify_macros (bool define_p, int flags, unsigned bu_mask) +rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) { if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) - fprintf (stderr, "rs6000_target_modify_macros (%s, 0x%x, 0x%x)\n", + fprintf (stderr, "rs6000_target_modify_macros (%s, 0x%lx)\n", (define_p) ? "define" : "undef", - (unsigned) flags, bu_mask); + (unsigned long) flags); - /* target_flags based options. */ + /* rs6000_isa_flags based options. */ rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); - if ((flags & MASK_PPC_GPOPT) != 0) + if ((flags & OPTION_MASK_PPC_GPOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ"); - if ((flags & MASK_PPC_GFXOPT) != 0) + if ((flags & OPTION_MASK_PPC_GFXOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR"); - if ((flags & MASK_POWERPC64) != 0) + if ((flags & OPTION_MASK_POWERPC64) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"); - if ((flags & MASK_MFCRF) != 0) + if ((flags & OPTION_MASK_MFCRF) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4"); - if ((flags & MASK_POPCNTB) != 0) + if ((flags & OPTION_MASK_POPCNTB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5"); - if ((flags & MASK_FPRND) != 0) + if ((flags & OPTION_MASK_FPRND) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X"); - if ((flags & MASK_CMPB) != 0) + if ((flags & OPTION_MASK_CMPB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); - if ((flags & MASK_MFPGPR) != 0) + if ((flags & OPTION_MASK_MFPGPR) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X"); - if ((flags & MASK_POPCNTD) != 0) + if ((flags & OPTION_MASK_POPCNTD) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); - if ((flags & MASK_SOFT_FLOAT) != 0) + if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); - if ((flags & MASK_RECIP_PRECISION) != 0) + if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__"); - if ((flags & MASK_ALTIVEC) != 0) + if ((flags & OPTION_MASK_ALTIVEC) != 0) { const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__"; rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__"); @@ -326,15 +328,15 @@ rs6000_target_modify_macros (bool define if (!flag_iso) rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__"); } - if ((flags & MASK_VSX) != 0) + if ((flags & OPTION_MASK_VSX) != 0) rs6000_define_or_undefine_macro (define_p, "__VSX__"); /* options from the builtin masks. */ - if ((bu_mask & RS6000_BTM_SPE) != 0) + if ((flags & OPTION_MASK_SPE) != 0) rs6000_define_or_undefine_macro (define_p, "__SPE__"); - if ((bu_mask & RS6000_BTM_PAIRED) != 0) + if ((flags & OPTION_MASK_PAIRED_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "__PAIRED__"); - if ((bu_mask & RS6000_BTM_CELL) != 0) + if ((flags & OPTION_MASK_CELL_BUILTIN) != 0) rs6000_define_or_undefine_macro (define_p, "__PPU__"); } @@ -342,8 +344,7 @@ void rs6000_cpu_cpp_builtins (cpp_reader *pfile) { /* Define all of the common macros. */ - rs6000_target_modify_macros (true, target_flags, - rs6000_builtin_mask_calculate ()); + rs6000_target_modify_macros (true, rs6000_isa_flags); if (TARGET_FRE) builtin_define ("__RECIP__"); @@ -463,7 +464,7 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfi builtin_define ("__NO_FPRS__"); /* Generate defines for Xilinx FPU. */ - if (rs6000_xilinx_fpu) + if (TARGET_XILINX_FPU) { builtin_define ("_XFPU"); if (rs6000_single_float && ! rs6000_double_float) Index: gcc/config/rs6000/rs6000.opt =================================================================== --- gcc/config/rs6000/rs6000.opt (revision 191266) +++ gcc/config/rs6000/rs6000.opt (working copy) @@ -22,6 +22,39 @@ HeaderInclude config/rs6000/rs6000-opts.h +;; ISA flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags + +;; Miscellaneous flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags_explicit + +;; Miscellaneous flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_misc_flags = TARGET_MISC_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_misc_flags + +;; Miscellaneous flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_misc_flags_explicit + +;; Debug flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_debug_flags = TARGET_DEBUG_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_debug_flags + +;; Debug flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_debug_flags_explicit + ;; Current processor TargetVariable enum processor_type rs6000_cpu = PROCESSOR_PPC603 @@ -80,161 +113,161 @@ unsigned int rs6000_recip_control ;; Mask of what builtin functions are allowed TargetVariable -unsigned int rs6000_builtin_mask +HOST_WIDE_INT rs6000_builtin_mask ;; Debug flags TargetVariable unsigned int rs6000_debug -;; Save for target_flags_explicit -TargetSave -int rs6000_target_flags_explicit - ;; This option existed in the past, but now is always on. mpowerpc Target RejectNegative Undocumented Ignore mpowerpc64 -Target Report Mask(POWERPC64) +Target Report Mask(POWERPC64) Var(rs6000_isa_flags) Use PowerPC-64 instruction set mpowerpc-gpopt -Target Report Mask(PPC_GPOPT) Save +Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) Use PowerPC General Purpose group optional instructions mpowerpc-gfxopt -Target Report Mask(PPC_GFXOPT) Save +Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) Use PowerPC Graphics group optional instructions mmfcrf -Target Report Mask(MFCRF) Save +Target Report Mask(MFCRF) Var(rs6000_isa_flags) Use PowerPC V2.01 single field mfcr instruction mpopcntb -Target Report Mask(POPCNTB) Save +Target Report Mask(POPCNTB) Var(rs6000_isa_flags) Use PowerPC V2.02 popcntb instruction mfprnd -Target Report Mask(FPRND) Save +Target Report Mask(FPRND) Var(rs6000_isa_flags) Use PowerPC V2.02 floating point rounding instructions mcmpb -Target Report Mask(CMPB) Save +Target Report Mask(CMPB) Var(rs6000_isa_flags) Use PowerPC V2.05 compare bytes instruction mmfpgpr -Target Report Mask(MFPGPR) Save +Target Report Mask(MFPGPR) Var(rs6000_isa_flags) Use extended PowerPC V2.05 move floating point to/from GPR instructions maltivec -Target Report Mask(ALTIVEC) Save +Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) Use AltiVec instructions mhard-dfp -Target Report Mask(DFP) Save +Target Report Mask(DFP) Var(rs6000_isa_flags) Use decimal floating point instructions mmulhw -Target Report Mask(MULHW) Save +Target Report Mask(MULHW) Var(rs6000_isa_flags) Use 4xx half-word multiply instructions mdlmzb -Target Report Mask(DLMZB) Save +Target Report Mask(DLMZB) Var(rs6000_isa_flags) Use 4xx string-search dlmzb instruction mmultiple -Target Report Mask(MULTIPLE) Save +Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) Generate load/store multiple instructions mstring -Target Report Mask(STRING) Save +Target Report Mask(STRING) Var(rs6000_isa_flags) Generate string instructions for block moves msoft-float -Target Report RejectNegative Mask(SOFT_FLOAT) +Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) Do not use hardware floating point mhard-float -Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) +Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) Use hardware floating point mpopcntd -Target Report Mask(POPCNTD) Save +Target Report Mask(POPCNTD) Var(rs6000_isa_flags) Use PowerPC V2.06 popcntd instruction +mno-friz +Target Report RejectNegative Mask(NO_FRIZ) Var(rs6000_isa_flags) +Under -ffast-math, do not generate a FRIZ instruction for (double)(long long) conversions + mfriz -Target Report Var(TARGET_FRIZ) Init(-1) Save +Target Report RejectNegative InverseMask(NO_FRIZ, FRIZ) Var(rs6000_isa_flags) Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions +mcell-builtins +Target Undocumented Report Mask(CELL_BUILTIN) Var(rs6000_isa_flags) +; Enable cell builtins + mveclibabi= Target RejectNegative Joined Var(rs6000_veclibabi_name) Vector library ABI to use mvsx -Target Report Mask(VSX) Save +Target Report Mask(VSX) Var(rs6000_isa_flags) Use vector/scalar (VSX) instructions mvsx-scalar-double -Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1) +Target Report Undocumented Mask(VSX_SCALAR_DOUBLE) Var(rs6000_misc_flags) ; If -mvsx, use VSX arithmetic instructions for scalar double (on by default) mvsx-scalar-memory -Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY) +Target Report Undocumented Mask(VSX_SCALAR_MEMORY) Var(rs6000_misc_flags) ; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default) mvsx-align-128 -Target Undocumented Report Var(TARGET_VSX_ALIGN_128) +Target Report Undocumented Mask(VSX_ALIGN_128) Var(rs6000_misc_flags) ; If -mvsx, set alignment to 128 bits instead of 32/64 mallow-movmisalign -Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) +Target Report Undocumented Mask(ALLOW_MOVMISALIGN) Var(rs6000_misc_flags) ; Allow/disallow the movmisalign in DF/DI vectors -mallow-df-permute -Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) -; Allow/disallow permutation of DF/DI vectors - msched-groups -Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) +Target Undocumented Report Mask(SCHED_GROUPS) Var(rs6000_isa_flags) ; Explicitly set/unset whether rs6000_sched_groups is set malways-hint -Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) +Target Undocumented Report InverseMask(NO_HINT) Var(rs6000_isa_flags) ; Explicitly set/unset whether rs6000_always_hint is set malign-branch-targets -Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) +Target Undocumented Report Mask(ALIGN_BRANCH_TARGETS) Var(rs6000_isa_flags) ; Explicitly set/unset whether rs6000_align_branch_targets is set mvectorize-builtins -Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) +Target Undocumented Report Mask(VECTORIZE_BUILTINS) Var(rs6000_misc_flags) ; Explicitly control whether we vectorize the builtins or not. mno-update -Target Report RejectNegative Mask(NO_UPDATE) Save +Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) Do not generate load/store with update instructions mupdate -Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) +Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) Generate load/store with update instructions msingle-pic-base -Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0) +Target Report Mask(SINGLE_PIC_BASE) Var(rs6000_misc_flags) Do not load the PIC register in function prologues mavoid-indexed-addresses -Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save +Target Report Mask(AVOID_XFORM) Var(rs6000_isa_flags) Avoid generation of indexed load/store instructions when possible mtls-markers -Target Report Var(tls_markers) Init(1) Save +Target Report Mask(TLS_MARKERS) Var(rs6000_misc_flags) Mark __tls_get_addr calls with argument info msched-epilog -Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save +Target Report Undocumented Mask(SCHED_PROLOG) Var(rs6000_misc_flags) msched-prolog -Target Report Var(TARGET_SCHED_PROLOG) Save +Target Report Mask(SCHED_PROLOG) Var(rs6000_misc_flags) Schedule the start and end of the procedure maix-struct-return @@ -246,7 +279,7 @@ Target Report RejectNegative Var(aix_str Return small structures in registers (SVR4 default) mxl-compat -Target Report Var(TARGET_XL_COMPAT) Save +Target Report Mask(XL_COMPAT) Var(rs6000_misc_flags) Conform more closely to IBM XLC semantics mrecip @@ -258,24 +291,16 @@ Target Report RejectNegative Joined Var( Generate software reciprocal divide and square root for better throughput. mrecip-precision -Target Report Mask(RECIP_PRECISION) Save +Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) Assume that the reciprocal estimate instructions provide more accuracy. -mno-fp-in-toc -Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save -Do not place floating point constants in TOC - mfp-in-toc -Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save -Place floating point constants in TOC - -mno-sum-in-toc -Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save -Do not place symbol+offset constants in TOC +Target Report InverseMask(NO_FP_IN_TOC) Var(rs6000_misc_flags) +Place/do not place floating point constants in TOC msum-in-toc -Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save -Place symbol+offset constants in TOC +Target Report InverseMask(NO_SUM_IN_TOC) Var(rs6000_misc_flags) +Place/do not place symbol+offset constants in TOC ; Output only one TOC entry per module. Normally linking fails if ; there are more than 16K unique variables/constants in an executable. With @@ -285,7 +310,7 @@ Place symbol+offset constants in TOC ; This is at the cost of having 2 extra loads and one extra store per ; function, and one less allocable register. mminimal-toc -Target Report Mask(MINIMAL_TOC) +Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) Use only one TOC entry per procedure mfull-toc @@ -293,7 +318,7 @@ Target Report Put everything in the regular TOC mvrsave -Target Report Var(TARGET_ALTIVEC_VRSAVE) Save +Target Report Mask(ALTIVEC_VRSAVE) Var(rs6000_misc_flags) Generate VRSAVE instructions when generating AltiVec code mvrsave=no @@ -309,7 +334,7 @@ Target Report Var(rs6000_block_move_inli Specify how many bytes should be moved inline before calling out to memcpy/memmove misel -Target Report Mask(ISEL) Save +Target Report Mask(ISEL) Var(rs6000_isa_flags) Generate isel instructions misel=no @@ -321,13 +346,9 @@ Target RejectNegative Alias(misel) Deprecated option. Use -misel instead mspe -Target Var(rs6000_spe) Save +Target Report Mask(SPE) Var(rs6000_isa_flags) Generate SPE SIMD instructions on E500 -mpaired -Target Var(rs6000_paired_float) Save -Generate PPC750CL paired-single instructions - mspe=no Target RejectNegative Alias(mspe) NegativeAlias Deprecated option. Use -mno-spe instead @@ -336,9 +357,54 @@ mspe=yes Target RejectNegative Alias(mspe) Deprecated option. Use -mspe instead -mdebug= -Target RejectNegative Joined --mdebug= Enable debug output +mpaired +Target Report Mask(PAIRED_FLOAT) Var(rs6000_isa_flags) +Generate PPC750CL paired-single instructions + +mdebug=all +Target Report RejectNegative Undocumented Mask(DEBUG_ALL) Var(rs6000_debug_flags) + +mdebug=addr +Target Report RejectNegative Undocumented Mask(DEBUG_ADDR) Var(rs6000_debug_flags) + +mdebug=noaddr +Target Report RejectNegative Undocumented InverseMask(DEBUG_ADDR) Var(rs6000_debug_flags) + +mdebug=arg +Target Report RejectNegative Undocumented Mask(DEBUG_ARG) Var(rs6000_debug_flags) + +mdebug=noarg +Target Report RejectNegative Undocumented InverseMask(DEBUG_ARG) Var(rs6000_debug_flags) + +mdebug=builtin +Target Report RejectNegative Undocumented Mask(DEBUG_BUILTIN) Var(rs6000_debug_flags) + +mdebug=nobuiltin +Target Report RejectNegative Undocumented InverseMask(DEBUG_BUILTIN) Var(rs6000_debug_flags) + +mdebug=cost +Target Report RejectNegative Undocumented Mask(DEBUG_COST) Var(rs6000_debug_flags) + +mdebug=nocost +Target Report RejectNegative Undocumented InverseMask(DEBUG_COST) Var(rs6000_debug_flags) + +mdebug=reg +Target Report RejectNegative Undocumented Mask(DEBUG_REG) Var(rs6000_debug_flags) + +mdebug=noreg +Target Report RejectNegative Undocumented InverseMask(DEBUG_REG) Var(rs6000_debug_flags) + +mdebug=stack +Target Report RejectNegative Undocumented Mask(DEBUG_STACK) Var(rs6000_debug_flags) + +mdebug=nostack +Target Report RejectNegative Undocumented InverseMask(DEBUG_STACK) Var(rs6000_debug_flags) + +mdebug=target +Target Report RejectNegative Undocumented Mask(DEBUG_TARGET) Var(rs6000_debug_flags) + +mdebug=notarget +Target Report RejectNegative Undocumented InverseMask(DEBUG_TARGET) Var(rs6000_debug_flags) mabi=altivec Target RejectNegative Var(rs6000_altivec_abi) Save @@ -397,19 +463,19 @@ EnumValue Enum(rs6000_traceback_type) String(no) Value(traceback_none) mlongcall -Target Report Var(rs6000_default_long_calls) Save +Target Report Mask(LONG_CALLS) Var(rs6000_isa_flags) Avoid all range limits on call instructions mgen-cell-microcode -Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save +Target Report Mask(GEN_CELL_MICROCODE) Var(rs6000_misc_flags) Generate Cell microcode mwarn-cell-microcode -Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save +Target Report Warning Mask(WARN_CELL_MICROCODE) Var(rs6000_misc_flags) Warn when a Cell microcoded instruction is emitted mwarn-altivec-long -Target Var(rs6000_warn_altivec_long) Init(1) Save +Target Report Mask(WARN_ALTIVEC_LONG) Var(rs6000_misc_flags) Warn about deprecated 'vector long ...' AltiVec type usage mfloat-gprs= @@ -497,13 +563,13 @@ EnumValue Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL) mxilinx-fpu -Target Var(rs6000_xilinx_fpu) Save +Target Report Var(rs6000_isa_flags) Mask(XILINX_FPU) Specify Xilinx FPU. mpointers-to-nested-functions -Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save +Target Report Mask(POINTERS_TO_NESTED_FUNCTIONS) Var(rs6000_misc_flags) Use/do not use r11 to hold the static link in calls to functions via pointers. msave-toc-indirect -Target Report Var(TARGET_SAVE_TOC_INDIRECT) Save +Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_misc_flags) Control whether we save the TOC in the prologue for indirect calls or generate the save inline Index: gcc/config/rs6000/linuxaltivec.h =================================================================== --- gcc/config/rs6000/linuxaltivec.h (revision 191266) +++ gcc/config/rs6000/linuxaltivec.h (working copy) @@ -21,7 +21,7 @@ /* Override rs6000.h and sysv4.h definition. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_ALTIVEC +#define TARGET_DEFAULT OPTION_MASK_ALTIVEC #undef SUBSUBTARGET_OVERRIDE_OPTIONS #define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1 Index: gcc/config/rs6000/linux64.h =================================================================== --- gcc/config/rs6000/linux64.h (revision 191266) +++ gcc/config/rs6000/linux64.h (working copy) @@ -37,7 +37,7 @@ #else -#define DEFAULT_ARCH64_P (TARGET_DEFAULT & MASK_64BIT) +#define DEFAULT_ARCH64_P (TARGET_DEFAULT & OPTION_MASK_64BIT) #define RS6000_BI_ARCH_P 1 #endif @@ -61,7 +61,7 @@ extern int dot_symbols; #define DOT_SYMBOLS dot_symbols #endif -#define TARGET_PROFILE_KERNEL profile_kernel +#define TARGET_PROFILE_KERNEL OPTION_PROFILE_KERNEL #define TARGET_USES_LINUX64_OPT 1 #ifdef HAVE_LD_LARGE_TOC @@ -81,7 +81,7 @@ extern int dot_symbols; -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "linux" @@ -103,27 +103,28 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ - if (target_flags & MASK_RELOCATABLE) \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error (INVALID_64BIT, "relocatable"); \ } \ - if (target_flags & MASK_EABI) \ + if (rs6000_isa_flags & OPTION_MASK_EABI) \ { \ - target_flags &= ~MASK_EABI; \ + rs6000_isa_flags &= ~OPTION_MASK_EABI; \ error (INVALID_64BIT, "eabi"); \ } \ if (TARGET_PROTOTYPE) \ { \ - target_prototype = 0; \ + rs6000_misc_flags &= ~OPTION_MASK_PROTOTYPE; \ error (INVALID_64BIT, "prototype"); \ } \ - if ((target_flags & MASK_POWERPC64) == 0) \ + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ error ("-m64 requires a PowerPC64 cpu"); \ } \ - if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ + if ((rs6000_isa_flags_explicit \ + & OPTION_MASK_MINIMAL_TOC) != 0) \ { \ if (global_options_set.x_rs6000_current_cmodel \ && rs6000_current_cmodel != CMODEL_SMALL) \ @@ -136,8 +137,8 @@ extern int dot_symbols; SET_CMODEL (CMODEL_MEDIUM); \ if (rs6000_current_cmodel != CMODEL_SMALL) \ { \ - TARGET_NO_FP_IN_TOC = 0; \ - TARGET_NO_SUM_IN_TOC = 0; \ + rs6000_misc_flags &= ~(OPTION_MASK_NO_FP_IN_TOC \ + | OPTION_MASK_NO_SUM_IN_TOC); \ } \ } \ } \ @@ -147,7 +148,7 @@ extern int dot_symbols; error (INVALID_32BIT, "32"); \ if (TARGET_PROFILE_KERNEL) \ { \ - TARGET_PROFILE_KERNEL = 0; \ + rs6000_misc_flags &= ~OPTION_MASK_PROFILE_KERNEL; \ error (INVALID_32BIT, "profile-kernel"); \ } \ if (global_options_set.x_rs6000_current_cmodel) \ @@ -213,20 +214,20 @@ extern int dot_symbols; #ifndef RS6000_BI_ARCH /* 64-bit PowerPC Linux is always big-endian. */ -#undef TARGET_LITTLE_ENDIAN -#define TARGET_LITTLE_ENDIAN 0 +#undef OPTION_LITTLE_ENDIAN +#define OPTION_LITTLE_ENDIAN 0 /* 64-bit PowerPC Linux always has a TOC. */ #undef TARGET_TOC #define TARGET_TOC 1 /* Some things from sysv4.h we don't do when 64 bit. */ -#undef TARGET_RELOCATABLE -#define TARGET_RELOCATABLE 0 -#undef TARGET_EABI -#define TARGET_EABI 0 -#undef TARGET_PROTOTYPE -#define TARGET_PROTOTYPE 0 +#undef OPTION_RELOCATABLE +#define OPTION_RELOCATABLE 0 +#undef OPTION_EABI +#define OPTION_EABI 0 +#undef OPTION_PROTOTYPE +#define OPTION_PROTOTYPE 0 #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP 0 Index: gcc/config/rs6000/darwin.h =================================================================== --- gcc/config/rs6000/darwin.h (revision 191266) +++ gcc/config/rs6000/darwin.h (working copy) @@ -280,7 +280,7 @@ extern int darwin_emit_branch_islands; default as well. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_PPC_GFXOPT) +#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT) /* Darwin always uses IBM long double, never IEEE long double. */ #undef TARGET_IEEEQUAD Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 191266) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -213,7 +213,7 @@ static GTY(()) section *toc_section; struct builtin_description { - const unsigned int mask; + const HOST_WIDE_INT mask; const enum insn_code icode; const char *const name; const enum rs6000_builtins code; @@ -287,7 +287,7 @@ typedef rtx (*gen_2arg_fn_t) (rtx, rtx, /* Pointer to function (in rs6000-c.c) that can define or undefine target macros that have changed. Languages that don't support the preprocessor don't link in rs6000-c.c, so we can't call it directly. */ -void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned); +void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT); \f /* Target cpu costs. */ @@ -893,7 +893,7 @@ struct processor_costs ppca2_cost = { struct rs6000_builtin_info_type { const char *name; const enum insn_code icode; - const unsigned mask; + const HOST_WIDE_INT mask; const unsigned attr; }; @@ -1015,6 +1015,9 @@ bool (*rs6000_cannot_change_mode_class_p const int INSN_NOT_AVAILABLE = -1; +static void rs6000_print_isa_options (FILE *, HOST_WIDE_INT); +static void rs6000_print_misc_options (FILE *, HOST_WIDE_INT); + /* Hash table stuff for keeping track of TOC entries. */ struct GTY(()) toc_hash_struct @@ -1115,8 +1118,8 @@ static const struct attribute_spec rs600 { NULL, 0, 0, false, false, false, NULL, false } }; \f -#ifndef MASK_STRICT_ALIGN -#define MASK_STRICT_ALIGN 0 +#ifndef OPTION_MASK_STRICT_ALIGN +#define OPTION_MASK_STRICT_ALIGN 0 #endif #ifndef TARGET_PROFILE_KERNEL #define TARGET_PROFILE_KERNEL 0 @@ -1458,53 +1461,12 @@ static const struct attribute_spec rs600 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok \f -/* Simplifications for entries below. */ - -enum { - POWERPC_7400_MASK = MASK_PPC_GFXOPT | MASK_ALTIVEC -}; - -/* Some OSs don't support saving the high part of 64-bit registers on context - switch. Other OSs don't support saving Altivec registers. On those OSs, we - don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants - either, the user must explicitly specify them and we won't interfere with - the user's specification. */ - -enum { - POWERPC_MASKS = (MASK_PPC_GPOPT | MASK_STRICT_ALIGN - | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC - | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW - | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP - | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE - | MASK_RECIP_PRECISION) -}; - -/* Masks for instructions set at various powerpc ISAs. */ -enum { - ISA_2_1_MASKS = MASK_MFCRF, - ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB), - ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND), - - /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add - ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, - fre, fsqrt, etc. were no longer documented as optional. Group masks by - server and embedded. */ - ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION - | MASK_PPC_GFXOPT | MASK_PPC_GPOPT), - ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP), - - /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but - altivec is a win so enable it. */ - ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD), - ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC - | MASK_VSX) -}; - +/* Processor table. */ struct rs6000_ptt { const char *const name; /* Canonical processor name. */ const enum processor_type processor; /* Processor type enum value. */ - const int target_enable; /* Target flags to enable. */ + const HOST_WIDE_INT target_enable; /* Target flags to enable. */ }; static struct rs6000_ptt const processor_target_table[] = @@ -1715,9 +1677,12 @@ rs6000_debug_reg_print (int first_regno, } } -#define DEBUG_FMT_D "%-32s= %d\n" -#define DEBUG_FMT_X "%-32s= 0x%x\n" -#define DEBUG_FMT_S "%-32s= %s\n" +#define DEBUG_FMT_ID "%-32s= " +#define DEBUG_FMT_D DEBUG_FMT_ID "%d\n" +#define DEBUG_FMT_X DEBUG_FMT_ID "%#x\n" +#define DEBUG_FMT_WX DEBUG_FMT_ID HOST_WIDE_INT_PRINT_HEX ": " +#define DEBUG_FMT_WX2 DEBUG_FMT_ID HOST_WIDE_INT_PRINT_HEX "\n" +#define DEBUG_FMT_S DEBUG_FMT_ID "%s\n" /* Print various interesting information with -mdebug=reg. */ static void @@ -1728,11 +1693,13 @@ rs6000_debug_reg_global (void) int m; char costly_num[20]; char nop_num[20]; + char flags_buffer[40]; const char *costly_str; const char *nop_str; const char *trace_str; const char *abi_str; const char *cmodel_str; + struct cl_target_option cl_opts; /* Map enum rs6000_vector to string. */ static const char *rs6000_debug_vector_unit[] = { @@ -1812,12 +1779,90 @@ rs6000_debug_reg_global (void) } if (rs6000_cpu_index >= 0) - fprintf (stderr, DEBUG_FMT_S, "cpu", - processor_target_table[rs6000_cpu_index].name); + { + const char *name = processor_target_table[rs6000_cpu_index].name; + fprintf (stderr, DEBUG_FMT_S, "cpu", name); + sprintf (flags_buffer, "%s cpu flags", name); + + if (processor_target_table[rs6000_cpu_index].target_enable) + { + HOST_WIDE_INT flags + = processor_target_table[rs6000_cpu_index].target_enable; + fprintf (stderr, DEBUG_FMT_WX, flags_buffer, flags); + rs6000_print_isa_options (stderr, flags); + } + else + fprintf (stderr, DEBUG_FMT_S, flags_buffer, "<none>"); + } + else + fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>"); if (rs6000_tune_index >= 0) - fprintf (stderr, DEBUG_FMT_S, "tune", - processor_target_table[rs6000_tune_index].name); + { + const char *name = processor_target_table[rs6000_tune_index].name; + fprintf (stderr, DEBUG_FMT_S, "tune", name); + sprintf (flags_buffer, "%s tune flags", name); + + if (processor_target_table[rs6000_tune_index].target_enable) + { + HOST_WIDE_INT flags + = processor_target_table[rs6000_tune_index].target_enable; + fprintf (stderr, DEBUG_FMT_WX, flags_buffer, flags); + rs6000_print_isa_options (stderr, flags); + } + else + fprintf (stderr, DEBUG_FMT_S, flags_buffer, "<none>"); + } + else + fprintf (stderr, DEBUG_FMT_S, "tune", "<none>"); + + cl_target_option_save (&cl_opts, &global_options); + if (rs6000_isa_flags) + { + fprintf (stderr, DEBUG_FMT_WX, "rs6000_isa_flags", rs6000_isa_flags); + rs6000_print_isa_options (stderr, rs6000_isa_flags); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_isa_flags", "<none>"); + + if (rs6000_isa_flags_explicit) + { + fprintf (stderr, DEBUG_FMT_WX, "rs6000_isa_flags_explicit", + rs6000_isa_flags_explicit); + rs6000_print_isa_options (stderr, rs6000_isa_flags_explicit); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_isa_flags_explicit", "<none>"); + + if (rs6000_misc_flags) + { + fprintf (stderr, DEBUG_FMT_WX, "rs6000_misc_flags", rs6000_misc_flags); + rs6000_print_misc_options (stderr, rs6000_misc_flags); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_misc_flags", "<none>"); + + if (rs6000_misc_flags_explicit) + { + fprintf (stderr, DEBUG_FMT_WX, "rs6000_misc_flags_explicit", + rs6000_misc_flags_explicit); + rs6000_print_misc_options (stderr, rs6000_misc_flags_explicit); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_misc_flags_explicit", "<none>"); + + fprintf (stderr, DEBUG_FMT_WX2, "rs6000_debug_flags", rs6000_debug_flags); + fprintf (stderr, DEBUG_FMT_WX2, "rs6000_debug_flags_explicit", + rs6000_debug_flags_explicit); + + if (rs6000_builtin_mask) + { + fprintf (stderr, DEBUG_FMT_WX, "rs6000_builtin_mask", + rs6000_builtin_mask); + rs6000_print_isa_options (stderr, rs6000_builtin_mask); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_builtin_mask", "<none>"); switch (rs6000_sched_costly_dep) { @@ -1935,7 +1980,15 @@ rs6000_debug_reg_global (void) if (rs6000_float_gprs) fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true"); + if (TARGET_LINK_STACK) + fprintf (stderr, DEBUG_FMT_S, "link_stack", "true"); + + fprintf (stderr, DEBUG_FMT_S, "plt-format", + TARGET_SECURE_PLT ? "secure" : "bss"); + fprintf (stderr, DEBUG_FMT_S, "struct-return", + aix_struct_return ? "aix" : "sysv"); fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]); + fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]); fprintf (stderr, DEBUG_FMT_S, "align_branch", tf[!!rs6000_align_branch_targets]); fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size); @@ -1947,7 +2000,6 @@ rs6000_debug_reg_global (void) (int)END_BUILTINS); fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins", (int)RS6000_BUILTIN_COUNT); - fprintf (stderr, DEBUG_FMT_X, "Builtin mask", rs6000_builtin_mask); } /* Initialize the various global tables that are based on register size. */ @@ -2302,7 +2354,7 @@ darwin_rs6000_override_options (void) /* The Darwin ABI always includes AltiVec, can't be (validly) turned off. */ rs6000_altivec_abi = 1; - TARGET_ALTIVEC_VRSAVE = 1; + rs6000_misc_flags |= OPTION_MASK_ALTIVEC_VRSAVE; rs6000_current_abi = ABI_DARWIN; if (DEFAULT_ABI == ABI_DARWIN @@ -2311,21 +2363,18 @@ darwin_rs6000_override_options (void) if (TARGET_64BIT && ! TARGET_POWERPC64) { - target_flags |= MASK_POWERPC64; + rs6000_isa_flags |= OPTION_MASK_POWERPC64; warning (0, "-m64 requires PowerPC64 architecture, enabling"); } if (flag_mkernel) - { - rs6000_default_long_calls = 1; - target_flags |= MASK_SOFT_FLOAT; - } + rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT | OPTION_MASK_LONG_CALLS; /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes Altivec. */ if (!flag_mkernel && !flag_apple_kext && TARGET_64BIT - && ! (target_flags_explicit & MASK_ALTIVEC)) - target_flags |= MASK_ALTIVEC; + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)) + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; /* Unless the user (not the configurer) has explicitly overridden it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to @@ -2333,10 +2382,10 @@ darwin_rs6000_override_options (void) if (!flag_mkernel && !flag_apple_kext && strverscmp (darwin_macosx_version_min, "10.5") >= 0 - && ! (target_flags_explicit & MASK_ALTIVEC) + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC) && ! global_options_set.x_rs6000_cpu_index) { - target_flags |= MASK_ALTIVEC; + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; } } #endif @@ -2348,26 +2397,25 @@ darwin_rs6000_override_options (void) #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64 #endif -/* Return the builtin mask of the various options used that could affect which - builtins were used. In the past we used target_flags, but we've run out of - bits, and some options like SPE and PAIRED are no longer in - target_flags. */ - -unsigned -rs6000_builtin_mask_calculate (void) -{ - return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) - | ((TARGET_VSX) ? RS6000_BTM_VSX : 0) - | ((TARGET_SPE) ? RS6000_BTM_SPE : 0) - | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0) - | ((TARGET_FRE) ? RS6000_BTM_FRE : 0) - | ((TARGET_FRES) ? RS6000_BTM_FRES : 0) - | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0) - | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0) - | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0) - | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)); +/* Helper function for rs6000_option_override_internal, that returns whether an + option is set in the tuning flags, but allow an override from the switches + if it was set explicitly. */ +static inline HOST_WIDE_INT +rs6000_operand_tuning_flag (HOST_WIDE_INT option_mask) +{ + HOST_WIDE_INT mask = rs6000_isa_flags; + + if (rs6000_tune_index >= 0 && + (rs6000_isa_flags_explicit & option_mask) == 0) + mask = processor_target_table[rs6000_tune_index].target_enable; + + return (mask & option_mask); } + /* Allow the explicit debug switches to override the tuning settings. If no + explicit switch, fall back to the tuning options instead of the cpu + options. */ + /* Override command line options. Mostly we process the processor type and sometimes adjust other TARGET_ options. */ @@ -2380,13 +2428,17 @@ rs6000_option_override_internal (bool gl /* The default cpu requested at configure time, if any. */ const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT; - int set_masks; + HOST_WIDE_INT set_masks; int cpu_index; int tune_index; struct cl_target_option *main_target_opt = ((global_init_p || target_option_default_node == NULL) ? NULL : TREE_TARGET_OPTION (target_option_default_node)); + /* If -mdebug=all, enable all debug options excepct those explicitly set. */ + if (TARGET_DEBUG_ALL) + rs6000_debug_flags |= (ALL_DEBUG_MASKS & ~rs6000_debug_flags_explicit); + /* On 64-bit Darwin, power alignment is ABI-incompatible with some C library functions, so warn about it. The flag may be useful for performance studies from time to time though, so don't disable it @@ -2417,18 +2469,24 @@ rs6000_option_override_internal (bool gl rs6000_pointer_size = 32; } - set_masks = POWERPC_MASKS | MASK_SOFT_FLOAT; + /* Some OSs don't support saving the high part of 64-bit registers on context + switch. Other OSs don't support saving Altivec registers. On those OSs, + we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings; + if the user wants either, the user must explicitly specify them and we + won't interfere with the user's specification. */ + + set_masks = POWERPC_MASKS; #ifdef OS_MISSING_POWERPC64 if (OS_MISSING_POWERPC64) - set_masks &= ~MASK_POWERPC64; + set_masks &= ~OPTION_MASK_POWERPC64; #endif #ifdef OS_MISSING_ALTIVEC if (OS_MISSING_ALTIVEC) - set_masks &= ~MASK_ALTIVEC; + set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX); #endif /* Don't override by the processor default if given explicitly. */ - set_masks &= ~target_flags_explicit; + set_masks &= ~rs6000_isa_flags_explicit; /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed the cpu in a target attribute or pragma, but did not specify a tuning @@ -2457,9 +2515,9 @@ rs6000_option_override_internal (bool gl gcc_assert (cpu_index >= 0); - target_flags &= ~set_masks; - target_flags |= (processor_target_table[cpu_index].target_enable - & set_masks); + rs6000_isa_flags &= ~set_masks; + rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable + & set_masks); if (rs6000_tune_index >= 0) tune_index = rs6000_tune_index; @@ -2485,37 +2543,25 @@ rs6000_option_override_internal (bool gl /* Pick defaults for SPE related control flags. Do this early to make sure that the TARGET_ macros are representative ASAP. */ - { - int spe_capable_cpu = - (rs6000_cpu == PROCESSOR_PPC8540 - || rs6000_cpu == PROCESSOR_PPC8548); - - if (!global_options_set.x_rs6000_spe_abi) - rs6000_spe_abi = spe_capable_cpu; - - if (!global_options_set.x_rs6000_spe) - rs6000_spe = spe_capable_cpu; - - if (!global_options_set.x_rs6000_float_gprs) - rs6000_float_gprs = - (rs6000_cpu == PROCESSOR_PPC8540 ? 1 - : rs6000_cpu == PROCESSOR_PPC8548 ? 2 - : 0); - } + if (rs6000_cpu == PROCESSOR_PPC8540 || rs6000_cpu == PROCESSOR_PPC8548) + { + if (!global_options_set.x_rs6000_spe_abi) + rs6000_spe_abi = 1; + + if ((rs6000_isa_flags_explicit & OPTION_MASK_SPE) == 0) + rs6000_isa_flags |= OPTION_MASK_SPE; + + if (!global_options_set.x_rs6000_float_gprs) + rs6000_float_gprs = (rs6000_cpu == PROCESSOR_PPC8540) ? 1 : 2; + } + else if (!global_options_set.x_rs6000_spe_abi) + rs6000_spe_abi = 0; - if (global_options_set.x_rs6000_spe_abi - && rs6000_spe_abi - && !TARGET_SPE_ABI) - error ("not configured for SPE ABI"); - - if (global_options_set.x_rs6000_spe - && rs6000_spe - && !TARGET_SPE) - error ("not configured for SPE instruction set"); if (main_target_opt != NULL && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi) - || (main_target_opt->x_rs6000_spe != rs6000_spe) + || (((main_target_opt->x_rs6000_isa_flags ^ rs6000_isa_flags) + & OPTION_MASK_SPE) != 0) || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs))) error ("target attribute or pragma changes SPE ABI"); @@ -2536,15 +2582,16 @@ rs6000_option_override_internal (bool gl /* Disable Cell microcode if we are optimizing for the Cell and not optimizing for size. */ - if (rs6000_gen_cell_microcode == -1) - rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL - && !optimize_size); + if ((rs6000_misc_flags_explicit & OPTION_MASK_GEN_CELL_MICROCODE) == 0 + && !(rs6000_cpu == PROCESSOR_CELL && !optimize_size)) + rs6000_misc_flags |= OPTION_MASK_GEN_CELL_MICROCODE; /* If we are optimizing big endian systems for space and it's OK to use instructions that would be microcoded on the Cell, use the load/store multiple and string instructions. */ - if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode) - target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); + if (BYTES_BIG_ENDIAN && optimize_size && TARGET_GEN_CELL_MICROCODE) + rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE + | OPTION_MASK_STRING); /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu is a 750, because the hardware doesn't support the @@ -2556,15 +2603,15 @@ rs6000_option_override_internal (bool gl { if (TARGET_MULTIPLE) { - target_flags &= ~MASK_MULTIPLE; - if ((target_flags_explicit & MASK_MULTIPLE) != 0) + rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE; + if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0) warning (0, "-mmultiple is not supported on little endian systems"); } if (TARGET_STRING) { - target_flags &= ~MASK_STRING; - if ((target_flags_explicit & MASK_STRING) != 0) + rs6000_isa_flags &= ~OPTION_MASK_STRING; + if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0) warning (0, "-mstring is not supported on little endian systems"); } } @@ -2576,10 +2623,10 @@ rs6000_option_override_internal (bool gl if (!TARGET_HARD_FLOAT || !TARGET_FPRS || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx requires hardware floating point"); else - target_flags &= ~ MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; } else if (TARGET_PAIRED_FLOAT) msg = N_("-mvsx and -mpaired are incompatible"); @@ -2588,11 +2635,12 @@ rs6000_option_override_internal (bool gl systems at this point. */ else if (!BYTES_BIG_ENDIAN) msg = N_("-mvsx used with little endian code"); - else if (TARGET_AVOID_XFORM > 0) + else if (TARGET_AVOID_XFORM) msg = N_("-mvsx needs indexed addressing"); - else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC)) + else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit + & OPTION_MASK_ALTIVEC)) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx and -mno-altivec are incompatible"); else msg = N_("-mno-altivec disables vsx"); @@ -2601,27 +2649,27 @@ rs6000_option_override_internal (bool gl if (msg) { warning (0, msg); - target_flags &= ~ MASK_VSX; - target_flags_explicit |= MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; + rs6000_isa_flags_explicit |= OPTION_MASK_VSX; } } /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-<option> to disable the code. */ if (TARGET_VSX) - target_flags |= (ISA_2_6_MASKS_SERVER & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit); else if (TARGET_POPCNTD) - target_flags |= (ISA_2_6_MASKS_EMBEDDED & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit); else if (TARGET_DFP) - target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~rs6000_isa_flags_explicit); else if (TARGET_CMPB) - target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit); else if (TARGET_FPRND) - target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_4_MASKS & ~rs6000_isa_flags_explicit); else if (TARGET_POPCNTB) - target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_2_MASKS & ~rs6000_isa_flags_explicit); else if (TARGET_ALTIVEC) - target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit); + rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit); /* E500mc does "better" if we inline more aggressively. Respect the user's opinion, though. */ @@ -2700,7 +2748,8 @@ rs6000_option_override_internal (bool gl unless the altivec ABI was set. This is set by default for 64-bit, but not for 32-bit. */ if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi) - target_flags &= ~((MASK_VSX | MASK_ALTIVEC) & ~target_flags_explicit); + rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC) + & ~rs6000_isa_flags_explicit); /* Enable Altivec ABI for AIX -maltivec. */ if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX)) @@ -2727,8 +2776,8 @@ rs6000_option_override_internal (bool gl } /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */ - if (!global_options_set.x_TARGET_ALTIVEC_VRSAVE) - TARGET_ALTIVEC_VRSAVE = rs6000_altivec_abi; + if ((rs6000_misc_flags_explicit & OPTION_MASK_ALTIVEC_VRSAVE) == 0) + rs6000_misc_flags |= OPTION_MASK_ALTIVEC_VRSAVE; } /* Set the Darwin64 ABI as default for 64-bit Darwin. @@ -2750,7 +2799,7 @@ rs6000_option_override_internal (bool gl /* Place FP constants in the constant pool instead of TOC if section anchors enabled. */ if (flag_section_anchors) - TARGET_NO_FP_IN_TOC = 1; + rs6000_misc_flags |= OPTION_MASK_NO_FP_IN_TOC; #ifdef SUBTARGET_OVERRIDE_OPTIONS SUBTARGET_OVERRIDE_OPTIONS; @@ -2782,14 +2831,14 @@ rs6000_option_override_internal (bool gl rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE; rs6000_double_float = TARGET_E500_DOUBLE; - target_flags &= ~MASK_STRING; + rs6000_isa_flags &= ~OPTION_MASK_STRING; break; default: - if (have_cpu && !(target_flags_explicit & MASK_ISEL)) - target_flags &= ~MASK_ISEL; + if (have_cpu && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL)) + rs6000_isa_flags &= ~OPTION_MASK_ISEL; break; } @@ -2807,38 +2856,14 @@ rs6000_option_override_internal (bool gl /* Detect invalid option combinations with E500. */ CHECK_E500_OPTIONS; - rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4 - && rs6000_cpu != PROCESSOR_POWER5 - && rs6000_cpu != PROCESSOR_POWER6 - && rs6000_cpu != PROCESSOR_POWER7 - && rs6000_cpu != PROCESSOR_PPCA2 - && rs6000_cpu != PROCESSOR_CELL - && rs6000_cpu != PROCESSOR_PPC476); - rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4 - || rs6000_cpu == PROCESSOR_POWER5 - || rs6000_cpu == PROCESSOR_POWER7); - rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4 - || rs6000_cpu == PROCESSOR_POWER5 - || rs6000_cpu == PROCESSOR_POWER6 - || rs6000_cpu == PROCESSOR_POWER7 - || rs6000_cpu == PROCESSOR_PPCE500MC - || rs6000_cpu == PROCESSOR_PPCE500MC64 - || rs6000_cpu == PROCESSOR_PPCE5500 - || rs6000_cpu == PROCESSOR_PPCE6500); - - /* Allow debug switches to override the above settings. These are set to -1 - in rs6000.opt to indicate the user hasn't directly set the switch. */ - if (TARGET_ALWAYS_HINT >= 0) - rs6000_always_hint = TARGET_ALWAYS_HINT; - - if (TARGET_SCHED_GROUPS >= 0) - rs6000_sched_groups = TARGET_SCHED_GROUPS; - - if (TARGET_ALIGN_BRANCH_TARGETS >= 0) - rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS; - - rs6000_sched_restricted_insns_priority - = (rs6000_sched_groups ? 1 : 0); + /* Allow the explicit debug switches to override the tuning settings. If no + explicit switch, fall back to the tuning options instead of the cpu + options. */ + rs6000_always_hint = (rs6000_operand_tuning_flag (OPTION_MASK_NO_HINT) == 0); + rs6000_sched_groups = rs6000_sched_restricted_insns_priority + = (rs6000_operand_tuning_flag (OPTION_MASK_SCHED_GROUPS) != 0); + rs6000_align_branch_targets + = (rs6000_operand_tuning_flag (OPTION_MASK_ALIGN_BRANCH_TARGETS) != 0); /* Handle -msched-costly-dep option. */ rs6000_sched_costly_dep @@ -3104,14 +3129,18 @@ rs6000_option_override_internal (bool gl rs6000_single_float = rs6000_double_float = 1; /* If not explicitly specified via option, decide whether to generate indexed - load/store instructions. */ - if (TARGET_AVOID_XFORM == -1) - /* Avoid indexed addressing when targeting Power6 in order to avoid the - DERAT mispredict penalty. However the LVE and STVE altivec instructions - need indexed accesses and the type used is the scalar type of the element - being loaded or stored. */ - TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB - && !TARGET_ALTIVEC); + load/store instructions. Avoid indexed addressing when targeting Power6 + in order to avoid the DERAT mispredict penalty. However the LVE and STVE + altivec instructions need indexed accesses and the type used is the scalar + type of the element being loaded or stored. */ + + if ((rs6000_isa_flags_explicit & OPTION_MASK_AVOID_XFORM) == 0) + { + if (TARGET_ALTIVEC) + rs6000_isa_flags &= ~OPTION_MASK_AVOID_XFORM; + else if (rs6000_cpu == PROCESSOR_POWER6) + rs6000_isa_flags |= OPTION_MASK_AVOID_XFORM; + } /* Set the -mrecip options. */ if (rs6000_recip_name) @@ -3161,16 +3190,15 @@ rs6000_option_override_internal (bool gl } /* Set the builtin mask of the various options used that could affect which - builtins were used. In the past we used target_flags, but we've run out - of bits, and some options like SPE and PAIRED are no longer in - target_flags. */ - rs6000_builtin_mask = rs6000_builtin_mask_calculate (); + builtins were used. */ + rs6000_builtin_mask = (rs6000_isa_flags & RS6000_BTM_COMMON); if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) - fprintf (stderr, "new builtin mask = 0x%x%s%s%s%s\n", rs6000_builtin_mask, - (rs6000_builtin_mask & RS6000_BTM_ALTIVEC) ? ", altivec" : "", - (rs6000_builtin_mask & RS6000_BTM_VSX) ? ", vsx" : "", - (rs6000_builtin_mask & RS6000_BTM_PAIRED) ? ", paired" : "", - (rs6000_builtin_mask & RS6000_BTM_SPE) ? ", spe" : ""); + { + fprintf (stderr, + "new builtin mask = " HOST_WIDE_INT_PRINT_HEX ", ", + rs6000_builtin_mask); + rs6000_print_isa_options (stderr, rs6000_builtin_mask); + } /* Initialize all of the registers. */ rs6000_init_hard_regno_mode_ok (global_init_p); @@ -7440,7 +7468,7 @@ init_cumulative_args (CUMULATIVE_ARGS *c cum->nargs_prototype = n_named_args; /* Check for a longcall attribute. */ - if ((!fntype && rs6000_default_long_calls) + if ((!fntype && TARGET_LONG_CALLS) || (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))) @@ -10407,7 +10435,7 @@ altivec_expand_dst_builtin (tree exp, rt bool *expandedp) { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl); tree arg0, arg1, arg2; enum machine_mode mode0, mode1; rtx pat, op0, op1, op2; @@ -10809,7 +10837,7 @@ static rtx paired_expand_builtin (tree exp, rtx target, bool * expandedp) { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl); const struct builtin_description *d; size_t i; @@ -10840,28 +10868,28 @@ paired_expand_builtin (tree exp, rtx tar automagically by rs6000_expand_binop_builtin. */ static const struct builtin_description bdesc_2arg_spe[] = { - { RS6000_BTM_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, - { RS6000_BTM_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, - { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } + { OPTION_MASK_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, + { OPTION_MASK_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, + { OPTION_MASK_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, + { OPTION_MASK_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, + { OPTION_MASK_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } }; /* Expand the builtin in EXP and store the result in TARGET. Store @@ -10874,7 +10902,7 @@ spe_expand_builtin (tree exp, rtx target { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); tree arg1, arg0; - unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl); enum insn_code icode; enum machine_mode tmode, mode0; rtx pat, op0; @@ -11239,19 +11267,23 @@ rs6000_invalid_builtin (enum rs6000_buil { size_t uns_fncode = (size_t)fncode; const char *name = rs6000_builtin_info[uns_fncode].name; - unsigned fnmask = rs6000_builtin_info[uns_fncode].mask; + HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask; gcc_assert (name != NULL); - if ((fnmask & RS6000_BTM_CELL) != 0) + if ((fnmask & OPTION_MASK_CELL_BUILTIN) != 0) error ("Builtin function %s is only valid for the cell processor", name); - else if ((fnmask & RS6000_BTM_VSX) != 0) + else if ((fnmask & OPTION_MASK_VSX) != 0) error ("Builtin function %s requires the -mvsx option", name); - else if ((fnmask & RS6000_BTM_ALTIVEC) != 0) + else if ((fnmask & OPTION_MASK_ALTIVEC) != 0) error ("Builtin function %s requires the -maltivec option", name); - else if ((fnmask & RS6000_BTM_PAIRED) != 0) + else if ((fnmask & OPTION_MASK_PAIRED_FLOAT) != 0) error ("Builtin function %s requires the -mpaired option", name); - else if ((fnmask & RS6000_BTM_SPE) != 0) + else if ((fnmask & OPTION_MASK_SPE) != 0) error ("Builtin function %s requires the -mspe option", name); + else if ((fnmask & OPTION_MASK_POPCNTB) != 0) + error ("Builtin function %s requires the -mpopcntb option", name); + else if ((fnmask & OPTION_MASK_PPC_GFXOPT) != 0) + error ("Builtin function %s requires the -mpowerpc-gfxopt option", name); else error ("Builtin function %s is not supported with the current options", name); @@ -11276,7 +11308,7 @@ rs6000_expand_builtin (tree exp, rtx tar size_t i; rtx ret; bool success; - unsigned mask = rs6000_builtin_info[uns_fcode].mask; + HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask; bool func_valid_p = ((rs6000_builtin_mask & mask) == mask); if (TARGET_DEBUG_BUILTIN) @@ -11637,7 +11669,7 @@ rs6000_init_builtins (void) static tree rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) { - unsigned fnmask; + HOST_WIDE_INT fnmask; if (code >= RS6000_BUILTIN_COUNT) return error_mark_node; @@ -12509,7 +12541,7 @@ rs6000_common_init_builtins (void) tree v2si_ftype_qi = NULL_TREE; tree v2si_ftype_v2si_qi = NULL_TREE; tree v2si_ftype_int_qi = NULL_TREE; - unsigned builtin_mask = rs6000_builtin_mask; + HOST_WIDE_INT builtin_mask = rs6000_builtin_mask; if (!TARGET_PAIRED_FLOAT) { @@ -12531,7 +12563,7 @@ rs6000_common_init_builtins (void) for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) { tree type; - unsigned mask = d->mask; + HOST_WIDE_INT mask = d->mask; if ((mask & builtin_mask) != mask) { @@ -12572,7 +12604,7 @@ rs6000_common_init_builtins (void) { enum machine_mode mode0, mode1, mode2; tree type; - unsigned mask = d->mask; + HOST_WIDE_INT mask = d->mask; if ((mask & builtin_mask) != mask) { @@ -12635,7 +12667,7 @@ rs6000_common_init_builtins (void) { enum machine_mode mode0, mode1; tree type; - unsigned mask = d->mask; + HOST_WIDE_INT mask = d->mask; if ((mask & builtin_mask) != mask) { @@ -24474,7 +24506,7 @@ rs6000_handle_altivec_attribute (tree *n if (TARGET_64BIT) error ("use of %<long%> in AltiVec types is invalid for " "64-bit code without -mvsx"); - else if (rs6000_warn_altivec_long) + else if (TARGET_WARN_ALTIVEC_LONG) warning (0, "use of %<long%> in AltiVec types is deprecated; " "use %<int%>"); } @@ -24598,12 +24630,12 @@ rs6000_handle_longcall_attribute (tree * return NULL_TREE; } -/* Set longcall attributes on all functions declared when - rs6000_default_long_calls is true. */ +/* Set longcall attributes on all functions declared when TARGET_LONG_CALLS is + true. */ static void rs6000_set_default_type_attributes (tree type) { - if (rs6000_default_long_calls + if (TARGET_LONG_CALLS && (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)) TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), @@ -25208,14 +25240,15 @@ rs6000_darwin_file_start (void) { const char *arg; const char *name; - int if_set; + HOST_WIDE_INT if_set; } mapping[] = { - { "ppc64", "ppc64", MASK_64BIT }, - { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, + { "ppc64", "ppc64", OPTION_MASK_64BIT }, + { "970", "ppc970", (OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF + | OPTION_MASK_POWERPC64) }, { "power4", "ppc970", 0 }, { "G5", "ppc970", 0 }, { "7450", "ppc7450", 0 }, - { "7400", "ppc7400", MASK_ALTIVEC }, + { "7400", "ppc7400", OPTION_MASK_ALTIVEC }, { "G4", "ppc7400", 0 }, { "750", "ppc750", 0 }, { "740", "ppc750", 0 }, @@ -25247,7 +25280,7 @@ rs6000_darwin_file_start (void) i = 0; while (mapping[i].arg != NULL && strcmp (mapping[i].arg, cpu_id) != 0 - && (mapping[i].if_set & target_flags) == 0) + && (mapping[i].if_set & rs6000_isa_flags) == 0) i++; fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name); @@ -27310,7 +27343,7 @@ void rs6000_final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED, int num_operands ATTRIBUTE_UNUSED) { - if (rs6000_warn_cell_microcode) + if (TARGET_WARN_CELL_MICROCODE) { const char *temp; int insn_code_number = recog_memoized (insn); @@ -27341,95 +27374,103 @@ rs6000_final_prescan_insn (rtx insn, rtx struct rs6000_opt_mask { const char *name; /* option name */ - int mask; /* mask to set */ + HOST_WIDE_INT mask; /* mask to set */ bool invert; /* invert sense of mask */ bool valid_target; /* option is a target option */ }; static struct rs6000_opt_mask const rs6000_opt_masks[] = { - { "altivec", MASK_ALTIVEC, false, true }, - { "cmpb", MASK_CMPB, false, true }, - { "dlmzb", MASK_DLMZB, false, true }, - { "fprnd", MASK_FPRND, false, true }, - { "hard-dfp", MASK_DFP, false, true }, - { "isel", MASK_ISEL, false, true }, - { "mfcrf", MASK_MFCRF, false, true }, - { "mfpgpr", MASK_MFPGPR, false, true }, - { "mulhw", MASK_MULHW, false, true }, - { "multiple", MASK_MULTIPLE, false, true }, - { "update", MASK_NO_UPDATE, true , true }, - { "popcntb", MASK_POPCNTB, false, true }, - { "popcntd", MASK_POPCNTD, false, true }, - { "powerpc-gfxopt", MASK_PPC_GFXOPT, false, true }, - { "powerpc-gpopt", MASK_PPC_GPOPT, false, true }, - { "recip-precision", MASK_RECIP_PRECISION, false, true }, - { "string", MASK_STRING, false, true }, - { "vsx", MASK_VSX, false, true }, -#ifdef MASK_64BIT + { "altivec", OPTION_MASK_ALTIVEC, false, true }, + { "avoid-indexed-addresses", OPTION_MASK_AVOID_XFORM, false, true }, + { "cmpb", OPTION_MASK_CMPB, false, true }, + { "dlmzb", OPTION_MASK_DLMZB, false, true }, + { "fprnd", OPTION_MASK_FPRND, false, true }, + { "friz", OPTION_MASK_NO_FRIZ, true, true }, + { "hard-dfp", OPTION_MASK_DFP, false, true }, + { "isel", OPTION_MASK_ISEL, false, true }, + { "longcall", OPTION_MASK_LONG_CALLS, false, true }, + { "mfcrf", OPTION_MASK_MFCRF, false, true }, + { "mfpgpr", OPTION_MASK_MFPGPR, false, true }, + { "mulhw", OPTION_MASK_MULHW, false, true }, + { "multiple", OPTION_MASK_MULTIPLE, false, true }, + { "update", OPTION_MASK_NO_UPDATE, true , true }, + { "popcntb", OPTION_MASK_POPCNTB, false, true }, + { "popcntd", OPTION_MASK_POPCNTD, false, true }, + { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true }, + { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true }, + { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true }, + { "string", OPTION_MASK_STRING, false, true }, + { "vsx", OPTION_MASK_VSX, false, true }, +#ifdef OPTION_MASK_64BIT #if TARGET_AIX_OS - { "aix64", MASK_64BIT, false, false }, - { "aix32", MASK_64BIT, true, false }, + { "aix64", OPTION_MASK_64BIT, false, false }, + { "aix32", OPTION_MASK_64BIT, true, false }, #else - { "64", MASK_64BIT, false, false }, - { "32", MASK_64BIT, true, false }, + { "64", OPTION_MASK_64BIT, false, false }, + { "32", OPTION_MASK_64BIT, true, false }, #endif #endif -#ifdef MASK_EABI - { "eabi", MASK_EABI, false, false }, +#ifdef OPTION_MASK_EABI + { "eabi", OPTION_MASK_EABI, false, false }, #endif -#ifdef MASK_LITTLE_ENDIAN - { "little", MASK_LITTLE_ENDIAN, false, false }, - { "big", MASK_LITTLE_ENDIAN, true, false }, -#endif -#ifdef MASK_RELOCATABLE - { "relocatable", MASK_RELOCATABLE, false, false }, -#endif -#ifdef MASK_STRICT_ALIGN - { "strict-align", MASK_STRICT_ALIGN, false, false }, -#endif - { "soft-float", MASK_SOFT_FLOAT, false, false }, - { "string", MASK_STRING, false, false }, +#ifdef OPTION_MASK_LITTLE_ENDIAN + { "little", OPTION_MASK_LITTLE_ENDIAN, false, false }, + { "big", OPTION_MASK_LITTLE_ENDIAN, true, false }, +#endif +#ifdef OPTION_MASK_RELOCATABLE + { "relocatable", OPTION_MASK_RELOCATABLE, false, false }, +#endif +#ifdef OPTION_MASK_STRICT_ALIGN + { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false }, +#endif + { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false }, + { "string", OPTION_MASK_STRING, false, false }, + { "spe", OPTION_MASK_SPE, false, false }, + { "paired", OPTION_MASK_PAIRED_FLOAT, false, false }, + { "sched-groups", OPTION_MASK_SCHED_GROUPS, false, true }, + { "always-hint", OPTION_MASK_NO_HINT, true, true }, + { "align-branch", OPTION_MASK_ALIGN_BRANCH_TARGETS,false, true }, }; -/* Builtin mask mapping for printing the flags. */ -static struct rs6000_opt_mask const rs6000_builtin_mask_names[] = +static struct rs6000_opt_mask const rs6000_misc_masks[] = { - { "altivec", RS6000_BTM_ALTIVEC, false, false }, - { "vsx", RS6000_BTM_VSX, false, false }, - { "spe", RS6000_BTM_SPE, false, false }, - { "paired", RS6000_BTM_PAIRED, false, false }, - { "fre", RS6000_BTM_FRE, false, false }, - { "fres", RS6000_BTM_FRES, false, false }, - { "frsqrte", RS6000_BTM_FRSQRTE, false, false }, - { "frsqrtes", RS6000_BTM_FRSQRTES, false, false }, - { "popcntd", RS6000_BTM_POPCNTD, false, false }, - { "cell", RS6000_BTM_CELL, false, false }, -}; - -/* Option variables that we want to support inside attribute((target)) and - #pragma GCC target operations. */ - -struct rs6000_opt_var { - const char *name; /* option name */ - size_t global_offset; /* offset of the option in global_options. */ - size_t target_offset; /* offset of the option in target optiosn. */ -}; - -static struct rs6000_opt_var const rs6000_opt_vars[] = -{ - { "friz", - offsetof (struct gcc_options, x_TARGET_FRIZ), - offsetof (struct cl_target_option, x_TARGET_FRIZ), }, - { "avoid-indexed-addresses", - offsetof (struct gcc_options, x_TARGET_AVOID_XFORM), - offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) }, - { "paired", - offsetof (struct gcc_options, x_rs6000_paired_float), - offsetof (struct cl_target_option, x_rs6000_paired_float), }, - { "longcall", - offsetof (struct gcc_options, x_rs6000_default_long_calls), - offsetof (struct cl_target_option, x_rs6000_default_long_calls), }, + { "allow-movmisalign", OPTION_MASK_ALLOW_MOVMISALIGN, false, false }, + { "pointers-to-nested-functions", + OPTION_MASK_POINTERS_TO_NESTED_FUNCTIONS, + false, false }, + { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, false }, + { "sched-prolog", OPTION_MASK_SCHED_PROLOG, false, false }, + { "single-pic-base", OPTION_MASK_SINGLE_PIC_BASE, false, false }, + { "tls-markers", OPTION_MASK_TLS_MARKERS, false, false }, + { "vectorize-builtins", OPTION_MASK_VECTORIZE_BUILTINS, false, false }, + { "vrsave", OPTION_MASK_ALTIVEC_VRSAVE, false, false }, + { "vsx-align128", OPTION_MASK_VSX_ALIGN_128, false, false }, + { "vsx-scalar-double", OPTION_MASK_VSX_SCALAR_DOUBLE, false, false }, + { "vsx-scalar-memory", OPTION_MASK_VSX_SCALAR_MEMORY, false, false }, + { "fp-in-toc", OPTION_MASK_NO_FP_IN_TOC, true, false }, + { "sum-in-toc", OPTION_MASK_NO_SUM_IN_TOC, true, false }, + { "gen-cell-microcode", OPTION_MASK_GEN_CELL_MICROCODE, false, false }, + { "warn-cell-microcode", OPTION_MASK_WARN_CELL_MICROCODE,false, false }, + { "warn-altivec-long", OPTION_MASK_WARN_ALTIVEC_LONG, false, false }, +#ifdef OPTION_MASK_NO_BITFIELD_TYPE + { "bitfield-type", OPTION_MASK_NO_BITFIELD_TYPE, true, false }, +#endif +#ifdef OPTION_MASK_NO_BITFIELD_WORD + { "bitfield-word", OPTION_MASK_NO_BITFIELD_WORD, true, false }, +#endif +#ifdef OPTION_MASK_SECURE_PLT + { "secure-plt", OPTION_MASK_SECURE_PLT, false, false }, +#endif +#ifdef OPTION_MASK_REGNAMES + { "regnames", OPTION_MASK_REGNAMES, false, false }, +#endif +#ifdef OPTION_MASK_XL_COMPAT + { "xl-compat", OPTION_MASK_XL_COMPAT, false, false }, +#endif +#ifdef OPTION_MASK_NO_LINK_STACK + { "preserve-link-stack", OPTION_MASK_NO_LINK_STACK, true, false }, +#endif }; /* Inner function to handle attribute((target("..."))) and #pragma GCC target @@ -27493,42 +27534,30 @@ rs6000_inner_target_options (tree args, for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++) if (strcmp (r, rs6000_opt_masks[i].name) == 0) { - int mask = rs6000_opt_masks[i].mask; + HOST_WIDE_INT mask = rs6000_opt_masks[i].mask; if (!rs6000_opt_masks[i].valid_target) not_valid_p = true; else { error_p = false; - target_flags_explicit |= mask; + rs6000_isa_flags_explicit |= mask; /* VSX needs altivec, so -mvsx automagically sets altivec. */ - if (mask == MASK_VSX && !invert) - mask |= MASK_ALTIVEC; + if (mask == OPTION_MASK_VSX && !invert) + mask |= OPTION_MASK_ALTIVEC; if (rs6000_opt_masks[i].invert) invert = !invert; if (invert) - target_flags &= ~mask; + rs6000_isa_flags &= ~mask; else - target_flags |= mask; + rs6000_isa_flags |= mask; } break; } - - if (error_p && !not_valid_p) - { - for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++) - if (strcmp (r, rs6000_opt_vars[i].name) == 0) - { - size_t j = rs6000_opt_vars[i].global_offset; - *((int *) ((char *)&global_options + j)) = !invert; - error_p = false; - break; - } - } } if (error_p) @@ -27717,8 +27746,7 @@ rs6000_pragma_target_parse (tree args, t tree prev_tree = build_target_option_node (); tree cur_tree; struct cl_target_option *prev_opt, *cur_opt; - unsigned prev_bumask, cur_bumask, diff_bumask; - int prev_flags, cur_flags, diff_flags; + HOST_WIDE_INT prev_flags, cur_flags, diff_flags; if (TARGET_DEBUG_TARGET) { @@ -27767,27 +27795,20 @@ rs6000_pragma_target_parse (tree args, t if (rs6000_target_modify_macros_ptr) { prev_opt = TREE_TARGET_OPTION (prev_tree); - prev_bumask = prev_opt->x_rs6000_builtin_mask; - prev_flags = prev_opt->x_target_flags; + prev_flags = prev_opt->x_rs6000_isa_flags; cur_opt = TREE_TARGET_OPTION (cur_tree); - cur_flags = cur_opt->x_target_flags; - cur_bumask = cur_opt->x_rs6000_builtin_mask; + cur_flags = cur_opt->x_rs6000_isa_flags; - diff_bumask = (prev_bumask ^ cur_bumask); - diff_flags = (prev_flags ^ cur_flags); + diff_flags = (prev_flags ^ cur_flags); - if ((diff_flags != 0) || (diff_bumask != 0)) + if (diff_flags != 0) { /* Delete old macros. */ - rs6000_target_modify_macros_ptr (false, - prev_flags & diff_flags, - prev_bumask & diff_bumask); + rs6000_target_modify_macros_ptr (false, prev_flags & diff_flags); /* Define new macros. */ - rs6000_target_modify_macros_ptr (true, - cur_flags & diff_flags, - cur_bumask & diff_bumask); + rs6000_target_modify_macros_ptr (true, cur_flags & diff_flags); } } @@ -27878,7 +27899,12 @@ rs6000_set_current_function (tree fndecl static void rs6000_function_specific_save (struct cl_target_option *ptr) { - ptr->rs6000_target_flags_explicit = target_flags_explicit; + ptr->x_rs6000_isa_flags = rs6000_isa_flags; + ptr->x_rs6000_isa_flags_explicit = rs6000_isa_flags_explicit; + ptr->x_rs6000_misc_flags = rs6000_misc_flags; + ptr->x_rs6000_misc_flags_explicit = rs6000_misc_flags_explicit; + ptr->x_rs6000_debug_flags = rs6000_debug_flags; + ptr->x_rs6000_debug_flags_explicit = rs6000_debug_flags_explicit; } /* Restore the current options */ @@ -27886,47 +27912,75 @@ rs6000_function_specific_save (struct cl static void rs6000_function_specific_restore (struct cl_target_option *ptr) { - target_flags_explicit = ptr->rs6000_target_flags_explicit; + rs6000_isa_flags = ptr->x_rs6000_isa_flags; + rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit; + rs6000_misc_flags = ptr->x_rs6000_misc_flags; + rs6000_misc_flags_explicit = ptr->x_rs6000_misc_flags_explicit; + rs6000_debug_flags = ptr->x_rs6000_debug_flags; + rs6000_debug_flags_explicit = ptr->x_rs6000_debug_flags_explicit; (void) rs6000_option_override_internal (false); } -/* Print the current options */ +/* Helper function to print the current isa or misc options on a line. */ static void -rs6000_function_specific_print (FILE *file, int indent, - struct cl_target_option *ptr) +rs6000_print_isa_or_misc_options (FILE *file, + HOST_WIDE_INT flags, + const struct rs6000_opt_mask *opts, + size_t num_elements) { size_t i; - int flags = ptr->x_target_flags; - unsigned bu_mask = ptr->x_rs6000_builtin_mask; + const char *comma = ""; + const char *suffix = "<none>\n"; /* Print the various mask options. */ - for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++) - if ((flags & rs6000_opt_masks[i].mask) != 0) + for (i = 0; i < num_elements; i++) + if ((flags & opts[i].mask) != 0) { - flags &= ~ rs6000_opt_masks[i].mask; - fprintf (file, "%*s-m%s%s\n", indent, "", + flags &= ~ opts[i].mask; + fprintf (file, "%s-m%s%s", comma, rs6000_opt_masks[i].invert ? "no-" : "", rs6000_opt_masks[i].name); + comma = ", "; + suffix = "\n"; } - /* Print the various options that are variables. */ - for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++) - { - size_t j = rs6000_opt_vars[i].target_offset; - if (((signed char *) ptr)[j]) - fprintf (file, "%*s-m%s\n", indent, "", - rs6000_opt_vars[i].name); - } + fputs (suffix, file); +} - /* Print the various builtin flags. */ - fprintf (file, "%*sbuiltin mask = 0x%x\n", indent, "", bu_mask); - for (i = 0; i < ARRAY_SIZE (rs6000_builtin_mask_names); i++) - if ((bu_mask & rs6000_builtin_mask_names[i].mask) != 0) - { - fprintf (file, "%*s%s builtins supported\n", indent, "", - rs6000_builtin_mask_names[i].name); - } +/* Helper function to print the current isa options on a line. */ + +static void +rs6000_print_isa_options (FILE *file, HOST_WIDE_INT flags) +{ + rs6000_print_isa_or_misc_options (file, flags, &rs6000_opt_masks[0], + ARRAY_SIZE (rs6000_opt_masks)); +} + +/* Helper function to print the current miscellaneous options on a line. */ + +static void +rs6000_print_misc_options (FILE *file, HOST_WIDE_INT flags) +{ + rs6000_print_isa_or_misc_options (file, flags, &rs6000_misc_masks[0], + ARRAY_SIZE (rs6000_misc_masks)); +} + +/* Print the current options */ + +static void +rs6000_function_specific_print (FILE *file, int indent, + struct cl_target_option *ptr) +{ + fprintf (file, + "%*sOptions (" HOST_WIDE_INT_PRINT_HEX "): ", + indent, "", ptr->x_rs6000_isa_flags); + rs6000_print_isa_options (file, ptr->x_rs6000_isa_flags); + + fprintf (file, + "%*sExplict (" HOST_WIDE_INT_PRINT_HEX "): ", + indent, "", ptr->x_rs6000_isa_flags_explicit); + rs6000_print_isa_options (file, ptr->x_rs6000_isa_flags_explicit); } \f @@ -27956,8 +28010,8 @@ rs6000_can_inline_p (tree caller, tree c /* Callee's options should a subset of the caller's, i.e. a vsx function can inline an altivec function but a non-vsx function can't inline a vsx function. */ - if ((caller_opts->x_target_flags & callee_opts->x_target_flags) - == callee_opts->x_target_flags) + if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags) + == callee_opts->x_rs6000_isa_flags) ret = true; } Index: gcc/config/rs6000/aix52.h =================================================================== --- gcc/config/rs6000/aix52.h (revision 191266) +++ gcc/config/rs6000/aix52.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/750cl.h =================================================================== --- gcc/config/rs6000/750cl.h (revision 191266) +++ gcc/config/rs6000/750cl.h (working copy) @@ -23,7 +23,9 @@ <http://www.gnu.org/licenses/>. */ #undef TARGET_PAIRED_FLOAT -#define TARGET_PAIRED_FLOAT rs6000_paired_float +#define TARGET_PAIRED_FLOAT OPTION_PAIRED_FLOAT + +#define TARGET_USES_PAIRED_FLOAT 1 #undef ASM_CPU_SPEC #define ASM_CPU_SPEC "-m750cl" Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 191266) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -218,55 +218,55 @@ extern const char *host_detect_local_cpu optional field operand for mfcr. */ #ifndef HAVE_AS_MFCRF -#undef TARGET_MFCRF -#define TARGET_MFCRF 0 +#undef OPTION_MFCRF +#define OPTION_MFCRF 0 #endif /* Define TARGET_POPCNTB if the target assembler does not support the popcount byte instruction. */ #ifndef HAVE_AS_POPCNTB -#undef TARGET_POPCNTB -#define TARGET_POPCNTB 0 +#undef OPTION_POPCNTB +#define OPTION_POPCNTB 0 #endif /* Define TARGET_FPRND if the target assembler does not support the fp rounding instructions. */ #ifndef HAVE_AS_FPRND -#undef TARGET_FPRND -#define TARGET_FPRND 0 +#undef OPTION_FPRND +#define OPTION_FPRND 0 #endif /* Define TARGET_CMPB if the target assembler does not support the cmpb instruction. */ #ifndef HAVE_AS_CMPB -#undef TARGET_CMPB -#define TARGET_CMPB 0 +#undef OPTION_CMPB +#define OPTION_CMPB 0 #endif /* Define TARGET_MFPGPR if the target assembler does not support the mffpr and mftgpr instructions. */ #ifndef HAVE_AS_MFPGPR -#undef TARGET_MFPGPR -#define TARGET_MFPGPR 0 +#undef OPTION_MFPGPR +#define OPTION_MFPGPR 0 #endif /* Define TARGET_DFP if the target assembler does not support decimal floating point instructions. */ #ifndef HAVE_AS_DFP -#undef TARGET_DFP -#define TARGET_DFP 0 +#undef OPTION_DFP +#define OPTION_DFP 0 #endif /* Define TARGET_POPCNTD if the target assembler does not support the popcount word and double word instructions. */ #ifndef HAVE_AS_POPCNTD -#undef TARGET_POPCNTD -#define TARGET_POPCNTD 0 +#undef OPTION_POPCNTD +#define OPTION_POPCNTD 0 #endif /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If @@ -283,11 +283,13 @@ extern const char *host_detect_local_cpu #undef TARGET_TLS_MARKERS #define TARGET_TLS_MARKERS 0 #else -#define TARGET_TLS_MARKERS tls_markers +#define TARGET_TLS_MARKERS OPTION_TLS_MARKERS #endif -#ifndef TARGET_SECURE_PLT +#ifndef OPTION_SECURE_PLT #define TARGET_SECURE_PLT 0 +#else +#define TARGET_SECURE_PLT OPTION_SECURE_PLT #endif #ifndef TARGET_CMODEL @@ -325,7 +327,7 @@ extern const char *host_detect_local_cpu /* The option machinery will define this. */ #endif -#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING) +#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE | OPTION_MASK_STRING) /* FPU operations supported. Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must @@ -348,30 +350,6 @@ extern const char *host_detect_local_cpu #define PROCESSOR_DEFAULT PROCESSOR_PPC603 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A -/* Debug support */ -#define MASK_DEBUG_STACK 0x01 /* debug stack applications */ -#define MASK_DEBUG_ARG 0x02 /* debug argument handling */ -#define MASK_DEBUG_REG 0x04 /* debug register handling */ -#define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ -#define MASK_DEBUG_COST 0x10 /* debug rtx codes */ -#define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ -#define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ -#define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ - | MASK_DEBUG_ARG \ - | MASK_DEBUG_REG \ - | MASK_DEBUG_ADDR \ - | MASK_DEBUG_COST \ - | MASK_DEBUG_TARGET \ - | MASK_DEBUG_BUILTIN) - -#define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) -#define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) -#define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) -#define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) -#define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) -#define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) -#define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) - extern enum rs6000_vector rs6000_vector_unit[]; #define VECTOR_UNIT_NONE_P(MODE) \ @@ -465,21 +443,136 @@ extern int rs6000_vector_align[]; #define TARGET_FCTIDUZ TARGET_POPCNTD #define TARGET_FCTIWUZ TARGET_POPCNTD +/* Map OPTION_<xxx> back into TARGET_<xxx> options in rs6000_isa_flags. */ +#define TARGET_64BIT OPTION_64BIT +#define TARGET_ALIGN_BRANCH_TARGETS OPTION_ALIGN_BRANCH_TARGETS +#define TARGET_ALTIVEC OPTION_ALTIVEC +#define TARGET_ALWAYS_HINT OPTION_ALWAYS_HINT +#define TARGET_AVOID_XFORM OPTION_AVOID_XFORM +#define TARGET_CELL_BUILTIN OPTION_CELL_BUILTIN +#define TARGET_CMPB OPTION_CMPB +#define TARGET_DFP OPTION_DFP +#define TARGET_DLMZB OPTION_DLMZB +#define TARGET_EABI OPTION_EABI +#define TARGET_FPRND OPTION_FPRND +#define TARGET_FRIZ OPTION_FRIZ +#define TARGET_GEN_CELL_MICROCODE OPTION_GEN_CELL_MICROCODE +#define TARGET_HARD_FLOAT OPTION_HARD_FLOAT +#define TARGET_ISEL OPTION_ISEL +#define TARGET_LITTLE_ENDIAN OPTION_LITTLE_ENDIAN +#define TARGET_LONG_CALLS OPTION_LONG_CALLS +#define TARGET_MFCRF OPTION_MFCRF +#define TARGET_MFPGPR OPTION_MFPGPR +#define TARGET_MULHW OPTION_MULHW +#define TARGET_MULTIPLE OPTION_MULTIPLE +#define TARGET_NO_FP_IN_TOC OPTION_NO_FP_IN_TOC +#define TARGET_NO_FRIZ OPTION_NO_FRIZ +#define TARGET_NO_HINT OPTION_NO_HINT +#define TARGET_NO_SUM_IN_TOC OPTION_NO_SUM_IN_TOC +#define TARGET_NO_UPDATE OPTION_NO_UPDATE +#define TARGET_POPCNTB OPTION_POPCNTB +#define TARGET_POPCNTD OPTION_POPCNTD +#define TARGET_PPC_GFXOPT OPTION_PPC_GFXOPT +#define TARGET_PPC_GPOPT OPTION_PPC_GPOPT +#define TARGET_RECIP_PRECISION OPTION_RECIP_PRECISION +#define TARGET_SCHED_GROUPS OPTION_SCHED_GROUPS +#define TARGET_SOFT_FLOAT OPTION_SOFT_FLOAT +#define TARGET_STRICT_ALIGN OPTION_STRICT_ALIGN +#define TARGET_STRING OPTION_STRING +#define TARGET_UPDATE OPTION_UPDATE +#define TARGET_VSX OPTION_VSX +#define TARGET_WARN_ALTIVEC_LONG OPTION_WARN_ALTIVEC_LONG +#define TARGET_WARN_CELL_MICROCODE OPTION_WARN_CELL_MICROCODE + +#ifndef IN_LIBGCC2 +#define TARGET_POWERPC64 OPTION_POWERPC64 +#endif + +#ifdef OPTION_RELOCATABLE +#define TARGET_RELOCATABLE OPTION_RELOCATABLE +#endif + +#ifdef OPTION_MINIMAL_TOC +#define TARGET_MINIMAL_TOC OPTION_MINIMAL_TOC +#endif + +#ifdef OPTION_REGNAMES +#define TARGET_REGNAMES OPTION_REGNAMES +#endif + +#ifdef OPTION_PROTOTYPE +#define TARGET_PROTOTYPE OPTION_PROTOTYPE +#endif + +/* Map OPTION_<xxx> back into TARGET_<xxx> options in rs6000_misc_flags. */ +#define TARGET_ALLOW_MOVMISALIGN OPTION_ALLOW_MOVMISALIGN +#define TARGET_ALTIVEC_VRSAVE OPTION_ALTIVEC_VRSAVE +#define TARGET_NO_BITFIELD_TYPE OPTION_NO_BITFIELD_TYPE +#define TARGET_NO_BITFIELD_WORD OPTION_NO_BITFIELD_WORD +#define TARGET_POINTERS_TO_NESTED_FUNCTIONS OPTION_POINTERS_TO_NESTED_FUNCTIONS +#define TARGET_SAVE_TOC_INDIRECT OPTION_SAVE_TOC_INDIRECT +#define TARGET_SINGLE_PIC_BASE OPTION_SINGLE_PIC_BASE +#define TARGET_SCHED_PROLOG OPTION_SCHED_PROLOG +#define TARGET_VECTORIZE_BUILTINS OPTION_VECTORIZE_BUILTINS +#define TARGET_VSX_ALIGN_128 OPTION_VSX_ALIGN_128 +#define TARGET_VSX_SCALAR_DOUBLE OPTION_VSX_SCALAR_DOUBLE +#define TARGET_VSX_SCALAR_MEMORY OPTION_VSX_SCALAR_MEMORY +#define TARGET_XL_COMPAT OPTION_XL_COMPAT + +/* Map OPTION_<xxx> back into TARGET_<xxx> options in rs6000_debug_flags. */ +#define TARGET_DEBUG_ALL OPTION_DEBUG_ALL +#define TARGET_DEBUG_ARG OPTION_DEBUG_ARG +#define TARGET_DEBUG_STACK OPTION_DEBUG_STACK +#define TARGET_DEBUG_ADDR OPTION_DEBUG_ADDR +#define TARGET_DEBUG_BUILTIN OPTION_DEBUG_BUILTIN +#define TARGET_DEBUG_COST OPTION_DEBUG_COST +#define TARGET_DEBUG_REG OPTION_DEBUG_REG +#define TARGET_DEBUG_TARGET OPTION_DEBUG_TARGET + +/* Debug masks. */ +#define ALL_DEBUG_MASKS (OPTION_MASK_DEBUG_ADDR \ + | OPTION_MASK_DEBUG_ARG \ + | OPTION_MASK_DEBUG_BUILTIN \ + | OPTION_MASK_DEBUG_COST \ + | OPTION_MASK_DEBUG_REG \ + | OPTION_MASK_DEBUG_STACK \ + | OPTION_MASK_DEBUG_TARGET) + +/* Explicit ISA options that were set. */ +#define rs6000_isa_flags_explicit global_options_set.x_rs6000_isa_flags +#define rs6000_misc_flags_explicit global_options_set.x_rs6000_misc_flags +#define rs6000_debug_flags_explicit global_options_set.x_rs6000_debug_flags + +#ifndef OPTION_MASK_DEFAULT_SECURE_PLT +#define OPTION_MASK_DEFAULT_SECURE_PLT 0 +#endif + +/* Miscellaneous/debug flag bits to set. */ +#define TARGET_MISC_DEFAULT (OPTION_MASK_VECTORIZE_BUILTINS \ + | OPTION_MASK_VSX_SCALAR_DOUBLE \ + | OPTION_MASK_ALLOW_MOVMISALIGN \ + | OPTION_MASK_SCHED_PROLOG \ + | OPTION_MASK_TLS_MARKERS \ + | OPTION_MASK_POINTERS_TO_NESTED_FUNCTIONS \ + | OPTION_MASK_DEFAULT_SECURE_PLT \ + | OPTION_MASK_WARN_ALTIVEC_LONG) + +#define TARGET_DEBUG_DEFAULT 0 + /* For power systems, we want to enable Altivec and VSX builtins even if the user did not use -maltivec or -mvsx to allow the builtins to be used inside of #pragma GCC target or the target attribute to change the code level for a - given system. The SPE and Paired builtins are only enabled if you configure - the compiler for those builtins, and those machines don't support altivec or - VSX. */ - -#define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \ - && ((TARGET_POWERPC64 \ - || TARGET_PPC_GPOPT /* 970/power4 */ \ - || TARGET_POPCNTB /* ISA 2.02 */ \ - || TARGET_CMPB /* ISA 2.05 */ \ - || TARGET_POPCNTD /* ISA 2.06 */ \ - || TARGET_ALTIVEC \ - || TARGET_VSX))) + given system. */ + +#define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \ + || TARGET_PPC_GPOPT /* 970/power4 */ \ + || TARGET_ALTIVEC /* G5/ISA 2.05 */ \ + || TARGET_POPCNTB /* ISA 2.02 */ \ + || TARGET_CMPB /* ISA 2.05 */ \ + || TARGET_POPCNTD /* ISA 2.06 */ \ + || TARGET_VSX /* ISA 2.06 */ \ + || TARGET_PAIRED_FLOAT /* 750CL */ \ + || TARGET_SPE) /* E500 */ /* E500 cores only support plain "sync", not lwsync. */ #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ @@ -654,7 +747,7 @@ extern unsigned char rs6000_recip_bits[] #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size /* Define this to set long double type size to use in libgcc2.c, which can - not depend on target_flags. */ + not depend on rs6000_isa_flags. */ #ifdef __LONG_DOUBLE_128__ #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 #else @@ -2273,29 +2366,15 @@ extern int frame_pointer_needed; #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ -/* Builtin targets. For now, we reuse the masks for those options that are in - target flags, and pick two random bits for SPE and paired which aren't in - target_flags. */ -#define RS6000_BTM_ALWAYS 0 /* Always enabled. */ -#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ -#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ -#define RS6000_BTM_SPE MASK_STRING /* E500 */ -#define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ -#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ -#define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ -#define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ -#define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ -#define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ -#define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ - -#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ - | RS6000_BTM_VSX \ - | RS6000_BTM_FRE \ - | RS6000_BTM_FRES \ - | RS6000_BTM_FRSQRTE \ - | RS6000_BTM_FRSQRTES \ - | RS6000_BTM_POPCNTD \ - | RS6000_BTM_CELL) +/* Options that control builtin targets. */ +#define RS6000_BTM_COMMON (OPTION_MASK_ALTIVEC \ + | OPTION_MASK_VSX \ + | OPTION_MASK_SPE \ + | OPTION_MASK_PAIRED_FLOAT \ + | OPTION_MASK_POPCNTB \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_CELL_BUILTIN) /* Define builtin enum index. */ Index: gcc/config/rs6000/predicates.md =================================================================== --- gcc/config/rs6000/predicates.md (revision 191266) +++ gcc/config/rs6000/predicates.md (working copy) @@ -151,8 +151,8 @@ (define_predicate "cc_reg_not_micro_cr0_ (and (match_operand 0 "register_operand") (match_test "GET_CODE (op) != REG || REGNO (op) > LAST_VIRTUAL_REGISTER - || (rs6000_gen_cell_microcode && CR_REGNO_NOT_CR0_P (REGNO (op))) - || (!rs6000_gen_cell_microcode && CR_REGNO_P (REGNO (op)))"))) + || (TARGET_GEN_CELL_MICROCODE && CR_REGNO_NOT_CR0_P (REGNO (op))) + || (!TARGET_GEN_CELL_MICROCODE && CR_REGNO_P (REGNO (op)))"))) ;; Return 1 if op is a constant integer valid for D field ;; or non-special register register. Index: gcc/config/rs6000/aix64.opt =================================================================== --- gcc/config/rs6000/aix64.opt (revision 191266) +++ gcc/config/rs6000/aix64.opt (working copy) @@ -20,11 +20,11 @@ ; <http://www.gnu.org/licenses/>. maix64 -Target Report RejectNegative Negative(maix32) Mask(64BIT) +Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags) Compile for 64-bit pointers maix32 -Target Report RejectNegative Negative(maix64) InverseMask(64BIT) +Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags) Compile for 32-bit pointers mpe Index: gcc/config/rs6000/sysv4le.h =================================================================== --- gcc/config/rs6000/sysv4le.h (revision 191266) +++ gcc/config/rs6000/sysv4le.h (working copy) @@ -20,7 +20,7 @@ <http://www.gnu.org/licenses/>. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_LITTLE_ENDIAN +#define TARGET_DEFAULT OPTION_MASK_LITTLE_ENDIAN #undef CC1_ENDIAN_DEFAULT_SPEC #define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)" Index: gcc/config/rs6000/xfpu.h =================================================================== --- gcc/config/rs6000/xfpu.h (revision 191266) +++ gcc/config/rs6000/xfpu.h (working copy) @@ -23,4 +23,7 @@ /* Undefine definitions from rs6000.h. */ #undef TARGET_XILINX_FPU -#define TARGET_XILINX_FPU (rs6000_xilinx_fpu) +#define TARGET_XILINX_FPU OPTION_XILINX_FPU + +#define TARGET_USES_XILINX_FPU 1 + Index: gcc/config/rs6000/linux64.opt =================================================================== --- gcc/config/rs6000/linux64.opt (revision 191266) +++ gcc/config/rs6000/linux64.opt (working copy) @@ -20,7 +20,7 @@ ; <http://www.gnu.org/licenses/>. mprofile-kernel -Target Report Var(profile_kernel) Save +Target Report Mask(PROFILE_KERNEL) Var(rs6000_misc_flags) Call mcount for profiling before a function prologue mcmodel= Index: gcc/config/rs6000/freebsd64.h =================================================================== --- gcc/config/rs6000/freebsd64.h (revision 191266) +++ gcc/config/rs6000/freebsd64.h (working copy) @@ -57,7 +57,7 @@ extern int dot_symbols; -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "freebsd" @@ -79,27 +79,28 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ - if (target_flags & MASK_RELOCATABLE) \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error (INVALID_64BIT, "relocatable"); \ } \ - if (target_flags & MASK_EABI) \ + if (rs6000_isa_flags & OPTION_MASK_EABI) \ { \ - target_flags &= ~MASK_EABI; \ + rs6000_isa_flags &= ~OPTION_MASK_EABI; \ error (INVALID_64BIT, "eabi"); \ } \ if (TARGET_PROTOTYPE) \ { \ - target_prototype = 0; \ + rs6000_misc_flags &= ~OPTION_MASK_PROTOTYPE; \ error (INVALID_64BIT, "prototype"); \ } \ - if ((target_flags & MASK_POWERPC64) == 0) \ + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ error ("-m64 requires a PowerPC64 cpu"); \ } \ - if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ + if ((rs6000_isa_flags_explicit \ + & OPTION_MASK_MINIMAL_TOC) != 0) \ { \ if (global_options_set.x_rs6000_current_cmodel \ && rs6000_current_cmodel != CMODEL_SMALL) \ @@ -112,8 +113,8 @@ extern int dot_symbols; SET_CMODEL (CMODEL_MEDIUM); \ if (rs6000_current_cmodel != CMODEL_SMALL) \ { \ - TARGET_NO_FP_IN_TOC = 0; \ - TARGET_NO_SUM_IN_TOC = 0; \ + rs6000_misc_flags &= ~(OPTION_MASK_NO_FP_IN_TOC \ + | OPTION_MASK_NO_SUM_IN_TOC); \ } \ } \ } \ Index: gcc/config/rs6000/aix61.h =================================================================== --- gcc/config/rs6000/aix61.h (revision 191266) +++ gcc/config/rs6000/aix61.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/sysv4.opt =================================================================== --- gcc/config/rs6000/sysv4.opt (revision 191266) +++ gcc/config/rs6000/sysv4.opt (working copy) @@ -45,16 +45,16 @@ EnumValue Enum(rs6000_tls_size) String(64) Value(64) mbit-align -Target Report Var(TARGET_NO_BITFIELD_TYPE) Save +Target Report Mask(NO_BITFIELD_TYPE) Var(rs6000_misc_flags) Align to the base type of the bit-field mstrict-align -Target Report Mask(STRICT_ALIGN) +Target Report Mask(STRICT_ALIGN) Var(rs6000_isa_flags) Align to the base type of the bit-field Don't assume that unaligned accesses are handled by the system mrelocatable -Target Report Mask(RELOCATABLE) +Target Report Mask(RELOCATABLE) Var(rs6000_isa_flags) Produce code relocatable at runtime mrelocatable-lib @@ -62,19 +62,19 @@ Target Produce code relocatable at runtime mlittle-endian -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code mlittle -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code mbig-endian -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code mbig -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code ;; FIXME: This does nothing. What should be done? @@ -87,7 +87,7 @@ Target RejectNegative no description yet mprototype -Target Var(target_prototype) Save +Target Report Mask(PROTOTYPE) Var(rs6000_misc_flags) Assume all variable arg functions are prototyped ;; FIXME: Does nothing. @@ -96,15 +96,15 @@ Target RejectNegative no description yet meabi -Target Report Mask(EABI) +Target Report Mask(EABI) Var(rs6000_isa_flags) Use EABI mbit-word -Target Report Var(TARGET_NO_BITFIELD_WORD) Save +Target Report Mask(NO_BITFIELD_WORD) Var(rs6000_misc_flags) Allow bit-fields to cross word boundaries mregnames -Target Var(rs6000_regnames) Save +Target Mask(REGNAMES) Var(rs6000_misc_flags) Use alternate register names ;; This option does nothing and only exists because the compiler @@ -138,11 +138,11 @@ Target RejectNegative no description yet m64 -Target Report RejectNegative Negative(m32) Mask(64BIT) +Target Report RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target Report RejectNegative Negative(m64) InverseMask(64BIT) +Target Report RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code mnewlib @@ -150,9 +150,9 @@ Target RejectNegative no description yet msecure-plt -Target Report RejectNegative Var(secure_plt, 1) Save +Target Report RejectNegative Mask(SECURE_PLT) Var(rs6000_misc_flags) Generate code to use a non-exec PLT and GOT mbss-plt -Target Report RejectNegative Var(secure_plt, 0) Save +Target Report RejectNegative InverseMask(SECURE_PLT) Var(rs6000_misc_flags) Generate code for old exec BSS PLT Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 191266) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -446,7 +446,7 @@ (define_expand "extendhidi2" (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] - "TARGET_POWERPC64 && rs6000_gen_cell_microcode" + "TARGET_POWERPC64 && TARGET_GEN_CELL_MICROCODE" "@ lha%U1%X1 %0,%1 extsh %0,%1" @@ -455,7 +455,7 @@ (define_insn "" (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))] - "TARGET_POWERPC64 && !rs6000_gen_cell_microcode" + "TARGET_POWERPC64 && !TARGET_GEN_CELL_MICROCODE" "extsh %0,%1" [(set_attr "type" "exts")]) @@ -520,7 +520,7 @@ (define_expand "extendsidi2" (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] - "TARGET_POWERPC64 && rs6000_gen_cell_microcode" + "TARGET_POWERPC64 && TARGET_GEN_CELL_MICROCODE" "@ lwa%U1%X1 %0,%1 extsw %0,%1" @@ -529,7 +529,7 @@ (define_insn "" (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))] - "TARGET_POWERPC64 && !rs6000_gen_cell_microcode" + "TARGET_POWERPC64 && !TARGET_GEN_CELL_MICROCODE" "extsw %0,%1" [(set_attr "type" "exts")]) @@ -907,7 +907,7 @@ (define_expand "extendhisi2" (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] - "rs6000_gen_cell_microcode" + "TARGET_GEN_CELL_MICROCODE" "@ lha%U1%X1 %0,%1 extsh %0,%1" @@ -916,7 +916,7 @@ (define_insn "" (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))] - "!rs6000_gen_cell_microcode" + "!TARGET_GEN_CELL_MICROCODE" "extsh %0,%1" [(set_attr "type" "exts")]) @@ -2766,7 +2766,7 @@ (define_insn "andsi3_mc" (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") (match_operand:SI 2 "and_operand" "?r,T,K,L"))) (clobber (match_scratch:CC 3 "=X,X,x,x"))] - "rs6000_gen_cell_microcode" + "TARGET_GEN_CELL_MICROCODE" "@ and %0,%1,%2 rlwinm %0,%1,0,%m2,%M2 @@ -2779,7 +2779,7 @@ (define_insn "andsi3_nomc" (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") (match_operand:SI 2 "and_operand" "?r,T"))) (clobber (match_scratch:CC 3 "=X,X"))] - "!rs6000_gen_cell_microcode" + "!TARGET_GEN_CELL_MICROCODE" "@ and %0,%1,%2 rlwinm %0,%1,0,%m2,%M2") @@ -2788,7 +2788,7 @@ (define_insn "andsi3_internal0_nomc" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") (match_operand:SI 2 "and_operand" "?r,T")))] - "!rs6000_gen_cell_microcode" + "!TARGET_GEN_CELL_MICROCODE" "@ and %0,%1,%2 rlwinm %0,%1,0,%m2,%M2") @@ -2805,7 +2805,7 @@ (define_insn "*andsi3_internal2_mc" (const_int 0))) (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] - "TARGET_32BIT && rs6000_gen_cell_microcode" + "TARGET_32BIT && TARGET_GEN_CELL_MICROCODE" "@ and. %3,%1,%2 andi. %3,%1,%b2 @@ -2826,7 +2826,7 @@ (define_insn "*andsi3_internal3_mc" (const_int 0))) (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] - "TARGET_64BIT && rs6000_gen_cell_microcode" + "TARGET_64BIT && TARGET_GEN_CELL_MICROCODE" "@ # andi. %3,%1,%b2 @@ -2886,7 +2886,7 @@ (define_insn "*andsi3_internal4" (and:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] - "TARGET_32BIT && rs6000_gen_cell_microcode" + "TARGET_32BIT && TARGET_GEN_CELL_MICROCODE" "@ and. %0,%1,%2 andi. %0,%1,%b2 @@ -2909,7 +2909,7 @@ (define_insn "*andsi3_internal5_mc" (and:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] - "TARGET_64BIT && rs6000_gen_cell_microcode" + "TARGET_64BIT && TARGET_GEN_CELL_MICROCODE" "@ # andi. %0,%1,%b2 @@ -3645,7 +3645,7 @@ (define_insn "*extzvdi_internal1" (match_operand:SI 3 "const_int_operand" "i")) (const_int 0))) (clobber (match_scratch:DI 4 "=r"))] - "TARGET_64BIT && rs6000_gen_cell_microcode" + "TARGET_64BIT && TARGET_GEN_CELL_MICROCODE" "* { int start = INTVAL (operands[3]) & 63; @@ -3668,7 +3668,7 @@ (define_insn "*extzvdi_internal2" (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r") (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] - "TARGET_64BIT && rs6000_gen_cell_microcode" + "TARGET_64BIT && TARGET_GEN_CELL_MICROCODE" "* { int start = INTVAL (operands[3]) & 63; @@ -7312,7 +7312,7 @@ (define_insn "anddi3_mc" (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r") (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t"))) (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))] - "TARGET_POWERPC64 && rs6000_gen_cell_microcode" + "TARGET_POWERPC64 && TARGET_GEN_CELL_MICROCODE" "@ and %0,%1,%2 rldic%B2 %0,%1,0,%S2 @@ -7328,7 +7328,7 @@ (define_insn "anddi3_nomc" (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") (match_operand:DI 2 "and64_2_operand" "?r,S,T,t"))) (clobber (match_scratch:CC 3 "=X,X,X,X"))] - "TARGET_POWERPC64 && !rs6000_gen_cell_microcode" + "TARGET_POWERPC64 && !TARGET_GEN_CELL_MICROCODE" "@ and %0,%1,%2 rldic%B2 %0,%1,0,%S2 @@ -7364,7 +7364,7 @@ (define_insn "*anddi3_internal2_mc" (const_int 0))) (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r")) (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))] - "TARGET_64BIT && rs6000_gen_cell_microcode" + "TARGET_64BIT && TARGET_GEN_CELL_MICROCODE" "@ and. %3,%1,%2 rldic%B2. %3,%1,0,%S2 @@ -7417,7 +7417,7 @@ (define_insn "*anddi3_internal3_mc" (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r") (and:DI (match_dup 1) (match_dup 2))) (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))] - "TARGET_64BIT && rs6000_gen_cell_microcode" + "TARGET_64BIT && TARGET_GEN_CELL_MICROCODE" "@ and. %0,%1,%2 rldic%B2. %0,%1,0,%S2 @@ -9549,7 +9549,7 @@ (define_insn "*movsi_update2" (match_operand:DI 2 "gpc_reg_operand" "r"))))) (set (match_operand:DI 0 "gpc_reg_operand" "=b") (plus:DI (match_dup 1) (match_dup 2)))] - "TARGET_POWERPC64 && rs6000_gen_cell_microcode + "TARGET_POWERPC64 && TARGET_GEN_CELL_MICROCODE && !avoiding_indexed_address_p (DImode)" "lwaux %3,%0,%2" [(set_attr "type" "load_ext_ux")]) @@ -9620,7 +9620,7 @@ (define_insn "*movhi_update3" (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_UPDATE && rs6000_gen_cell_microcode + "TARGET_UPDATE && TARGET_GEN_CELL_MICROCODE && (!avoiding_indexed_address_p (SImode) || !gpc_reg_operand (operands[2], SImode))" "@ Index: gcc/config/rs6000/eabispe.h =================================================================== --- gcc/config/rs6000/eabispe.h (revision 191266) +++ gcc/config/rs6000/eabispe.h (working copy) @@ -20,7 +20,7 @@ <http://www.gnu.org/licenses/>. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_STRICT_ALIGN | MASK_EABI) +#define TARGET_DEFAULT (OPTION_MASK_STRICT_ALIGN | OPTION_MASK_EABI) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc -mspe -me500" Index: gcc/config/rs6000/rs6000-cpus.def =================================================================== --- gcc/config/rs6000/rs6000-cpus.def (revision 191266) +++ gcc/config/rs6000/rs6000-cpus.def (working copy) @@ -32,78 +32,179 @@ where the arguments are the fields of struct rs6000_ptt. */ -RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT) -RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN) -RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("476", PROCESSOR_PPC476, - MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB - | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("476fp", PROCESSOR_PPC476, - MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_MULHW | MASK_DLMZB) + +/* ISA masks. */ +#ifndef ISA_2_1_MASKS +#define ISA_2_1_MASKS OPTION_MASK_MFCRF +#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB) +#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND) + + /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add + ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, + fre, fsqrt, etc. were no longer documented as optional. Group masks by + server and embedded. */ +#define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT) + +#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP) + + /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but + altivec is a win so enable it. */ +#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD) +#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_ALTIVEC \ + | OPTION_MASK_VSX) + +/* Masks for various processors. */ +#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) + +#define POWER_BASE_MASK (OPTION_MASK_POWERPC64 \ + | OPTION_MASK_PPC_GPOPT \ + | OPTION_MASK_PPC_GFXOPT) \ + +#define POWER4_ISA_MASK (POWER_BASE_MASK | ISA_2_1_MASKS) +#define POWER4_TUNE_MASK (OPTION_MASK_SCHED_GROUPS \ + | OPTION_MASK_NO_HINT \ + | OPTION_MASK_ALIGN_BRANCH_TARGETS) + +#define POWER5_ISA_MASK (POWER_BASE_MASK | ISA_2_2_MASKS) +#define POWER5P_ISA_MASK (POWER_BASE_MASK | ISA_2_4_MASKS) +#define POWER5_TUNE_MASK POWER4_TUNE_MASK + +/* Don't include Altivec on power6 because it is generally not a win. */ +#define POWER6_ISA_MASK (POWER_BASE_MASK | ISA_2_5_MASKS_SERVER) +#define POWER6X_ISA_MASK (POWER6_ISA_MASK | OPTION_MASK_MFPGPR) +#define POWER6_TUNE_MASK (OPTION_MASK_NO_HINT \ + | OPTION_MASK_ALIGN_BRANCH_TARGETS \ + | OPTION_MASK_AVOID_XFORM) + +/* Don't add ISEL by default to power7, since it is generally not a win. */ +#define POWER7_ISA_MASK (POWER_BASE_MASK | ISA_2_6_MASKS_SERVER) +#define POWER7_TUNE_MASK POWER4_TUNE_MASK + +#define PPC_476_MASK (OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_MFCRF \ + | OPTION_MASK_POPCNTB \ + | OPTION_MASK_FPRND \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_MULHW \ + | OPTION_MASK_DLMZB \ + | OPTION_MASK_NO_HINT) + +/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ +#define POWERPC_MASKS (OPTION_MASK_ALIGN_BRANCH_TARGETS \ + | OPTION_MASK_ALTIVEC \ + | OPTION_MASK_AVOID_XFORM \ + | OPTION_MASK_CELL_BUILTIN \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_DFP \ + | OPTION_MASK_DLMZB \ + | OPTION_MASK_FPRND \ + | OPTION_MASK_ISEL \ + | OPTION_MASK_MFCRF \ + | OPTION_MASK_MFPGPR \ + | OPTION_MASK_MULHW \ + | OPTION_MASK_NO_FRIZ \ + | OPTION_MASK_NO_HINT \ + | OPTION_MASK_NO_UPDATE \ + | OPTION_MASK_PAIRED_FLOAT \ + | OPTION_MASK_POPCNTB \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_POWERPC64 \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_SCHED_GROUPS \ + | OPTION_MASK_SOFT_FLOAT \ + | OPTION_MASK_SPE \ + | OPTION_MASK_STRICT_ALIGN \ + | OPTION_MASK_VSX \ + | OPTION_MASK_XILINX_FPU) + +#endif + +RS6000_CPU ("401", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("403", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT + | OPTION_MASK_STRICT_ALIGN) +RS6000_CPU ("405", PROCESSOR_PPC405, OPTION_MASK_SOFT_FLOAT + | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("405fp", PROCESSOR_PPC405, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("440", PROCESSOR_PPC440, OPTION_MASK_SOFT_FLOAT + | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("440fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("464", PROCESSOR_PPC440, OPTION_MASK_SOFT_FLOAT + | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("476", PROCESSOR_PPC476, PPC_476_MASK | OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("476fp", PROCESSOR_PPC476, PPC_476_MASK) RS6000_CPU ("505", PROCESSOR_MPCCORE, 0) -RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE | MASK_STRING) -RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT) -RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT) -RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT) -RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT) -RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT) -RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT) +RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE | OPTION_MASK_STRING) +RS6000_CPU ("602", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("603", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("603e", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("604", PROCESSOR_PPC604, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("604e", PROCESSOR_PPC604e, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("620", PROCESSOR_PPC620, OPTION_MASK_PPC_GFXOPT + | OPTION_MASK_POWERPC64) +RS6000_CPU ("630", PROCESSOR_PPC630, OPTION_MASK_PPC_GFXOPT + | OPTION_MASK_POWERPC64) +RS6000_CPU ("740", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT) RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK) RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK) -RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT) -RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL) -RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL) -RS6000_CPU ("a2", PROCESSOR_PPCA2, - MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB - | MASK_NO_UPDATE) -RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT) +RS6000_CPU ("750", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("801", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("821", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("823", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("8540", PROCESSOR_PPC8540, OPTION_MASK_STRICT_ALIGN + | OPTION_MASK_ISEL | OPTION_MASK_SPE) +RS6000_CPU ("8548", PROCESSOR_PPC8548, OPTION_MASK_STRICT_ALIGN + | OPTION_MASK_ISEL | OPTION_MASK_SPE) +RS6000_CPU ("a2", PROCESSOR_PPCA2, OPTION_MASK_PPC_GFXOPT + | OPTION_MASK_POWERPC64 | OPTION_MASK_POPCNTB | OPTION_MASK_CMPB + | OPTION_MASK_NO_UPDATE | OPTION_MASK_NO_HINT) +RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, OPTION_MASK_SOFT_FLOAT) RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0) -RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL) -RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64, - MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) +RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, OPTION_MASK_PPC_GFXOPT + | OPTION_MASK_ISEL | OPTION_MASK_ALIGN_BRANCH_TARGETS) +RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64, OPTION_MASK_POWERPC64 + | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL + | OPTION_MASK_ALIGN_BRANCH_TARGETS) RS6000_CPU ("e5500", PROCESSOR_PPCE5500, - MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) -RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64 - | MASK_MFCRF | MASK_ISEL) -RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("970", PROCESSOR_POWER4, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) -RS6000_CPU ("cell", PROCESSOR_CELL, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) -RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT) -RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT) + OPTION_MASK_POWERPC64 | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL + | OPTION_MASK_ALIGN_BRANCH_TARGETS) +RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK + | OPTION_MASK_POWERPC64 | OPTION_MASK_MFCRF | OPTION_MASK_ISEL + | OPTION_MASK_ALIGN_BRANCH_TARGETS) +RS6000_CPU ("860", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("970", PROCESSOR_POWER4, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_MFCRF | OPTION_MASK_POWERPC64 + | OPTION_MASK_SCHED_GROUPS | OPTION_MASK_NO_HINT + | OPTION_MASK_ALIGN_BRANCH_TARGETS) +RS6000_CPU ("cell", PROCESSOR_CELL, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_MFCRF | OPTION_MASK_POWERPC64 + | OPTION_MASK_CELL_BUILTIN | OPTION_MASK_NO_HINT) +RS6000_CPU ("ec603e", PROCESSOR_PPC603, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("G3", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT) RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK) -RS6000_CPU ("G5", PROCESSOR_POWER4, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) -RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF) -RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB) -RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND) -RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) -RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION) -RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */ - POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF - | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD - | MASK_VSX | MASK_RECIP_PRECISION) +RS6000_CPU ("G5", PROCESSOR_POWER4, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_MFCRF | OPTION_MASK_POWERPC64 + | OPTION_MASK_SCHED_GROUPS | OPTION_MASK_NO_HINT + | OPTION_MASK_ALIGN_BRANCH_TARGETS) +RS6000_CPU ("titan", PROCESSOR_TITAN, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("power3", PROCESSOR_PPC630, OPTION_MASK_PPC_GFXOPT + | OPTION_MASK_POWERPC64) +RS6000_CPU ("power4", PROCESSOR_POWER4, POWER4_ISA_MASK | POWER4_TUNE_MASK) +RS6000_CPU ("power5", PROCESSOR_POWER5, POWER5_ISA_MASK | POWER5_TUNE_MASK) +RS6000_CPU ("power5+", PROCESSOR_POWER5, POWER5P_ISA_MASK | POWER5_TUNE_MASK) +RS6000_CPU ("power6", PROCESSOR_POWER6, POWER6_ISA_MASK | POWER6_TUNE_MASK) +RS6000_CPU ("power6x", PROCESSOR_POWER6, POWER6X_ISA_MASK | POWER6_TUNE_MASK) +RS6000_CPU ("power7", PROCESSOR_POWER7, POWER7_ISA_MASK | POWER7_TUNE_MASK) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) -RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT + | OPTION_MASK_POWERPC64) +RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT + | OPTION_MASK_POWERPC64) Index: gcc/config/rs6000/e500.h =================================================================== --- gcc/config/rs6000/e500.h (revision 191266) +++ gcc/config/rs6000/e500.h (working copy) @@ -24,8 +24,10 @@ #undef TARGET_E500_DOUBLE #undef CHECK_E500_OPTIONS +#define TARGET_USES_SPE 1 + #define TARGET_SPE_ABI rs6000_spe_abi -#define TARGET_SPE rs6000_spe +#define TARGET_SPE OPTION_SPE #define TARGET_FPRS (rs6000_float_gprs == 0) #define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1) #define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2) Index: gcc/config/rs6000/freebsd.h =================================================================== --- gcc/config/rs6000/freebsd.h (revision 191266) +++ gcc/config/rs6000/freebsd.h (working copy) @@ -72,7 +72,7 @@ -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) Index: gcc/config/rs6000/option-defaults.h =================================================================== --- gcc/config/rs6000/option-defaults.h (revision 191266) +++ gcc/config/rs6000/option-defaults.h (working copy) @@ -35,11 +35,11 @@ #define OPT_32 "m32" #endif -#ifndef MASK_64BIT -#define MASK_64BIT 0 +#ifndef OPTION_MASK_64BIT +#define OPTION_MASK_64BIT 0 #endif -#if TARGET_DEFAULT & MASK_64BIT +#if TARGET_DEFAULT & OPTION_MASK_64BIT #define OPT_ARCH64 "!"OPT_32 #define OPT_ARCH32 OPT_32 #else Index: gcc/config/rs6000/rs6000-protos.h =================================================================== --- gcc/config/rs6000/rs6000-protos.h (revision 191266) +++ gcc/config/rs6000/rs6000-protos.h (working copy) @@ -176,7 +176,6 @@ extern void rs6000_call_indirect_aix (rt extern void rs6000_aix_asm_output_dwarf_table_ref (char *); extern void get_ppc476_thunk_name (char name[32]); extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins); -extern unsigned rs6000_builtin_mask_calculate (void); /* Declare functions in rs6000-c.c */ @@ -185,8 +184,8 @@ extern void rs6000_cpu_cpp_builtins (str #ifdef TREE_CODE extern bool rs6000_pragma_target_parse (tree, tree); #endif -extern void rs6000_target_modify_macros (bool, int, unsigned); -extern void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned); +extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT); +extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT); #if TARGET_MACHO char *output_call (rtx, rtx *, int, int); Index: gcc/config/rs6000/vxworks.h =================================================================== --- gcc/config/rs6000/vxworks.h (revision 191266) +++ gcc/config/rs6000/vxworks.h (working copy) @@ -98,7 +98,7 @@ VXWORKS_ADDITIONAL_CPP_SPEC #undef MULTILIB_DEFAULTS #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_EABI | MASK_STRICT_ALIGN) +#define TARGET_DEFAULT (OPTION_MASK_EABI | OPTION_MASK_STRICT_ALIGN) #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_PPC604 Index: gcc/config/rs6000/aix51.h =================================================================== --- gcc/config/rs6000/aix51.h (revision 191266) +++ gcc/config/rs6000/aix51.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_POWERPC64 && ! TARGET_64BIT) \ Index: gcc/config/rs6000/sysv4.h =================================================================== --- gcc/config/rs6000/sysv4.h (revision 191266) +++ gcc/config/rs6000/sysv4.h (working copy) @@ -40,23 +40,22 @@ #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc" -#define TARGET_TOC ((target_flags & MASK_64BIT) \ - || ((target_flags & (MASK_RELOCATABLE \ - | MASK_MINIMAL_TOC)) \ +#define TARGET_TOC ((rs6000_isa_flags & OPTION_MASK_64BIT) \ + || ((rs6000_isa_flags \ + & (OPTION_MASK_RELOCATABLE \ + | OPTION_MASK_MINIMAL_TOC)) \ && flag_pic > 1) \ || DEFAULT_ABI == ABI_AIX) #define TARGET_BITFIELD_TYPE (! TARGET_NO_BITFIELD_TYPE) #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) -#define TARGET_PROTOTYPE target_prototype #define TARGET_NO_PROTOTYPE (! TARGET_PROTOTYPE) #define TARGET_NO_TOC (! TARGET_TOC) #define TARGET_NO_EABI (! TARGET_EABI) -#define TARGET_REGNAMES rs6000_regnames -#ifdef HAVE_AS_REL16 -#undef TARGET_SECURE_PLT -#define TARGET_SECURE_PLT secure_plt +#ifndef HAVE_AS_REL16 +#undef OPTION_SECURE_PLT +#define OPTION_SECURE_PLT 0 #endif #define SDATA_DEFAULT_SIZE 8 @@ -77,13 +76,13 @@ do { \ else if (!strcmp (rs6000_abi_name, "sysv-noeabi")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags &= ~ MASK_EABI; \ + rs6000_isa_flags &= ~ OPTION_MASK_EABI; \ } \ else if (!strcmp (rs6000_abi_name, "sysv-eabi") \ || !strcmp (rs6000_abi_name, "eabi")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags |= MASK_EABI; \ + rs6000_isa_flags |= OPTION_MASK_EABI; \ } \ else if (!strcmp (rs6000_abi_name, "aixdesc")) \ rs6000_current_abi = ABI_AIX; \ @@ -102,9 +101,9 @@ do { \ else if (!strcmp (rs6000_abi_name, "i960-old")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags |= (MASK_LITTLE_ENDIAN | MASK_EABI); \ - target_flags &= ~MASK_STRICT_ALIGN; \ - TARGET_NO_BITFIELD_WORD = 1; \ + rs6000_isa_flags |= (OPTION_MASK_LITTLE_ENDIAN | OPTION_MASK_EABI); \ + rs6000_isa_flags &= ~OPTION_MASK_STRICT_ALIGN; \ + rs6000_misc_flags |= OPTION_MASK_NO_BITFIELD_WORD; \ } \ else \ { \ @@ -168,13 +167,13 @@ do { \ \ if (TARGET_RELOCATABLE && !TARGET_MINIMAL_TOC) \ { \ - target_flags |= MASK_MINIMAL_TOC; \ + rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; \ error ("-mrelocatable and -mno-minimal-toc are incompatible"); \ } \ \ if (TARGET_RELOCATABLE && rs6000_current_abi == ABI_AIX) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error ("-mrelocatable and -mcall-%s are incompatible", \ rs6000_abi_name); \ } \ @@ -188,11 +187,12 @@ do { \ \ if (rs6000_current_abi == ABI_AIX && TARGET_LITTLE_ENDIAN) \ { \ - target_flags &= ~MASK_LITTLE_ENDIAN; \ + rs6000_isa_flags &= ~OPTION_MASK_LITTLE_ENDIAN; \ error ("-mcall-aixdesc must be big endian"); \ } \ \ - if (TARGET_SECURE_PLT != secure_plt) \ + if (!TARGET_SECURE_PLT \ + && ((rs6000_misc_flags & OPTION_MASK_SECURE_PLT) != 0)) \ { \ error ("-msecure-plt not supported by your assembler"); \ } \ @@ -200,8 +200,8 @@ do { \ /* Treat -fPIC the same as -mrelocatable. */ \ if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX) \ { \ - target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; \ - TARGET_NO_FP_IN_TOC = 1; \ + rs6000_isa_flags |= OPTION_MASK_RELOCATABLE | OPTION_MASK_MINIMAL_TOC; \ + rs6000_misc_flags |= OPTION_MASK_NO_FP_IN_TOC; \ } \ \ else if (TARGET_RELOCATABLE) \ @@ -212,9 +212,9 @@ do { \ #ifndef RS6000_BI_ARCH # define SUBSUBTARGET_OVERRIDE_OPTIONS \ do { \ - if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) \ + if ((TARGET_DEFAULT ^ rs6000_isa_flags) & OPTION_MASK_64BIT) \ error ("-m%s not supported in this configuration", \ - (target_flags & MASK_64BIT) ? "64" : "32"); \ + (rs6000_isa_flags & OPTION_MASK_64BIT) ? "64" : "32"); \ } while (0) #endif @@ -500,8 +500,8 @@ extern int fixuplabelno; #define TARGET_OS_SYSV_CPP_BUILTINS() \ do \ { \ - if (target_flags_explicit \ - & MASK_RELOCATABLE) \ + if (rs6000_isa_flags_explicit \ + & OPTION_MASK_RELOCATABLE) \ builtin_define ("_RELOCATABLE"); \ } \ while (0) ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch 2012-09-17 19:52 ` [PATCH] Rs6000 infrastructure cleanup (switches), revised patch Michael Meissner @ 2012-09-19 0:04 ` David Edelsohn 2012-09-20 20:12 ` Michael Meissner 0 siblings, 1 reply; 13+ messages in thread From: David Edelsohn @ 2012-09-19 0:04 UTC (permalink / raw) To: Michael Meissner, gcc-patches, bergner, segher, iain, andreast-list On Mon, Sep 17, 2012 at 3:51 PM, Michael Meissner <meissner@linux.vnet.ibm.com> wrote: > This patch has support for all of the additonal cleanups I mentioned in the > first patch that I hadn't gotten to. At this point, I am not planning any more > enhancements to the patch, and I would like to check it in. > > On my 64-bit powerpc system, there are 36 options in the main ISA flags fields, > 23 options in the miscellaneous flags fields, and 8 options in the debug flag > fields. > > I believe it answers the problems Ian had. I changed all of the debugging > fprintf's to use HOST_WIDE_INT_PRINT_HEX to print the numeric value of the > flags fields, and I changed the #ifdef TARGET_<xxx> to #ifdef OPTION_<xxx>. > > It builds and bootstraps fine on my powerpc64 linux system and there were no > regressions. It is ok to install? Mike, Thanks for working on this cleanup! Is it possible to split out some parts of the patch to make it easier to review and verify? Such as the debug parts? It looks like some parts are independent. Why do you use HOST_WIDE_INT instead of an explicit 64 bit type for the flags? I am confident that it bootstraps and passes regression tests. But how did you verify that it uses the correct defaults after the patch? Thanks, David ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch 2012-09-19 0:04 ` David Edelsohn @ 2012-09-20 20:12 ` Michael Meissner 2012-09-27 22:57 ` [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2b Michael Meissner 0 siblings, 1 reply; 13+ messages in thread From: Michael Meissner @ 2012-09-20 20:12 UTC (permalink / raw) To: David Edelsohn Cc: Michael Meissner, gcc-patches, bergner, segher, iain, andreast-list [-- Attachment #1: Type: text/plain, Size: 8592 bytes --] On Tue, Sep 18, 2012 at 08:04:06PM -0400, David Edelsohn wrote: > Mike, > > Thanks for working on this cleanup! > > Is it possible to split out some parts of the patch to make it easier > to review and verify? Such as the debug parts? It looks like some > parts are independent. Here is the first patch that only changes all of the current options that are target_flags based to rs6000_isa_flags, and adds a bit more debug information for -mdebug=reg (basically printing all of the target flag bits set in human readable terms). Unlike the last patch, I put in a bunch of #defines from OPTION_MASK_<xxx> to MASK_<xxx> so that many of the files did not need to be changed (particularly rs6000-cpus.def). I did the bootstrap and regression test with no regressions on a tree snapped before the INSN_LOCATOR change was made that temporarily broke rs6000 builds. I will merge up to the top, assuming the trunk builds before checkin. Is this first patch acceptable to be checked in? After this goes in, I will do another patch to clean up the builtins, move spe/paired back into rs6000_isa_flags. I also want to move the options that are currently variable options that are settable with attribute target into isa flags as well, to merge two separate tables. Unless I get distracted, I will then do a 3rd patch for the miscellaneous and debug options. The 3rd patch is more of a cleanup patch, and is not strictly needed. 2012-09-20 Michael Meissner <meissner@linux.vnet.ibm.com> * common/config/rs6000/rs6000-common.c (rs6000_handle_option): Move all switches that set target_flags to set rs6000_isa_flags, and make it HOST_WIDE_INT. Save/restore new option words. Add TARGET_<xxx> maps for OPTION_<xxx>. Add MASK_<xxx> maps for OPTION_MASK_<xxx>. Print more debug output for -mdebug=reg. Move masks for different cpu levels to rs6000-cpus.def. Turn off VSX if the assembler doesn't support Altivec. Change #ifdef TARGET_<xxx> to #ifdef OPTION_<xxx>. * gcc/config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix64.opt (-maix64): Likewise. (-maix32): Likewise. * gcc/config/rs6000/darwin.opt (-m64): Likewise. (-m32): Likewise. * gcc/config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * gcc/config/rs6000/freebsd64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/linux.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * gcc/config/rs6000/linux64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (OPTION_LITTLE_ENDIAN): Likewise. (OPTION_RELOCATABLE): Likewise. (OPTION_EABI): Likewise. (OPTION_PROTOTYPE): Likewise. * gcc/config/rs6000/option-defaults.h (OPTION_MASK_64BIT): Likewise. (OPT_ARCH32): Likewise. (OPT_ARCH64): Likewise. * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. (rs6000_cpu_cpp_builtins): Likewise. * gcc/config/rs6000/rs6000-cpus.def (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (ISA_2_6_MASKS_EMBEDDED): Likewise. (ISA_2_6_MASKS_SERVER): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. * gcc/config/rs6000/rs6000-protos.h (rs6000_builtin_mask_calculate): Likewise. (rs6000_target_modify_macros): Likewise. (rs6000_target_modify_macros_ptr): Likewise. * gcc/config/rs6000/rs6000.c (struct builtin_description): Likewise. (rs6000_target_modify_macros_ptr): Likewise. (struct rs6000_builtin_info): Likewise. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (ISA_2_6_MASKS_EMBEDDED): Likewise. (ISA_2_6_MASKS_SERVER): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. (OPTION_MASK_STRICT_ALIGN): Likewise. (struct rs6000_ptt): Likewise. (DEBUG_FMT_ID): Likewise. (DEBUG_FMT_D): Likewise. (DEBUG_FMT_X): Likewise. (DEBUG_FMT_WX): Likewise. (DEBUG_FMT_WX2): Likewise. (DEBUG_FMT_S): Likewise. (rs6000_debug_reg_global): Likewise. (darwin_rs6000_override_options): Likewise. (rs6000_builtin_mask_calculate): Likewise. (rs6000_option_override_internal): Likewise. (rs6000_init_hard_regno_mode_ok): Likewise. (paired_expand_builtin): Likewise. (spe_expand_builtin): Likewise. (rs6000_invalid_builtin): Likewise. (rs6000_expand_builtin): Likewise. (rs6000_builtin_decl): Likewise. (rs6000_common_init_builtins): Likewise. (rs6000_darwin_file_start): Likewise. (struct rs6000_opt_mask): Likewise. (rs6000_opt_masks): Likewise. (rs6000_inner_target_options): Likewise. (rs6000_pragma_target_parse): Likewise. (rs6000_function_specific_save): Likewise. (rs6000_function_specific_restore): Likewise. (rs6000_function_specific_print): Likewise. (rs6000_print_isa_or_misc_options): Likewise. (rs6000_print_isa_options): Likewise. (rs6000_can_inline_p): Likewise. * gcc/config/rs6000/rs6000.h (MASK_64BIT): Likewise. (MASK_ALTIVEC): Likewise. (MASK_CMPB): Likewise. (MASK_DFP): Likewise. (MASK_DLMZB): Likewise. (MASK_EABI): Likewise. (MASK_FPRND): Likewise. (MASK_HARD_FLOAT): Likewise. (MASK_ISEL): Likewise. (MASK_LITTLE_ENDIAN): Likewise. (MASK_MFCRF): Likewise. (MASK_MFPGPR): Likewise. (MASK_MINIMAL_TOC): Likewise. (MASK_MULHW): Likewise. (MASK_MULTIPLE): Likewise. (MASK_NO_UPDATE): Likewise. (MASK_POPCNTB): Likewise. (MASK_POPCNTD): Likewise. (MASK_POWERPC64): Likewise. (MASK_PPC_GFXOPT): Likewise. (MASK_PPC_GPOPT): Likewise. (MASK_PROTOTYPE): Likewise. (MASK_RECIP_PRECISION): Likewise. (MASK_REGNAMES): Likewise. (MASK_RELOCATABLE): Likewise. (MASK_SOFT_FLOAT): Likewise. (MASK_STRICT_ALIGN): Likewise. (MASK_STRING): Likewise. (MASK_UPDATE): Likewise. (MASK_VSX): Likewise. (OPTION_CMPB): Likewise. (OPTION_DFP): LIkewise. (OPTION_FPRND): Likewise. (OPTION_MFCRF): Likewise. (OPTION_MFPGPR): Likewise. (OPTION_POPCNTB): Likewise. (OPTION_POPCNTD): Likewise. (TARGET_64BIT): Likewise. (TARGET_ALTIVEC): Likewise. (TARGET_CMPB): Likewise. (TARGET_DFP): Likewise. (TARGET_DLMZB): Likewise. (TARGET_EABI): Likewise. (TARGET_FPRND): Likewise. (TARGET_HARD_FLOAT): Likewise. (TARGET_ISEL): Likewise. (TARGET_LITTLE_ENDIAN): Likewise. (TARGET_MFCRF): Likewise. (TARGET_MFPGPR): Likewise. (TARGET_MINIMAL_TOC): Likewise. (TARGET_MULHW): Likewise. (TARGET_MULTIPLE): Likewise. (TARGET_NO_UPDATE): Likewise. (TARGET_POPCNTB): Likewise. (TARGET_POPCNTD): Likewise. (TARGET_POWERPC64): Likewise. (TARGET_PPC_GFXOPT): Likewise. (TARGET_PPC_GPOPT): Likewise. (TARGET_PROTOTYPE): Likewise. (TARGET_RECIP_PRECISION): Likewise. (TARGET_REGNAMES): Likewise. (TARGET_RELOCATABLE): Likewise. (TARGET_SOFT_FLOAT): Likewise. (TARGET_STRICT_ALIGN): Likewise. (TARGET_STRING): Likewise. (TARGET_UPDATE): Likewise. (TARGET_VSX): Likewise. * gcc/config/rs6000/rs6000.opt (rs6000_isa_flags): Likewise. (x_rs6000_isa_flags): Likewise. (x_rs6000_ins_flags_explicit): Likewise. (rs6000_builtin_mask): Likewise. (target_flags_explicit): Likewise. (-mpowerpc64): Likewise. (-mpowerpc-gpopt): Likewise. (-mpowerpc-gfxopt): Likewise. (-mmfcrf): Likewise. (-mpopcntb): Likewise. (-mfprnd): Likewise. (-mcmpb): Likewise. (-mmfpgpr): Likewise. (-maltivec): Likewise. (-mhard-dfp): Likewise. (-mmulhw): Likewise. (-mdlmzb): Likewise. (-mmultiple): Likewise. (-mstring): Likewise. (-msoft-float): Likewise. (-mhard-float): Likewise. (-mpopcntd): Likewise. (-mvsx): Likewise. (-mno-update): Likewise. (-mupdate): Likewise. (-mrecip-precision): Likewise. (-mminimal-toc): Likewise. (-misel): Likewise. * gcc/config/rs6000/sysv4.h (TARGET_TOC): Likewise. (SUBTARGET_OVERRIDE_OPTIONS): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (TARGET_OS_SYSV_CPP_BUILTINS): Likewise. * gcc/config/rs6000/sysv4.opt (-mstrict-align): Likewise. (-mrelocatable): Likewise. (-mlittle-endian): Likewise. (-mlittle): Likewise. (-mbig-endian): Likewise. (-mbig): Likewise. (-meabi): Likewise. (-m64): Likewise. (-m32): Likewise. * config/rs6000/t-rs6000 (rs6000.o): Add rs6000-cpus.def dependency. -- Michael Meissner, IBM 5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA meissner@linux.vnet.ibm.com fax +1 (978) 399-6899 [-- Attachment #2: gcc-power7.patch352b --] [-- Type: text/plain, Size: 71138 bytes --] Index: gcc/config/rs6000/aix53.h =================================================================== --- gcc/config/rs6000/aix53.h (revision 191458) +++ gcc/config/rs6000/aix53.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/linux.h =================================================================== --- gcc/config/rs6000/linux.h (revision 191458) +++ gcc/config/rs6000/linux.h (working copy) @@ -109,7 +109,7 @@ -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #define TARGET_POSIX_IO Index: gcc/config/rs6000/t-rs6000 =================================================================== --- gcc/config/rs6000/t-rs6000 (revision 191458) +++ gcc/config/rs6000/t-rs6000 (working copy) @@ -26,7 +26,8 @@ rs6000.o: $(CONFIG_H) $(SYSTEM_H) corety $(OBSTACK_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) except.h function.h \ output.h dbxout.h $(BASIC_BLOCK_H) toplev.h $(GGC_H) $(HASHTAB_H) \ $(TM_P_H) $(TARGET_H) $(TARGET_DEF_H) langhooks.h reload.h gt-rs6000.h \ - cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) + cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) \ + $(srcdir)/config/rs6000/rs6000-cpus.def rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.c \ $(srcdir)/config/rs6000/rs6000-protos.h \ Index: gcc/config/rs6000/aix43.h =================================================================== --- gcc/config/rs6000/aix43.h (revision 191458) +++ gcc/config/rs6000/aix43.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/darwin.opt =================================================================== --- gcc/config/rs6000/darwin.opt (revision 191458) +++ gcc/config/rs6000/darwin.opt (working copy) @@ -34,9 +34,9 @@ findirect-data Driver RejectNegative Alias(mfix-and-continue) m64 -Target RejectNegative Negative(m32) Mask(64BIT) +Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target RejectNegative Negative(m64) InverseMask(64BIT) +Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code Index: gcc/config/rs6000/rs6000.opt =================================================================== --- gcc/config/rs6000/rs6000.opt (revision 191458) +++ gcc/config/rs6000/rs6000.opt (working copy) @@ -22,6 +22,17 @@ HeaderInclude config/rs6000/rs6000-opts.h +;; ISA flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags + +;; Miscellaneous flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags_explicit + ;; Current processor TargetVariable enum processor_type rs6000_cpu = PROCESSOR_PPC603 @@ -80,86 +91,82 @@ unsigned int rs6000_recip_control ;; Mask of what builtin functions are allowed TargetVariable -unsigned int rs6000_builtin_mask +HOST_WIDE_INT rs6000_builtin_mask ;; Debug flags TargetVariable unsigned int rs6000_debug -;; Save for target_flags_explicit -TargetSave -int rs6000_target_flags_explicit - ;; This option existed in the past, but now is always on. mpowerpc Target RejectNegative Undocumented Ignore mpowerpc64 -Target Report Mask(POWERPC64) +Target Report Mask(POWERPC64) Var(rs6000_isa_flags) Use PowerPC-64 instruction set mpowerpc-gpopt -Target Report Mask(PPC_GPOPT) Save +Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) Use PowerPC General Purpose group optional instructions mpowerpc-gfxopt -Target Report Mask(PPC_GFXOPT) Save +Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) Use PowerPC Graphics group optional instructions mmfcrf -Target Report Mask(MFCRF) Save +Target Report Mask(MFCRF) Var(rs6000_isa_flags) Use PowerPC V2.01 single field mfcr instruction mpopcntb -Target Report Mask(POPCNTB) Save +Target Report Mask(POPCNTB) Var(rs6000_isa_flags) Use PowerPC V2.02 popcntb instruction mfprnd -Target Report Mask(FPRND) Save +Target Report Mask(FPRND) Var(rs6000_isa_flags) Use PowerPC V2.02 floating point rounding instructions mcmpb -Target Report Mask(CMPB) Save +Target Report Mask(CMPB) Var(rs6000_isa_flags) Use PowerPC V2.05 compare bytes instruction mmfpgpr -Target Report Mask(MFPGPR) Save +Target Report Mask(MFPGPR) Var(rs6000_isa_flags) Use extended PowerPC V2.05 move floating point to/from GPR instructions maltivec -Target Report Mask(ALTIVEC) Save +Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) Use AltiVec instructions mhard-dfp -Target Report Mask(DFP) Save +Target Report Mask(DFP) Var(rs6000_isa_flags) Use decimal floating point instructions mmulhw -Target Report Mask(MULHW) Save +Target Report Mask(MULHW) Var(rs6000_isa_flags) Use 4xx half-word multiply instructions mdlmzb -Target Report Mask(DLMZB) Save +Target Report Mask(DLMZB) Var(rs6000_isa_flags) Use 4xx string-search dlmzb instruction mmultiple -Target Report Mask(MULTIPLE) Save +Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) Generate load/store multiple instructions mstring -Target Report Mask(STRING) Save +Target Report Mask(STRING) Var(rs6000_isa_flags) Generate string instructions for block moves msoft-float -Target Report RejectNegative Mask(SOFT_FLOAT) +Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) Do not use hardware floating point mhard-float -Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) +Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) Use hardware floating point mpopcntd -Target Report Mask(POPCNTD) Save +Target Report Mask(POPCNTD) Var(rs6000_isa_flags) Use PowerPC V2.06 popcntd instruction mfriz @@ -171,7 +178,7 @@ Target RejectNegative Joined Var(rs6000_ Vector library ABI to use mvsx -Target Report Mask(VSX) Save +Target Report Mask(VSX) Var(rs6000_isa_flags) Use vector/scalar (VSX) instructions mvsx-scalar-double @@ -211,11 +218,11 @@ Target Undocumented Report Var(TARGET_VE ; Explicitly control whether we vectorize the builtins or not. mno-update -Target Report RejectNegative Mask(NO_UPDATE) Save +Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) Do not generate load/store with update instructions mupdate -Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) +Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) Generate load/store with update instructions msingle-pic-base @@ -258,7 +265,7 @@ Target Report RejectNegative Joined Var( Generate software reciprocal divide and square root for better throughput. mrecip-precision -Target Report Mask(RECIP_PRECISION) Save +Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) Assume that the reciprocal estimate instructions provide more accuracy. mno-fp-in-toc @@ -285,7 +292,7 @@ Place symbol+offset constants in TOC ; This is at the cost of having 2 extra loads and one extra store per ; function, and one less allocable register. mminimal-toc -Target Report Mask(MINIMAL_TOC) +Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) Use only one TOC entry per procedure mfull-toc @@ -309,7 +316,7 @@ Target Report Var(rs6000_block_move_inli Specify how many bytes should be moved inline before calling out to memcpy/memmove misel -Target Report Mask(ISEL) Save +Target Report Mask(ISEL) Var(rs6000_isa_flags) Generate isel instructions misel=no Index: gcc/config/rs6000/rs6000-c.c =================================================================== --- gcc/config/rs6000/rs6000-c.c (revision 191458) +++ gcc/config/rs6000/rs6000-c.c (working copy) @@ -285,38 +285,42 @@ rs6000_define_or_undefine_macro (bool de have both the target flags and the builtin flags as arguments. */ void -rs6000_target_modify_macros (bool define_p, int flags, unsigned bu_mask) +rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, + HOST_WIDE_INT bu_mask) { if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) - fprintf (stderr, "rs6000_target_modify_macros (%s, 0x%x, 0x%x)\n", + fprintf (stderr, + "rs6000_target_modify_macros (%s, " + HOST_WIDE_INT_PRINT_HEX ", " + HOST_WIDE_INT_PRINT_HEX ")\n", (define_p) ? "define" : "undef", - (unsigned) flags, bu_mask); + flags, bu_mask); - /* target_flags based options. */ + /* rs6000_isa_flags based options. */ rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); - if ((flags & MASK_PPC_GPOPT) != 0) + if ((flags & OPTION_MASK_PPC_GPOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ"); - if ((flags & MASK_PPC_GFXOPT) != 0) + if ((flags & OPTION_MASK_PPC_GFXOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR"); - if ((flags & MASK_POWERPC64) != 0) + if ((flags & OPTION_MASK_POWERPC64) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"); - if ((flags & MASK_MFCRF) != 0) + if ((flags & OPTION_MASK_MFCRF) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4"); - if ((flags & MASK_POPCNTB) != 0) + if ((flags & OPTION_MASK_POPCNTB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5"); - if ((flags & MASK_FPRND) != 0) + if ((flags & OPTION_MASK_FPRND) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X"); - if ((flags & MASK_CMPB) != 0) + if ((flags & OPTION_MASK_CMPB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); - if ((flags & MASK_MFPGPR) != 0) + if ((flags & OPTION_MASK_MFPGPR) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X"); - if ((flags & MASK_POPCNTD) != 0) + if ((flags & OPTION_MASK_POPCNTD) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); - if ((flags & MASK_SOFT_FLOAT) != 0) + if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); - if ((flags & MASK_RECIP_PRECISION) != 0) + if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__"); - if ((flags & MASK_ALTIVEC) != 0) + if ((flags & OPTION_MASK_ALTIVEC) != 0) { const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__"; rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__"); @@ -326,7 +330,7 @@ rs6000_target_modify_macros (bool define if (!flag_iso) rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__"); } - if ((flags & MASK_VSX) != 0) + if ((flags & OPTION_MASK_VSX) != 0) rs6000_define_or_undefine_macro (define_p, "__VSX__"); /* options from the builtin masks. */ @@ -342,7 +346,7 @@ void rs6000_cpu_cpp_builtins (cpp_reader *pfile) { /* Define all of the common macros. */ - rs6000_target_modify_macros (true, target_flags, + rs6000_target_modify_macros (true, rs6000_isa_flags, rs6000_builtin_mask_calculate ()); if (TARGET_FRE) Index: gcc/config/rs6000/linux64.h =================================================================== --- gcc/config/rs6000/linux64.h (revision 191458) +++ gcc/config/rs6000/linux64.h (working copy) @@ -81,7 +81,7 @@ extern int dot_symbols; -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "linux" @@ -103,14 +103,14 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ - if (target_flags & MASK_RELOCATABLE) \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error (INVALID_64BIT, "relocatable"); \ } \ - if (target_flags & MASK_EABI) \ + if (rs6000_isa_flags & OPTION_MASK_EABI) \ { \ - target_flags &= ~MASK_EABI; \ + rs6000_isa_flags &= ~OPTION_MASK_EABI; \ error (INVALID_64BIT, "eabi"); \ } \ if (TARGET_PROTOTYPE) \ @@ -118,12 +118,13 @@ extern int dot_symbols; target_prototype = 0; \ error (INVALID_64BIT, "prototype"); \ } \ - if ((target_flags & MASK_POWERPC64) == 0) \ + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ error ("-m64 requires a PowerPC64 cpu"); \ } \ - if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ + if ((rs6000_isa_flags_explicit \ + & OPTION_MASK_MINIMAL_TOC) != 0) \ { \ if (global_options_set.x_rs6000_current_cmodel \ && rs6000_current_cmodel != CMODEL_SMALL) \ @@ -213,20 +214,20 @@ extern int dot_symbols; #ifndef RS6000_BI_ARCH /* 64-bit PowerPC Linux is always big-endian. */ -#undef TARGET_LITTLE_ENDIAN -#define TARGET_LITTLE_ENDIAN 0 +#undef OPTION_LITTLE_ENDIAN +#define OPTION_LITTLE_ENDIAN 0 /* 64-bit PowerPC Linux always has a TOC. */ #undef TARGET_TOC #define TARGET_TOC 1 /* Some things from sysv4.h we don't do when 64 bit. */ -#undef TARGET_RELOCATABLE -#define TARGET_RELOCATABLE 0 -#undef TARGET_EABI -#define TARGET_EABI 0 -#undef TARGET_PROTOTYPE -#define TARGET_PROTOTYPE 0 +#undef OPTION_RELOCATABLE +#define OPTION_RELOCATABLE 0 +#undef OPTION_EABI +#define OPTION_EABI 0 +#undef OPTION_PROTOTYPE +#define OPTION_PROTOTYPE 0 #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP 0 Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 191458) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -213,7 +213,7 @@ static GTY(()) section *toc_section; struct builtin_description { - const unsigned int mask; + const HOST_WIDE_INT mask; const enum insn_code icode; const char *const name; const enum rs6000_builtins code; @@ -287,7 +287,7 @@ typedef rtx (*gen_2arg_fn_t) (rtx, rtx, /* Pointer to function (in rs6000-c.c) that can define or undefine target macros that have changed. Languages that don't support the preprocessor don't link in rs6000-c.c, so we can't call it directly. */ -void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned); +void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT); \f /* Target cpu costs. */ @@ -893,7 +893,7 @@ struct processor_costs ppca2_cost = { struct rs6000_builtin_info_type { const char *name; const enum insn_code icode; - const unsigned mask; + const HOST_WIDE_INT mask; const unsigned attr; }; @@ -1015,6 +1015,8 @@ bool (*rs6000_cannot_change_mode_class_p const int INSN_NOT_AVAILABLE = -1; +static void rs6000_print_isa_options (FILE *, HOST_WIDE_INT); + /* Hash table stuff for keeping track of TOC entries. */ struct GTY(()) toc_hash_struct @@ -1115,7 +1117,8 @@ static const struct attribute_spec rs600 { NULL, 0, 0, false, false, false, NULL, false } }; \f -#ifndef MASK_STRICT_ALIGN +#ifndef OPTION_MASK_STRICT_ALIGN +#define OPTION_MASK_STRICT_ALIGN 0 #define MASK_STRICT_ALIGN 0 #endif #ifndef TARGET_PROFILE_KERNEL @@ -1458,53 +1461,12 @@ static const struct attribute_spec rs600 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok \f -/* Simplifications for entries below. */ - -enum { - POWERPC_7400_MASK = MASK_PPC_GFXOPT | MASK_ALTIVEC -}; - -/* Some OSs don't support saving the high part of 64-bit registers on context - switch. Other OSs don't support saving Altivec registers. On those OSs, we - don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants - either, the user must explicitly specify them and we won't interfere with - the user's specification. */ - -enum { - POWERPC_MASKS = (MASK_PPC_GPOPT | MASK_STRICT_ALIGN - | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC - | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW - | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP - | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE - | MASK_RECIP_PRECISION) -}; - -/* Masks for instructions set at various powerpc ISAs. */ -enum { - ISA_2_1_MASKS = MASK_MFCRF, - ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB), - ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND), - - /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add - ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, - fre, fsqrt, etc. were no longer documented as optional. Group masks by - server and embedded. */ - ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION - | MASK_PPC_GFXOPT | MASK_PPC_GPOPT), - ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP), - - /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but - altivec is a win so enable it. */ - ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD), - ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC - | MASK_VSX) -}; - +/* Processor table. */ struct rs6000_ptt { const char *const name; /* Canonical processor name. */ const enum processor_type processor; /* Processor type enum value. */ - const int target_enable; /* Target flags to enable. */ + const HOST_WIDE_INT target_enable; /* Target flags to enable. */ }; static struct rs6000_ptt const processor_target_table[] = @@ -1715,9 +1677,12 @@ rs6000_debug_reg_print (int first_regno, } } -#define DEBUG_FMT_D "%-32s= %d\n" -#define DEBUG_FMT_X "%-32s= 0x%x\n" -#define DEBUG_FMT_S "%-32s= %s\n" +#define DEBUG_FMT_ID "%-32s= " +#define DEBUG_FMT_D DEBUG_FMT_ID "%d\n" +#define DEBUG_FMT_X DEBUG_FMT_ID "%#x\n" +#define DEBUG_FMT_WX DEBUG_FMT_ID HOST_WIDE_INT_PRINT_HEX ": " +#define DEBUG_FMT_WX2 DEBUG_FMT_ID HOST_WIDE_INT_PRINT_HEX "\n" +#define DEBUG_FMT_S DEBUG_FMT_ID "%s\n" /* Print various interesting information with -mdebug=reg. */ static void @@ -1728,11 +1693,13 @@ rs6000_debug_reg_global (void) int m; char costly_num[20]; char nop_num[20]; + char flags_buffer[40]; const char *costly_str; const char *nop_str; const char *trace_str; const char *abi_str; const char *cmodel_str; + struct cl_target_option cl_opts; /* Map enum rs6000_vector to string. */ static const char *rs6000_debug_vector_unit[] = { @@ -1812,12 +1779,69 @@ rs6000_debug_reg_global (void) } if (rs6000_cpu_index >= 0) - fprintf (stderr, DEBUG_FMT_S, "cpu", - processor_target_table[rs6000_cpu_index].name); + { + const char *name = processor_target_table[rs6000_cpu_index].name; + fprintf (stderr, DEBUG_FMT_S, "cpu", name); + sprintf (flags_buffer, "%s cpu flags", name); + + if (processor_target_table[rs6000_cpu_index].target_enable) + { + HOST_WIDE_INT flags + = processor_target_table[rs6000_cpu_index].target_enable; + fprintf (stderr, DEBUG_FMT_WX, flags_buffer, flags); + rs6000_print_isa_options (stderr, flags); + } + else + fprintf (stderr, DEBUG_FMT_S, flags_buffer, "<none>"); + } + else + fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>"); if (rs6000_tune_index >= 0) - fprintf (stderr, DEBUG_FMT_S, "tune", - processor_target_table[rs6000_tune_index].name); + { + const char *name = processor_target_table[rs6000_tune_index].name; + fprintf (stderr, DEBUG_FMT_S, "tune", name); + sprintf (flags_buffer, "%s tune flags", name); + + if (processor_target_table[rs6000_tune_index].target_enable) + { + HOST_WIDE_INT flags + = processor_target_table[rs6000_tune_index].target_enable; + fprintf (stderr, DEBUG_FMT_WX, flags_buffer, flags); + rs6000_print_isa_options (stderr, flags); + } + else + fprintf (stderr, DEBUG_FMT_S, flags_buffer, "<none>"); + } + else + fprintf (stderr, DEBUG_FMT_S, "tune", "<none>"); + + cl_target_option_save (&cl_opts, &global_options); + if (rs6000_isa_flags) + { + fprintf (stderr, DEBUG_FMT_WX, "rs6000_isa_flags", rs6000_isa_flags); + rs6000_print_isa_options (stderr, rs6000_isa_flags); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_isa_flags", "<none>"); + + if (rs6000_isa_flags_explicit) + { + fprintf (stderr, DEBUG_FMT_WX, "rs6000_isa_flags_explicit", + rs6000_isa_flags_explicit); + rs6000_print_isa_options (stderr, rs6000_isa_flags_explicit); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_isa_flags_explicit", "<none>"); + + if (rs6000_builtin_mask) + { + fprintf (stderr, DEBUG_FMT_WX, "rs6000_builtin_mask", + rs6000_builtin_mask); + rs6000_print_isa_options (stderr, rs6000_builtin_mask); + } + else + fprintf (stderr, DEBUG_FMT_S, "rs6000_builtin_mask", "<none>"); switch (rs6000_sched_costly_dep) { @@ -1935,7 +1959,15 @@ rs6000_debug_reg_global (void) if (rs6000_float_gprs) fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true"); + if (TARGET_LINK_STACK) + fprintf (stderr, DEBUG_FMT_S, "link_stack", "true"); + + fprintf (stderr, DEBUG_FMT_S, "plt-format", + TARGET_SECURE_PLT ? "secure" : "bss"); + fprintf (stderr, DEBUG_FMT_S, "struct-return", + aix_struct_return ? "aix" : "sysv"); fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]); + fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]); fprintf (stderr, DEBUG_FMT_S, "align_branch", tf[!!rs6000_align_branch_targets]); fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size); @@ -1947,7 +1979,6 @@ rs6000_debug_reg_global (void) (int)END_BUILTINS); fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins", (int)RS6000_BUILTIN_COUNT); - fprintf (stderr, DEBUG_FMT_X, "Builtin mask", rs6000_builtin_mask); } /* Initialize the various global tables that are based on register size. */ @@ -2311,21 +2342,21 @@ darwin_rs6000_override_options (void) if (TARGET_64BIT && ! TARGET_POWERPC64) { - target_flags |= MASK_POWERPC64; + rs6000_isa_flags |= OPTION_MASK_POWERPC64; warning (0, "-m64 requires PowerPC64 architecture, enabling"); } if (flag_mkernel) { rs6000_default_long_calls = 1; - target_flags |= MASK_SOFT_FLOAT; + rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; } /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes Altivec. */ if (!flag_mkernel && !flag_apple_kext && TARGET_64BIT - && ! (target_flags_explicit & MASK_ALTIVEC)) - target_flags |= MASK_ALTIVEC; + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)) + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; /* Unless the user (not the configurer) has explicitly overridden it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to @@ -2333,10 +2364,10 @@ darwin_rs6000_override_options (void) if (!flag_mkernel && !flag_apple_kext && strverscmp (darwin_macosx_version_min, "10.5") >= 0 - && ! (target_flags_explicit & MASK_ALTIVEC) + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC) && ! global_options_set.x_rs6000_cpu_index) { - target_flags |= MASK_ALTIVEC; + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; } } #endif @@ -2353,7 +2384,7 @@ darwin_rs6000_override_options (void) bits, and some options like SPE and PAIRED are no longer in target_flags. */ -unsigned +HOST_WIDE_INT rs6000_builtin_mask_calculate (void) { return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) @@ -2380,7 +2411,7 @@ rs6000_option_override_internal (bool gl /* The default cpu requested at configure time, if any. */ const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT; - int set_masks; + HOST_WIDE_INT set_masks; int cpu_index; int tune_index; struct cl_target_option *main_target_opt @@ -2417,18 +2448,24 @@ rs6000_option_override_internal (bool gl rs6000_pointer_size = 32; } - set_masks = POWERPC_MASKS | MASK_SOFT_FLOAT; + /* Some OSs don't support saving the high part of 64-bit registers on context + switch. Other OSs don't support saving Altivec registers. On those OSs, + we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings; + if the user wants either, the user must explicitly specify them and we + won't interfere with the user's specification. */ + + set_masks = POWERPC_MASKS; #ifdef OS_MISSING_POWERPC64 if (OS_MISSING_POWERPC64) - set_masks &= ~MASK_POWERPC64; + set_masks &= ~OPTION_MASK_POWERPC64; #endif #ifdef OS_MISSING_ALTIVEC if (OS_MISSING_ALTIVEC) - set_masks &= ~MASK_ALTIVEC; + set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX); #endif /* Don't override by the processor default if given explicitly. */ - set_masks &= ~target_flags_explicit; + set_masks &= ~rs6000_isa_flags_explicit; /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed the cpu in a target attribute or pragma, but did not specify a tuning @@ -2457,9 +2494,9 @@ rs6000_option_override_internal (bool gl gcc_assert (cpu_index >= 0); - target_flags &= ~set_masks; - target_flags |= (processor_target_table[cpu_index].target_enable - & set_masks); + rs6000_isa_flags &= ~set_masks; + rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable + & set_masks); if (rs6000_tune_index >= 0) tune_index = rs6000_tune_index; @@ -2544,7 +2581,8 @@ rs6000_option_override_internal (bool gl use instructions that would be microcoded on the Cell, use the load/store multiple and string instructions. */ if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode) - target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); + rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE + | OPTION_MASK_STRING); /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu is a 750, because the hardware doesn't support the @@ -2556,15 +2594,15 @@ rs6000_option_override_internal (bool gl { if (TARGET_MULTIPLE) { - target_flags &= ~MASK_MULTIPLE; - if ((target_flags_explicit & MASK_MULTIPLE) != 0) + rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE; + if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0) warning (0, "-mmultiple is not supported on little endian systems"); } if (TARGET_STRING) { - target_flags &= ~MASK_STRING; - if ((target_flags_explicit & MASK_STRING) != 0) + rs6000_isa_flags &= ~OPTION_MASK_STRING; + if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0) warning (0, "-mstring is not supported on little endian systems"); } } @@ -2576,10 +2614,10 @@ rs6000_option_override_internal (bool gl if (!TARGET_HARD_FLOAT || !TARGET_FPRS || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx requires hardware floating point"); else - target_flags &= ~ MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; } else if (TARGET_PAIRED_FLOAT) msg = N_("-mvsx and -mpaired are incompatible"); @@ -2590,9 +2628,10 @@ rs6000_option_override_internal (bool gl msg = N_("-mvsx used with little endian code"); else if (TARGET_AVOID_XFORM > 0) msg = N_("-mvsx needs indexed addressing"); - else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC)) + else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit + & OPTION_MASK_ALTIVEC)) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx and -mno-altivec are incompatible"); else msg = N_("-mno-altivec disables vsx"); @@ -2601,27 +2640,27 @@ rs6000_option_override_internal (bool gl if (msg) { warning (0, msg); - target_flags &= ~ MASK_VSX; - target_flags_explicit |= MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; + rs6000_isa_flags_explicit |= OPTION_MASK_VSX; } } /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-<option> to disable the code. */ if (TARGET_VSX) - target_flags |= (ISA_2_6_MASKS_SERVER & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit); else if (TARGET_POPCNTD) - target_flags |= (ISA_2_6_MASKS_EMBEDDED & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit); else if (TARGET_DFP) - target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~rs6000_isa_flags_explicit); else if (TARGET_CMPB) - target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit); else if (TARGET_FPRND) - target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_4_MASKS & ~rs6000_isa_flags_explicit); else if (TARGET_POPCNTB) - target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_2_MASKS & ~rs6000_isa_flags_explicit); else if (TARGET_ALTIVEC) - target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit); + rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit); /* E500mc does "better" if we inline more aggressively. Respect the user's opinion, though. */ @@ -2700,7 +2739,8 @@ rs6000_option_override_internal (bool gl unless the altivec ABI was set. This is set by default for 64-bit, but not for 32-bit. */ if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi) - target_flags &= ~((MASK_VSX | MASK_ALTIVEC) & ~target_flags_explicit); + rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC) + & ~rs6000_isa_flags_explicit); /* Enable Altivec ABI for AIX -maltivec. */ if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX)) @@ -2782,14 +2822,14 @@ rs6000_option_override_internal (bool gl rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE; rs6000_double_float = TARGET_E500_DOUBLE; - target_flags &= ~MASK_STRING; + rs6000_isa_flags &= ~OPTION_MASK_STRING; break; default: - if (have_cpu && !(target_flags_explicit & MASK_ISEL)) - target_flags &= ~MASK_ISEL; + if (have_cpu && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL)) + rs6000_isa_flags &= ~OPTION_MASK_ISEL; break; } @@ -3166,11 +3206,12 @@ rs6000_option_override_internal (bool gl target_flags. */ rs6000_builtin_mask = rs6000_builtin_mask_calculate (); if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) - fprintf (stderr, "new builtin mask = 0x%x%s%s%s%s\n", rs6000_builtin_mask, - (rs6000_builtin_mask & RS6000_BTM_ALTIVEC) ? ", altivec" : "", - (rs6000_builtin_mask & RS6000_BTM_VSX) ? ", vsx" : "", - (rs6000_builtin_mask & RS6000_BTM_PAIRED) ? ", paired" : "", - (rs6000_builtin_mask & RS6000_BTM_SPE) ? ", spe" : ""); + { + fprintf (stderr, + "new builtin mask = " HOST_WIDE_INT_PRINT_HEX ", ", + rs6000_builtin_mask); + rs6000_print_isa_options (stderr, rs6000_builtin_mask); + } /* Initialize all of the registers. */ rs6000_init_hard_regno_mode_ok (global_init_p); @@ -10407,7 +10448,7 @@ altivec_expand_dst_builtin (tree exp, rt bool *expandedp) { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl); tree arg0, arg1, arg2; enum machine_mode mode0, mode1; rtx pat, op0, op1, op2; @@ -10809,7 +10850,7 @@ static rtx paired_expand_builtin (tree exp, rtx target, bool * expandedp) { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl); const struct builtin_description *d; size_t i; @@ -10874,7 +10915,7 @@ spe_expand_builtin (tree exp, rtx target { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); tree arg1, arg0; - unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl); enum insn_code icode; enum machine_mode tmode, mode0; rtx pat, op0; @@ -11239,7 +11280,7 @@ rs6000_invalid_builtin (enum rs6000_buil { size_t uns_fncode = (size_t)fncode; const char *name = rs6000_builtin_info[uns_fncode].name; - unsigned fnmask = rs6000_builtin_info[uns_fncode].mask; + HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask; gcc_assert (name != NULL); if ((fnmask & RS6000_BTM_CELL) != 0) @@ -11276,7 +11317,7 @@ rs6000_expand_builtin (tree exp, rtx tar size_t i; rtx ret; bool success; - unsigned mask = rs6000_builtin_info[uns_fcode].mask; + HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask; bool func_valid_p = ((rs6000_builtin_mask & mask) == mask); if (TARGET_DEBUG_BUILTIN) @@ -11637,7 +11678,7 @@ rs6000_init_builtins (void) static tree rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) { - unsigned fnmask; + HOST_WIDE_INT fnmask; if (code >= RS6000_BUILTIN_COUNT) return error_mark_node; @@ -12509,7 +12550,7 @@ rs6000_common_init_builtins (void) tree v2si_ftype_qi = NULL_TREE; tree v2si_ftype_v2si_qi = NULL_TREE; tree v2si_ftype_int_qi = NULL_TREE; - unsigned builtin_mask = rs6000_builtin_mask; + HOST_WIDE_INT builtin_mask = rs6000_builtin_mask; if (!TARGET_PAIRED_FLOAT) { @@ -12531,7 +12572,7 @@ rs6000_common_init_builtins (void) for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) { tree type; - unsigned mask = d->mask; + HOST_WIDE_INT mask = d->mask; if ((mask & builtin_mask) != mask) { @@ -12572,7 +12613,7 @@ rs6000_common_init_builtins (void) { enum machine_mode mode0, mode1, mode2; tree type; - unsigned mask = d->mask; + HOST_WIDE_INT mask = d->mask; if ((mask & builtin_mask) != mask) { @@ -12635,7 +12676,7 @@ rs6000_common_init_builtins (void) { enum machine_mode mode0, mode1; tree type; - unsigned mask = d->mask; + HOST_WIDE_INT mask = d->mask; if ((mask & builtin_mask) != mask) { @@ -25200,7 +25241,7 @@ rs6000_darwin_file_start (void) { const char *arg; const char *name; - int if_set; + HOST_WIDE_INT if_set; } mapping[] = { { "ppc64", "ppc64", MASK_64BIT }, { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, @@ -25239,7 +25280,7 @@ rs6000_darwin_file_start (void) i = 0; while (mapping[i].arg != NULL && strcmp (mapping[i].arg, cpu_id) != 0 - && (mapping[i].if_set & target_flags) == 0) + && (mapping[i].if_set & rs6000_isa_flags) == 0) i++; fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name); @@ -27333,55 +27374,55 @@ rs6000_final_prescan_insn (rtx insn, rtx struct rs6000_opt_mask { const char *name; /* option name */ - int mask; /* mask to set */ + HOST_WIDE_INT mask; /* mask to set */ bool invert; /* invert sense of mask */ bool valid_target; /* option is a target option */ }; static struct rs6000_opt_mask const rs6000_opt_masks[] = { - { "altivec", MASK_ALTIVEC, false, true }, - { "cmpb", MASK_CMPB, false, true }, - { "dlmzb", MASK_DLMZB, false, true }, - { "fprnd", MASK_FPRND, false, true }, - { "hard-dfp", MASK_DFP, false, true }, - { "isel", MASK_ISEL, false, true }, - { "mfcrf", MASK_MFCRF, false, true }, - { "mfpgpr", MASK_MFPGPR, false, true }, - { "mulhw", MASK_MULHW, false, true }, - { "multiple", MASK_MULTIPLE, false, true }, - { "update", MASK_NO_UPDATE, true , true }, - { "popcntb", MASK_POPCNTB, false, true }, - { "popcntd", MASK_POPCNTD, false, true }, - { "powerpc-gfxopt", MASK_PPC_GFXOPT, false, true }, - { "powerpc-gpopt", MASK_PPC_GPOPT, false, true }, - { "recip-precision", MASK_RECIP_PRECISION, false, true }, - { "string", MASK_STRING, false, true }, - { "vsx", MASK_VSX, false, true }, -#ifdef MASK_64BIT + { "altivec", OPTION_MASK_ALTIVEC, false, true }, + { "cmpb", OPTION_MASK_CMPB, false, true }, + { "dlmzb", OPTION_MASK_DLMZB, false, true }, + { "fprnd", OPTION_MASK_FPRND, false, true }, + { "hard-dfp", OPTION_MASK_DFP, false, true }, + { "isel", OPTION_MASK_ISEL, false, true }, + { "mfcrf", OPTION_MASK_MFCRF, false, true }, + { "mfpgpr", OPTION_MASK_MFPGPR, false, true }, + { "mulhw", OPTION_MASK_MULHW, false, true }, + { "multiple", OPTION_MASK_MULTIPLE, false, true }, + { "update", OPTION_MASK_NO_UPDATE, true , true }, + { "popcntb", OPTION_MASK_POPCNTB, false, true }, + { "popcntd", OPTION_MASK_POPCNTD, false, true }, + { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true }, + { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true }, + { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true }, + { "string", OPTION_MASK_STRING, false, true }, + { "vsx", OPTION_MASK_VSX, false, true }, +#ifdef OPTION_MASK_64BIT #if TARGET_AIX_OS - { "aix64", MASK_64BIT, false, false }, - { "aix32", MASK_64BIT, true, false }, + { "aix64", OPTION_MASK_64BIT, false, false }, + { "aix32", OPTION_MASK_64BIT, true, false }, #else - { "64", MASK_64BIT, false, false }, - { "32", MASK_64BIT, true, false }, + { "64", OPTION_MASK_64BIT, false, false }, + { "32", OPTION_MASK_64BIT, true, false }, #endif #endif -#ifdef MASK_EABI - { "eabi", MASK_EABI, false, false }, +#ifdef OPTION_MASK_EABI + { "eabi", OPTION_MASK_EABI, false, false }, #endif -#ifdef MASK_LITTLE_ENDIAN - { "little", MASK_LITTLE_ENDIAN, false, false }, - { "big", MASK_LITTLE_ENDIAN, true, false }, +#ifdef OPTION_MASK_LITTLE_ENDIAN + { "little", OPTION_MASK_LITTLE_ENDIAN, false, false }, + { "big", OPTION_MASK_LITTLE_ENDIAN, true, false }, #endif -#ifdef MASK_RELOCATABLE - { "relocatable", MASK_RELOCATABLE, false, false }, +#ifdef OPTION_MASK_RELOCATABLE + { "relocatable", OPTION_MASK_RELOCATABLE, false, false }, #endif -#ifdef MASK_STRICT_ALIGN - { "strict-align", MASK_STRICT_ALIGN, false, false }, +#ifdef OPTION_MASK_STRICT_ALIGN + { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false }, #endif - { "soft-float", MASK_SOFT_FLOAT, false, false }, - { "string", MASK_STRING, false, false }, + { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false }, + { "string", OPTION_MASK_STRING, false, false }, }; /* Builtin mask mapping for printing the flags. */ @@ -27485,27 +27526,27 @@ rs6000_inner_target_options (tree args, for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++) if (strcmp (r, rs6000_opt_masks[i].name) == 0) { - int mask = rs6000_opt_masks[i].mask; + HOST_WIDE_INT mask = rs6000_opt_masks[i].mask; if (!rs6000_opt_masks[i].valid_target) not_valid_p = true; else { error_p = false; - target_flags_explicit |= mask; + rs6000_isa_flags_explicit |= mask; /* VSX needs altivec, so -mvsx automagically sets altivec. */ - if (mask == MASK_VSX && !invert) - mask |= MASK_ALTIVEC; + if (mask == OPTION_MASK_VSX && !invert) + mask |= OPTION_MASK_ALTIVEC; if (rs6000_opt_masks[i].invert) invert = !invert; if (invert) - target_flags &= ~mask; + rs6000_isa_flags &= ~mask; else - target_flags |= mask; + rs6000_isa_flags |= mask; } break; } @@ -27709,8 +27750,8 @@ rs6000_pragma_target_parse (tree args, t tree prev_tree = build_target_option_node (); tree cur_tree; struct cl_target_option *prev_opt, *cur_opt; - unsigned prev_bumask, cur_bumask, diff_bumask; - int prev_flags, cur_flags, diff_flags; + HOST_WIDE_INT prev_flags, cur_flags, diff_flags; + HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask; if (TARGET_DEBUG_TARGET) { @@ -27760,14 +27801,14 @@ rs6000_pragma_target_parse (tree args, t { prev_opt = TREE_TARGET_OPTION (prev_tree); prev_bumask = prev_opt->x_rs6000_builtin_mask; - prev_flags = prev_opt->x_target_flags; + prev_flags = prev_opt->x_rs6000_isa_flags; cur_opt = TREE_TARGET_OPTION (cur_tree); - cur_flags = cur_opt->x_target_flags; + cur_flags = cur_opt->x_rs6000_isa_flags; cur_bumask = cur_opt->x_rs6000_builtin_mask; diff_bumask = (prev_bumask ^ cur_bumask); - diff_flags = (prev_flags ^ cur_flags); + diff_flags = (prev_flags ^ cur_flags); if ((diff_flags != 0) || (diff_bumask != 0)) { @@ -27870,7 +27911,8 @@ rs6000_set_current_function (tree fndecl static void rs6000_function_specific_save (struct cl_target_option *ptr) { - ptr->rs6000_target_flags_explicit = target_flags_explicit; + ptr->x_rs6000_isa_flags = rs6000_isa_flags; + ptr->x_rs6000_isa_flags_explicit = rs6000_isa_flags_explicit; } /* Restore the current options */ @@ -27878,47 +27920,62 @@ rs6000_function_specific_save (struct cl static void rs6000_function_specific_restore (struct cl_target_option *ptr) { - target_flags_explicit = ptr->rs6000_target_flags_explicit; + rs6000_isa_flags = ptr->x_rs6000_isa_flags; + rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit; (void) rs6000_option_override_internal (false); } -/* Print the current options */ +/* Helper function to print the current isa or misc options on a line. */ static void -rs6000_function_specific_print (FILE *file, int indent, - struct cl_target_option *ptr) +rs6000_print_isa_or_misc_options (FILE *file, + HOST_WIDE_INT flags, + const struct rs6000_opt_mask *opts, + size_t num_elements) { size_t i; - int flags = ptr->x_target_flags; - unsigned bu_mask = ptr->x_rs6000_builtin_mask; + const char *comma = ""; + const char *suffix = "<none>\n"; /* Print the various mask options. */ - for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++) - if ((flags & rs6000_opt_masks[i].mask) != 0) + for (i = 0; i < num_elements; i++) + if ((flags & opts[i].mask) != 0) { - flags &= ~ rs6000_opt_masks[i].mask; - fprintf (file, "%*s-m%s%s\n", indent, "", + flags &= ~ opts[i].mask; + fprintf (file, "%s-m%s%s", comma, rs6000_opt_masks[i].invert ? "no-" : "", rs6000_opt_masks[i].name); + comma = ", "; + suffix = "\n"; } - /* Print the various options that are variables. */ - for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++) - { - size_t j = rs6000_opt_vars[i].target_offset; - if (((signed char *) ptr)[j]) - fprintf (file, "%*s-m%s\n", indent, "", - rs6000_opt_vars[i].name); - } + fputs (suffix, file); +} - /* Print the various builtin flags. */ - fprintf (file, "%*sbuiltin mask = 0x%x\n", indent, "", bu_mask); - for (i = 0; i < ARRAY_SIZE (rs6000_builtin_mask_names); i++) - if ((bu_mask & rs6000_builtin_mask_names[i].mask) != 0) - { - fprintf (file, "%*s%s builtins supported\n", indent, "", - rs6000_builtin_mask_names[i].name); - } +/* Helper function to print the current isa options on a line. */ + +static void +rs6000_print_isa_options (FILE *file, HOST_WIDE_INT flags) +{ + rs6000_print_isa_or_misc_options (file, flags, &rs6000_opt_masks[0], + ARRAY_SIZE (rs6000_opt_masks)); +} + +/* Print the current options */ + +static void +rs6000_function_specific_print (FILE *file, int indent, + struct cl_target_option *ptr) +{ + fprintf (file, + "%*sOptions (" HOST_WIDE_INT_PRINT_HEX "): ", + indent, "", ptr->x_rs6000_isa_flags); + rs6000_print_isa_options (file, ptr->x_rs6000_isa_flags); + + fprintf (file, + "%*sExplict (" HOST_WIDE_INT_PRINT_HEX "): ", + indent, "", ptr->x_rs6000_isa_flags_explicit); + rs6000_print_isa_options (file, ptr->x_rs6000_isa_flags_explicit); } \f @@ -27948,8 +28005,8 @@ rs6000_can_inline_p (tree caller, tree c /* Callee's options should a subset of the caller's, i.e. a vsx function can inline an altivec function but a non-vsx function can't inline a vsx function. */ - if ((caller_opts->x_target_flags & callee_opts->x_target_flags) - == callee_opts->x_target_flags) + if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags) + == callee_opts->x_rs6000_isa_flags) ret = true; } Index: gcc/config/rs6000/aix52.h =================================================================== --- gcc/config/rs6000/aix52.h (revision 191458) +++ gcc/config/rs6000/aix52.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 191458) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -218,55 +218,55 @@ extern const char *host_detect_local_cpu optional field operand for mfcr. */ #ifndef HAVE_AS_MFCRF -#undef TARGET_MFCRF -#define TARGET_MFCRF 0 +#undef OPTION_MFCRF +#define OPTION_MFCRF 0 #endif /* Define TARGET_POPCNTB if the target assembler does not support the popcount byte instruction. */ #ifndef HAVE_AS_POPCNTB -#undef TARGET_POPCNTB -#define TARGET_POPCNTB 0 +#undef OPTION_POPCNTB +#define OPTION_POPCNTB 0 #endif /* Define TARGET_FPRND if the target assembler does not support the fp rounding instructions. */ #ifndef HAVE_AS_FPRND -#undef TARGET_FPRND -#define TARGET_FPRND 0 +#undef OPTION_FPRND +#define OPTION_FPRND 0 #endif /* Define TARGET_CMPB if the target assembler does not support the cmpb instruction. */ #ifndef HAVE_AS_CMPB -#undef TARGET_CMPB -#define TARGET_CMPB 0 +#undef OPTION_CMPB +#define OPTION_CMPB 0 #endif /* Define TARGET_MFPGPR if the target assembler does not support the mffpr and mftgpr instructions. */ #ifndef HAVE_AS_MFPGPR -#undef TARGET_MFPGPR -#define TARGET_MFPGPR 0 +#undef OPTION_MFPGPR +#define OPTION_MFPGPR 0 #endif /* Define TARGET_DFP if the target assembler does not support decimal floating point instructions. */ #ifndef HAVE_AS_DFP -#undef TARGET_DFP -#define TARGET_DFP 0 +#undef OPTION_DFP +#define OPTION_DFP 0 #endif /* Define TARGET_POPCNTD if the target assembler does not support the popcount word and double word instructions. */ #ifndef HAVE_AS_POPCNTD -#undef TARGET_POPCNTD -#define TARGET_POPCNTD 0 +#undef OPTION_POPCNTD +#define OPTION_POPCNTD 0 #endif /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If @@ -465,6 +465,93 @@ extern int rs6000_vector_align[]; #define TARGET_FCTIDUZ TARGET_POPCNTD #define TARGET_FCTIWUZ TARGET_POPCNTD +/* Map OPTION_<xxx> back into TARGET_<xxx> options in rs6000_isa_flags. */ +#define TARGET_ALTIVEC OPTION_ALTIVEC +#define TARGET_CMPB OPTION_CMPB +#define TARGET_DFP OPTION_DFP +#define TARGET_DLMZB OPTION_DLMZB +#define TARGET_EABI OPTION_EABI +#define TARGET_FPRND OPTION_FPRND +#define TARGET_HARD_FLOAT OPTION_HARD_FLOAT +#define TARGET_ISEL OPTION_ISEL +#define TARGET_MFCRF OPTION_MFCRF +#define TARGET_MFPGPR OPTION_MFPGPR +#define TARGET_MULHW OPTION_MULHW +#define TARGET_MULTIPLE OPTION_MULTIPLE +#define TARGET_NO_UPDATE OPTION_NO_UPDATE +#define TARGET_POPCNTB OPTION_POPCNTB +#define TARGET_POPCNTD OPTION_POPCNTD +#define TARGET_PPC_GFXOPT OPTION_PPC_GFXOPT +#define TARGET_PPC_GPOPT OPTION_PPC_GPOPT +#define TARGET_RECIP_PRECISION OPTION_RECIP_PRECISION +#define TARGET_SOFT_FLOAT OPTION_SOFT_FLOAT +#define TARGET_STRICT_ALIGN OPTION_STRICT_ALIGN +#define TARGET_STRING OPTION_STRING +#define TARGET_UPDATE OPTION_UPDATE +#define TARGET_VSX OPTION_VSX + +#define MASK_ALTIVEC OPTION_MASK_ALTIVEC +#define MASK_CMPB OPTION_MASK_CMPB +#define MASK_DFP OPTION_MASK_DFP +#define MASK_DLMZB OPTION_MASK_DLMZB +#define MASK_EABI OPTION_MASK_EABI +#define MASK_FPRND OPTION_MASK_FPRND +#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT +#define MASK_ISEL OPTION_MASK_ISEL +#define MASK_MFCRF OPTION_MASK_MFCRF +#define MASK_MFPGPR OPTION_MASK_MFPGPR +#define MASK_MULHW OPTION_MASK_MULHW +#define MASK_MULTIPLE OPTION_MASK_MULTIPLE +#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE +#define MASK_POPCNTB OPTION_MASK_POPCNTB +#define MASK_POPCNTD OPTION_MASK_POPCNTD +#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT +#define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT +#define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION +#define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT +#define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN +#define MASK_STRING OPTION_MASK_STRING +#define MASK_UPDATE OPTION_MASK_UPDATE +#define MASK_VSX OPTION_MASK_VSX + +#ifndef IN_LIBGCC2 +#define TARGET_POWERPC64 OPTION_POWERPC64 +#define MASK_POWERPC64 OPTION_MASK_POWERPC64 +#endif + +#ifdef OPTION_64BIT +#define TARGET_64BIT OPTION_64BIT +#define MASK_64BIT OPTION_MASK_64BIT +#endif + +#ifdef OPTION_RELOCATABLE +#define TARGET_RELOCATABLE OPTION_RELOCATABLE +#define MASK_RELOCATABLE OPTION_MASK_RELOCATABLE +#endif + +#ifdef OPTION_LITTLE_ENDIAN +#define TARGET_LITTLE_ENDIAN OPTION_LITTLE_ENDIAN +#define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN +#endif + +#ifdef OPTION_MINIMAL_TOC +#define TARGET_MINIMAL_TOC OPTION_MINIMAL_TOC +#define MASK_MINIMAL_TOC OPTION_MASK_MINIMAL_TOC +#endif + +#ifdef OPTION_REGNAMES +#define TARGET_REGNAMES OPTION_REGNAMES +#define MASK_REGNAMES OPTION_MASK_REGNAMES +#endif + +#ifdef OPTION_PROTOTYPE +#define TARGET_PROTOTYPE OPTION_PROTOTYPE +#define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE +#endif + +/* Explicit ISA options that were set. */ +#define rs6000_isa_flags_explicit global_options_set.x_rs6000_isa_flags + /* For power systems, we want to enable Altivec and VSX builtins even if the user did not use -maltivec or -mvsx to allow the builtins to be used inside of #pragma GCC target or the target attribute to change the code level for a Index: gcc/config/rs6000/aix64.opt =================================================================== --- gcc/config/rs6000/aix64.opt (revision 191458) +++ gcc/config/rs6000/aix64.opt (working copy) @@ -20,11 +20,11 @@ ; <http://www.gnu.org/licenses/>. maix64 -Target Report RejectNegative Negative(maix32) Mask(64BIT) +Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags) Compile for 64-bit pointers maix32 -Target Report RejectNegative Negative(maix64) InverseMask(64BIT) +Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags) Compile for 32-bit pointers mpe Index: gcc/config/rs6000/freebsd64.h =================================================================== --- gcc/config/rs6000/freebsd64.h (revision 191458) +++ gcc/config/rs6000/freebsd64.h (working copy) @@ -57,7 +57,7 @@ extern int dot_symbols; -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "freebsd" @@ -79,14 +79,14 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ - if (target_flags & MASK_RELOCATABLE) \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error (INVALID_64BIT, "relocatable"); \ } \ - if (target_flags & MASK_EABI) \ + if (rs6000_isa_flags & OPTION_MASK_EABI) \ { \ - target_flags &= ~MASK_EABI; \ + rs6000_isa_flags &= ~OPTION_MASK_EABI; \ error (INVALID_64BIT, "eabi"); \ } \ if (TARGET_PROTOTYPE) \ @@ -94,12 +94,13 @@ extern int dot_symbols; target_prototype = 0; \ error (INVALID_64BIT, "prototype"); \ } \ - if ((target_flags & MASK_POWERPC64) == 0) \ + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ error ("-m64 requires a PowerPC64 cpu"); \ } \ - if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ + if ((rs6000_isa_flags_explicit \ + & OPTION_MASK_MINIMAL_TOC) != 0) \ { \ if (global_options_set.x_rs6000_current_cmodel \ && rs6000_current_cmodel != CMODEL_SMALL) \ Index: gcc/config/rs6000/aix61.h =================================================================== --- gcc/config/rs6000/aix61.h (revision 191458) +++ gcc/config/rs6000/aix61.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/sysv4.opt =================================================================== --- gcc/config/rs6000/sysv4.opt (revision 191458) +++ gcc/config/rs6000/sysv4.opt (working copy) @@ -49,12 +49,12 @@ Target Report Var(TARGET_NO_BITFIELD_TYP Align to the base type of the bit-field mstrict-align -Target Report Mask(STRICT_ALIGN) +Target Report Mask(STRICT_ALIGN) Var(rs6000_isa_flags) Align to the base type of the bit-field Don't assume that unaligned accesses are handled by the system mrelocatable -Target Report Mask(RELOCATABLE) +Target Report Mask(RELOCATABLE) Var(rs6000_isa_flags) Produce code relocatable at runtime mrelocatable-lib @@ -62,19 +62,19 @@ Target Produce code relocatable at runtime mlittle-endian -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code mlittle -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code mbig-endian -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code mbig -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code ;; FIXME: This does nothing. What should be done? @@ -96,7 +96,7 @@ Target RejectNegative no description yet meabi -Target Report Mask(EABI) +Target Report Mask(EABI) Var(rs6000_isa_flags) Use EABI mbit-word @@ -138,11 +138,11 @@ Target RejectNegative no description yet m64 -Target Report RejectNegative Negative(m32) Mask(64BIT) +Target Report RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target Report RejectNegative Negative(m64) InverseMask(64BIT) +Target Report RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code mnewlib Index: gcc/config/rs6000/rs6000-cpus.def =================================================================== --- gcc/config/rs6000/rs6000-cpus.def (revision 191458) +++ gcc/config/rs6000/rs6000-cpus.def (working copy) @@ -18,6 +18,57 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ +/* ISA masks. */ +#ifndef ISA_2_1_MASKS +#define ISA_2_1_MASKS OPTION_MASK_MFCRF +#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB) +#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND) + + /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add + ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, + fre, fsqrt, etc. were no longer documented as optional. Group masks by + server and embedded. */ +#define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT) + +#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP) + + /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but + altivec is a win so enable it. */ +#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD) +#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_ALTIVEC \ + | OPTION_MASK_VSX) + +#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) + +/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ +#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_DFP \ + | OPTION_MASK_DLMZB \ + | OPTION_MASK_FPRND \ + | OPTION_MASK_ISEL \ + | OPTION_MASK_MFCRF \ + | OPTION_MASK_MFPGPR \ + | OPTION_MASK_MULHW \ + | OPTION_MASK_NO_UPDATE \ + | OPTION_MASK_POPCNTB \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_POWERPC64 \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_SOFT_FLOAT \ + | OPTION_MASK_STRICT_ALIGN \ + | OPTION_MASK_VSX) + +#endif + /* This table occasionally claims that a processor does not support a particular feature even though it does, but the feature is slower than the alternative. Thus, it shouldn't be relied on as a complete description of Index: gcc/config/rs6000/freebsd.h =================================================================== --- gcc/config/rs6000/freebsd.h (revision 191458) +++ gcc/config/rs6000/freebsd.h (working copy) @@ -72,7 +72,7 @@ -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) Index: gcc/config/rs6000/option-defaults.h =================================================================== --- gcc/config/rs6000/option-defaults.h (revision 191458) +++ gcc/config/rs6000/option-defaults.h (working copy) @@ -35,11 +35,12 @@ #define OPT_32 "m32" #endif -#ifndef MASK_64BIT +#ifndef OPTION_MASK_64BIT +#define OPTION_MASK_64BIT 0 #define MASK_64BIT 0 #endif -#if TARGET_DEFAULT & MASK_64BIT +#if TARGET_DEFAULT & OPTION_MASK_64BIT #define OPT_ARCH64 "!"OPT_32 #define OPT_ARCH32 OPT_32 #else Index: gcc/config/rs6000/rs6000-protos.h =================================================================== --- gcc/config/rs6000/rs6000-protos.h (revision 191458) +++ gcc/config/rs6000/rs6000-protos.h (working copy) @@ -176,7 +176,7 @@ extern void rs6000_call_indirect_aix (rt extern void rs6000_aix_asm_output_dwarf_table_ref (char *); extern void get_ppc476_thunk_name (char name[32]); extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins); -extern unsigned rs6000_builtin_mask_calculate (void); +extern HOST_WIDE_INT rs6000_builtin_mask_calculate (void); /* Declare functions in rs6000-c.c */ @@ -185,8 +185,9 @@ extern void rs6000_cpu_cpp_builtins (str #ifdef TREE_CODE extern bool rs6000_pragma_target_parse (tree, tree); #endif -extern void rs6000_target_modify_macros (bool, int, unsigned); -extern void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned); +extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT, HOST_WIDE_INT); +extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, + HOST_WIDE_INT); #if TARGET_MACHO char *output_call (rtx, rtx *, int, int); Index: gcc/config/rs6000/aix51.h =================================================================== --- gcc/config/rs6000/aix51.h (revision 191458) +++ gcc/config/rs6000/aix51.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_POWERPC64 && ! TARGET_64BIT) \ Index: gcc/config/rs6000/sysv4.h =================================================================== --- gcc/config/rs6000/sysv4.h (revision 191458) +++ gcc/config/rs6000/sysv4.h (working copy) @@ -40,9 +40,10 @@ #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc" -#define TARGET_TOC ((target_flags & MASK_64BIT) \ - || ((target_flags & (MASK_RELOCATABLE \ - | MASK_MINIMAL_TOC)) \ +#define TARGET_TOC ((rs6000_isa_flags & OPTION_MASK_64BIT) \ + || ((rs6000_isa_flags \ + & (OPTION_MASK_RELOCATABLE \ + | OPTION_MASK_MINIMAL_TOC)) \ && flag_pic > 1) \ || DEFAULT_ABI == ABI_AIX) @@ -77,13 +78,13 @@ do { \ else if (!strcmp (rs6000_abi_name, "sysv-noeabi")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags &= ~ MASK_EABI; \ + rs6000_isa_flags &= ~ OPTION_MASK_EABI; \ } \ else if (!strcmp (rs6000_abi_name, "sysv-eabi") \ || !strcmp (rs6000_abi_name, "eabi")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags |= MASK_EABI; \ + rs6000_isa_flags |= OPTION_MASK_EABI; \ } \ else if (!strcmp (rs6000_abi_name, "aixdesc")) \ rs6000_current_abi = ABI_AIX; \ @@ -102,8 +103,8 @@ do { \ else if (!strcmp (rs6000_abi_name, "i960-old")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags |= (MASK_LITTLE_ENDIAN | MASK_EABI); \ - target_flags &= ~MASK_STRICT_ALIGN; \ + rs6000_isa_flags |= (OPTION_MASK_LITTLE_ENDIAN | OPTION_MASK_EABI); \ + rs6000_isa_flags &= ~OPTION_MASK_STRICT_ALIGN; \ TARGET_NO_BITFIELD_WORD = 1; \ } \ else \ @@ -168,13 +169,13 @@ do { \ \ if (TARGET_RELOCATABLE && !TARGET_MINIMAL_TOC) \ { \ - target_flags |= MASK_MINIMAL_TOC; \ + rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; \ error ("-mrelocatable and -mno-minimal-toc are incompatible"); \ } \ \ if (TARGET_RELOCATABLE && rs6000_current_abi == ABI_AIX) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error ("-mrelocatable and -mcall-%s are incompatible", \ rs6000_abi_name); \ } \ @@ -188,7 +189,7 @@ do { \ \ if (rs6000_current_abi == ABI_AIX && TARGET_LITTLE_ENDIAN) \ { \ - target_flags &= ~MASK_LITTLE_ENDIAN; \ + rs6000_isa_flags &= ~OPTION_MASK_LITTLE_ENDIAN; \ error ("-mcall-aixdesc must be big endian"); \ } \ \ @@ -200,7 +201,7 @@ do { \ /* Treat -fPIC the same as -mrelocatable. */ \ if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX) \ { \ - target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; \ + rs6000_isa_flags |= OPTION_MASK_RELOCATABLE | OPTION_MASK_MINIMAL_TOC; \ TARGET_NO_FP_IN_TOC = 1; \ } \ \ @@ -212,9 +213,9 @@ do { \ #ifndef RS6000_BI_ARCH # define SUBSUBTARGET_OVERRIDE_OPTIONS \ do { \ - if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) \ + if ((TARGET_DEFAULT ^ rs6000_isa_flags) & OPTION_MASK_64BIT) \ error ("-m%s not supported in this configuration", \ - (target_flags & MASK_64BIT) ? "64" : "32"); \ + (rs6000_isa_flags & OPTION_MASK_64BIT) ? "64" : "32"); \ } while (0) #endif @@ -500,8 +501,8 @@ extern int fixuplabelno; #define TARGET_OS_SYSV_CPP_BUILTINS() \ do \ { \ - if (target_flags_explicit \ - & MASK_RELOCATABLE) \ + if (rs6000_isa_flags_explicit \ + & OPTION_MASK_RELOCATABLE) \ builtin_define ("_RELOCATABLE"); \ } \ while (0) Index: gcc/common/config/rs6000/rs6000-common.c =================================================================== --- gcc/common/config/rs6000/rs6000-common.c (revision 191458) +++ gcc/common/config/rs6000/rs6000-common.c (working copy) @@ -82,23 +82,23 @@ rs6000_handle_option (struct gcc_options switch (code) { case OPT_mfull_toc: - opts->x_target_flags &= ~MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_MINIMAL_TOC; opts->x_TARGET_NO_FP_IN_TOC = 0; opts->x_TARGET_NO_SUM_IN_TOC = 0; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; #ifdef TARGET_USES_SYSV4_OPT /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be just the same as -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; #endif break; #ifdef TARGET_USES_SYSV4_OPT case OPT_mtoc: /* Make -mtoc behave like -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; break; #endif @@ -107,9 +107,10 @@ rs6000_handle_option (struct gcc_options #else case OPT_m64: #endif - opts->x_target_flags |= MASK_POWERPC64; - opts->x_target_flags |= ~opts_set->x_target_flags & MASK_PPC_GFXOPT; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; + opts->x_rs6000_isa_flags |= (~opts_set->x_rs6000_isa_flags + & OPTION_MASK_PPC_GFXOPT); + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; #ifdef TARGET_USES_AIX64_OPT @@ -117,8 +118,8 @@ rs6000_handle_option (struct gcc_options #else case OPT_m32: #endif - opts->x_target_flags &= ~MASK_POWERPC64; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_POWERPC64; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; case OPT_mminimal_toc: @@ -181,8 +182,8 @@ rs6000_handle_option (struct gcc_options case OPT_mrelocatable: if (value == 1) { - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; opts->x_TARGET_NO_FP_IN_TOC = 1; } break; @@ -190,14 +191,16 @@ rs6000_handle_option (struct gcc_options case OPT_mrelocatable_lib: if (value == 1) { - opts->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); + opts_set->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); opts->x_TARGET_NO_FP_IN_TOC = 1; } else { - opts->x_target_flags &= ~MASK_RELOCATABLE; - opts_set->x_target_flags |= MASK_RELOCATABLE; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_RELOCATABLE; } break; #endif @@ -227,15 +230,15 @@ rs6000_handle_option (struct gcc_options "-msingle-float option equivalent to -mhard-float"); /* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_double_float = 0; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_mdouble_float: /* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_single_float = 1; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_msimple_fpu: @@ -259,8 +262,8 @@ rs6000_handle_option (struct gcc_options { /* If -mfpu is not none, then turn off SOFT_FLOAT, turn on HARD_FLOAT. */ - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; opts->x_rs6000_xilinx_fpu = 1; if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL) opts->x_rs6000_single_float = 1; @@ -272,8 +275,8 @@ rs6000_handle_option (struct gcc_options else { /* -mfpu=none is equivalent to -msoft-float. */ - opts->x_target_flags |= MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0; } break; @@ -297,8 +300,4 @@ rs6000_handle_option (struct gcc_options #undef TARGET_OPTION_OPTIMIZATION_TABLE #define TARGET_OPTION_OPTIMIZATION_TABLE rs6000_option_optimization_table -#undef TARGET_DEFAULT_TARGET_FLAGS -#define TARGET_DEFAULT_TARGET_FLAGS \ - (TARGET_DEFAULT) - struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2b 2012-09-20 20:12 ` Michael Meissner @ 2012-09-27 22:57 ` Michael Meissner 2012-10-04 1:42 ` David Edelsohn 0 siblings, 1 reply; 13+ messages in thread From: Michael Meissner @ 2012-09-27 22:57 UTC (permalink / raw) To: David Edelsohn, gcc-patches, bergner, segher, iain, andreast-list [-- Attachment #1: Type: text/plain, Size: 8106 bytes --] (Lets try this again, this time attaching the said patch). This patch fixes a long standing bug that David noticed, namely if you don't use -mcpu=<xxx>, the target options that are set by the configuration .h files in TARGET_DEFAULT are cleared if they are in POWERPC_MASKS. Note, if you configure the compiler using --with-cpu=<xxx>, it provides a default cpu, so users using pre-packaged compilers, typically would not see the bug. In adding the support for the above change, I also tweaked the debug output for -mdebug=reg so it prints more information about the switches set. Other than that, this is the same patch that I previously submitted. I have done the bootstrap and make check with no regressions. I have also built special compilers without --with-cpu to make sure the changes were correctly propigated. Are these patches ok to install? 2012-09-27 Michael Meissner <meissner@linux.vnet.ibm.com> * common/config/rs6000/rs6000-common.c (rs6000_handle_option): Move all switches that set target_flags to set rs6000_isa_flags, and make it HOST_WIDE_INT. Save/restore new option words. Add TARGET_<xxx> maps for OPTION_<xxx>. Add MASK_<xxx> maps for OPTION_MASK_<xxx>. Print more debug output for -mdebug=reg. Move masks for different cpu levels to rs6000-cpus.def. Turn off VSX if the assembler doesn't support Altivec. Change #ifdef TARGET_<xxx> to #ifdef OPTION_<xxx>. If no -mcpu=<xxx> was used, use all of the bits in TARGET_DEFAULT for the isa bits. * gcc/config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix64.opt (-maix64): Likewise. (-maix32): Likewise. * gcc/config/rs6000/darwin.opt (-m64): Likewise. (-m32): Likewise. * gcc/config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * gcc/config/rs6000/freebsd64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/linux.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * gcc/config/rs6000/linux64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (OPTION_LITTLE_ENDIAN): Likewise. (OPTION_RELOCATABLE): Likewise. (OPTION_EABI): Likewise. (OPTION_PROTOTYPE): Likewise. * gcc/config/rs6000/option-defaults.h (OPTION_MASK_64BIT): Likewise. (OPT_ARCH32): Likewise. (OPT_ARCH64): Likewise. * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. (rs6000_cpu_cpp_builtins): Likewise. * gcc/config/rs6000/rs6000-cpus.def (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (ISA_2_6_MASKS_EMBEDDED): Likewise. (ISA_2_6_MASKS_SERVER): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. * gcc/config/rs6000/rs6000-protos.h (rs6000_builtin_mask_calculate): Likewise. (rs6000_target_modify_macros): Likewise. (rs6000_target_modify_macros_ptr): Likewise. * gcc/config/rs6000/rs6000.c (struct builtin_description): Likewise. (rs6000_target_modify_macros_ptr): Likewise. (struct rs6000_builtin_info): Likewise. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (ISA_2_6_MASKS_EMBEDDED): Likewise. (ISA_2_6_MASKS_SERVER): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. (OPTION_MASK_STRICT_ALIGN): Likewise. (struct rs6000_ptt): Likewise. (DEBUG_FMT_ID): Likewise. (DEBUG_FMT_D): Likewise. (DEBUG_FMT_X): Likewise. (DEBUG_FMT_WX): Likewise. (DEBUG_FMT_WX2): Likewise. (DEBUG_FMT_S): Likewise. (rs6000_debug_reg_global): Likewise. (darwin_rs6000_override_options): Likewise. (rs6000_builtin_mask_calculate): Likewise. (rs6000_option_override_internal): Likewise. (rs6000_init_hard_regno_mode_ok): Likewise. (paired_expand_builtin): Likewise. (spe_expand_builtin): Likewise. (rs6000_invalid_builtin): Likewise. (rs6000_expand_builtin): Likewise. (rs6000_builtin_decl): Likewise. (rs6000_common_init_builtins): Likewise. (rs6000_darwin_file_start): Likewise. (struct rs6000_opt_mask): Likewise. (rs6000_opt_masks): Likewise. (rs6000_inner_target_options): Likewise. (rs6000_pragma_target_parse): Likewise. (rs6000_function_specific_save): Likewise. (rs6000_function_specific_restore): Likewise. (rs6000_function_specific_print): Likewise. (rs6000_print_isa_or_misc_options): Likewise. (rs6000_print_isa_options): Likewise. (rs6000_can_inline_p): Likewise. * gcc/config/rs6000/rs6000.h (MASK_64BIT): Likewise. (MASK_ALTIVEC): Likewise. (MASK_CMPB): Likewise. (MASK_DFP): Likewise. (MASK_DLMZB): Likewise. (MASK_EABI): Likewise. (MASK_FPRND): Likewise. (MASK_HARD_FLOAT): Likewise. (MASK_ISEL): Likewise. (MASK_LITTLE_ENDIAN): Likewise. (MASK_MFCRF): Likewise. (MASK_MFPGPR): Likewise. (MASK_MINIMAL_TOC): Likewise. (MASK_MULHW): Likewise. (MASK_MULTIPLE): Likewise. (MASK_NO_UPDATE): Likewise. (MASK_POPCNTB): Likewise. (MASK_POPCNTD): Likewise. (MASK_POWERPC64): Likewise. (MASK_PPC_GFXOPT): Likewise. (MASK_PPC_GPOPT): Likewise. (MASK_PROTOTYPE): Likewise. (MASK_RECIP_PRECISION): Likewise. (MASK_REGNAMES): Likewise. (MASK_RELOCATABLE): Likewise. (MASK_SOFT_FLOAT): Likewise. (MASK_STRICT_ALIGN): Likewise. (MASK_STRING): Likewise. (MASK_UPDATE): Likewise. (MASK_VSX): Likewise. (OPTION_CMPB): Likewise. (OPTION_DFP): LIkewise. (OPTION_FPRND): Likewise. (OPTION_MFCRF): Likewise. (OPTION_MFPGPR): Likewise. (OPTION_POPCNTB): Likewise. (OPTION_POPCNTD): Likewise. (TARGET_64BIT): Likewise. (TARGET_ALTIVEC): Likewise. (TARGET_CMPB): Likewise. (TARGET_DFP): Likewise. (TARGET_DLMZB): Likewise. (TARGET_EABI): Likewise. (TARGET_FPRND): Likewise. (TARGET_HARD_FLOAT): Likewise. (TARGET_ISEL): Likewise. (TARGET_LITTLE_ENDIAN): Likewise. (TARGET_MFCRF): Likewise. (TARGET_MFPGPR): Likewise. (TARGET_MINIMAL_TOC): Likewise. (TARGET_MULHW): Likewise. (TARGET_MULTIPLE): Likewise. (TARGET_NO_UPDATE): Likewise. (TARGET_POPCNTB): Likewise. (TARGET_POPCNTD): Likewise. (TARGET_POWERPC64): Likewise. (TARGET_PPC_GFXOPT): Likewise. (TARGET_PPC_GPOPT): Likewise. (TARGET_PROTOTYPE): Likewise. (TARGET_RECIP_PRECISION): Likewise. (TARGET_REGNAMES): Likewise. (TARGET_RELOCATABLE): Likewise. (TARGET_SOFT_FLOAT): Likewise. (TARGET_STRICT_ALIGN): Likewise. (TARGET_STRING): Likewise. (TARGET_UPDATE): Likewise. (TARGET_VSX): Likewise. * gcc/config/rs6000/rs6000.opt (rs6000_isa_flags): Likewise. (x_rs6000_isa_flags): Likewise. (x_rs6000_ins_flags_explicit): Likewise. (rs6000_builtin_mask): Likewise. (target_flags_explicit): Likewise. (-mpowerpc64): Likewise. (-mpowerpc-gpopt): Likewise. (-mpowerpc-gfxopt): Likewise. (-mmfcrf): Likewise. (-mpopcntb): Likewise. (-mfprnd): Likewise. (-mcmpb): Likewise. (-mmfpgpr): Likewise. (-maltivec): Likewise. (-mhard-dfp): Likewise. (-mmulhw): Likewise. (-mdlmzb): Likewise. (-mmultiple): Likewise. (-mstring): Likewise. (-msoft-float): Likewise. (-mhard-float): Likewise. (-mpopcntd): Likewise. (-mvsx): Likewise. (-mno-update): Likewise. (-mupdate): Likewise. (-mrecip-precision): Likewise. (-mminimal-toc): Likewise. (-misel): Likewise. * gcc/config/rs6000/sysv4.h (TARGET_TOC): Likewise. (SUBTARGET_OVERRIDE_OPTIONS): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (TARGET_OS_SYSV_CPP_BUILTINS): Likewise. * gcc/config/rs6000/sysv4.opt (-mstrict-align): Likewise. (-mrelocatable): Likewise. (-mlittle-endian): Likewise. (-mlittle): Likewise. (-mbig-endian): Likewise. (-mbig): Likewise. (-meabi): Likewise. (-m64): Likewise. (-m32): Likewise. * config/rs6000/t-rs6000 (rs6000.o): Add rs6000-cpus.def dependency. -- Michael Meissner, IBM 5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA meissner@linux.vnet.ibm.com fax +1 (978) 399-6899 [-- Attachment #2: gcc-power7.patch353b --] [-- Type: text/plain, Size: 71228 bytes --] Index: gcc/common/config/rs6000/rs6000-common.c =================================================================== --- gcc/common/config/rs6000/rs6000-common.c (revision 191811) +++ gcc/common/config/rs6000/rs6000-common.c (working copy) @@ -82,23 +82,23 @@ rs6000_handle_option (struct gcc_options switch (code) { case OPT_mfull_toc: - opts->x_target_flags &= ~MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_MINIMAL_TOC; opts->x_TARGET_NO_FP_IN_TOC = 0; opts->x_TARGET_NO_SUM_IN_TOC = 0; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; #ifdef TARGET_USES_SYSV4_OPT /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be just the same as -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; #endif break; #ifdef TARGET_USES_SYSV4_OPT case OPT_mtoc: /* Make -mtoc behave like -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; break; #endif @@ -107,9 +107,10 @@ rs6000_handle_option (struct gcc_options #else case OPT_m64: #endif - opts->x_target_flags |= MASK_POWERPC64; - opts->x_target_flags |= ~opts_set->x_target_flags & MASK_PPC_GFXOPT; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; + opts->x_rs6000_isa_flags |= (~opts_set->x_rs6000_isa_flags + & OPTION_MASK_PPC_GFXOPT); + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; #ifdef TARGET_USES_AIX64_OPT @@ -117,8 +118,8 @@ rs6000_handle_option (struct gcc_options #else case OPT_m32: #endif - opts->x_target_flags &= ~MASK_POWERPC64; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_POWERPC64; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; case OPT_mminimal_toc: @@ -181,8 +182,8 @@ rs6000_handle_option (struct gcc_options case OPT_mrelocatable: if (value == 1) { - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; opts->x_TARGET_NO_FP_IN_TOC = 1; } break; @@ -190,14 +191,16 @@ rs6000_handle_option (struct gcc_options case OPT_mrelocatable_lib: if (value == 1) { - opts->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); + opts_set->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); opts->x_TARGET_NO_FP_IN_TOC = 1; } else { - opts->x_target_flags &= ~MASK_RELOCATABLE; - opts_set->x_target_flags |= MASK_RELOCATABLE; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_RELOCATABLE; } break; #endif @@ -227,15 +230,15 @@ rs6000_handle_option (struct gcc_options "-msingle-float option equivalent to -mhard-float"); /* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_double_float = 0; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_mdouble_float: /* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_single_float = 1; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_msimple_fpu: @@ -259,8 +262,8 @@ rs6000_handle_option (struct gcc_options { /* If -mfpu is not none, then turn off SOFT_FLOAT, turn on HARD_FLOAT. */ - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; opts->x_rs6000_xilinx_fpu = 1; if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL) opts->x_rs6000_single_float = 1; @@ -272,8 +275,8 @@ rs6000_handle_option (struct gcc_options else { /* -mfpu=none is equivalent to -msoft-float. */ - opts->x_target_flags |= MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0; } break; @@ -297,8 +300,4 @@ rs6000_handle_option (struct gcc_options #undef TARGET_OPTION_OPTIMIZATION_TABLE #define TARGET_OPTION_OPTIMIZATION_TABLE rs6000_option_optimization_table -#undef TARGET_DEFAULT_TARGET_FLAGS -#define TARGET_DEFAULT_TARGET_FLAGS \ - (TARGET_DEFAULT) - struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; Index: gcc/config/rs6000/aix53.h =================================================================== --- gcc/config/rs6000/aix53.h (revision 191811) +++ gcc/config/rs6000/aix53.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/linux.h =================================================================== --- gcc/config/rs6000/linux.h (revision 191811) +++ gcc/config/rs6000/linux.h (working copy) @@ -109,7 +109,7 @@ -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #define TARGET_POSIX_IO Index: gcc/config/rs6000/t-rs6000 =================================================================== --- gcc/config/rs6000/t-rs6000 (revision 191811) +++ gcc/config/rs6000/t-rs6000 (working copy) @@ -26,7 +26,8 @@ rs6000.o: $(CONFIG_H) $(SYSTEM_H) corety $(OBSTACK_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) except.h function.h \ output.h dbxout.h $(BASIC_BLOCK_H) toplev.h $(GGC_H) $(HASHTAB_H) \ $(TM_P_H) $(TARGET_H) $(TARGET_DEF_H) langhooks.h reload.h gt-rs6000.h \ - cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) + cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) \ + $(srcdir)/config/rs6000/rs6000-cpus.def rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.c \ $(srcdir)/config/rs6000/rs6000-protos.h \ Index: gcc/config/rs6000/aix43.h =================================================================== --- gcc/config/rs6000/aix43.h (revision 191811) +++ gcc/config/rs6000/aix43.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/darwin.opt =================================================================== --- gcc/config/rs6000/darwin.opt (revision 191811) +++ gcc/config/rs6000/darwin.opt (working copy) @@ -34,9 +34,9 @@ findirect-data Driver RejectNegative Alias(mfix-and-continue) m64 -Target RejectNegative Negative(m32) Mask(64BIT) +Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target RejectNegative Negative(m64) InverseMask(64BIT) +Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code Index: gcc/config/rs6000/rs6000-c.c =================================================================== --- gcc/config/rs6000/rs6000-c.c (revision 191811) +++ gcc/config/rs6000/rs6000-c.c (working copy) @@ -285,38 +285,42 @@ rs6000_define_or_undefine_macro (bool de have both the target flags and the builtin flags as arguments. */ void -rs6000_target_modify_macros (bool define_p, int flags, unsigned bu_mask) +rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, + HOST_WIDE_INT bu_mask) { if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) - fprintf (stderr, "rs6000_target_modify_macros (%s, 0x%x, 0x%x)\n", + fprintf (stderr, + "rs6000_target_modify_macros (%s, " + HOST_WIDE_INT_PRINT_HEX ", " + HOST_WIDE_INT_PRINT_HEX ")\n", (define_p) ? "define" : "undef", - (unsigned) flags, bu_mask); + flags, bu_mask); - /* target_flags based options. */ + /* rs6000_isa_flags based options. */ rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); - if ((flags & MASK_PPC_GPOPT) != 0) + if ((flags & OPTION_MASK_PPC_GPOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ"); - if ((flags & MASK_PPC_GFXOPT) != 0) + if ((flags & OPTION_MASK_PPC_GFXOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR"); - if ((flags & MASK_POWERPC64) != 0) + if ((flags & OPTION_MASK_POWERPC64) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"); - if ((flags & MASK_MFCRF) != 0) + if ((flags & OPTION_MASK_MFCRF) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4"); - if ((flags & MASK_POPCNTB) != 0) + if ((flags & OPTION_MASK_POPCNTB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5"); - if ((flags & MASK_FPRND) != 0) + if ((flags & OPTION_MASK_FPRND) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X"); - if ((flags & MASK_CMPB) != 0) + if ((flags & OPTION_MASK_CMPB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); - if ((flags & MASK_MFPGPR) != 0) + if ((flags & OPTION_MASK_MFPGPR) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X"); - if ((flags & MASK_POPCNTD) != 0) + if ((flags & OPTION_MASK_POPCNTD) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); - if ((flags & MASK_SOFT_FLOAT) != 0) + if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); - if ((flags & MASK_RECIP_PRECISION) != 0) + if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__"); - if ((flags & MASK_ALTIVEC) != 0) + if ((flags & OPTION_MASK_ALTIVEC) != 0) { const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__"; rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__"); @@ -326,7 +330,7 @@ rs6000_target_modify_macros (bool define if (!flag_iso) rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__"); } - if ((flags & MASK_VSX) != 0) + if ((flags & OPTION_MASK_VSX) != 0) rs6000_define_or_undefine_macro (define_p, "__VSX__"); /* options from the builtin masks. */ @@ -342,7 +346,7 @@ void rs6000_cpu_cpp_builtins (cpp_reader *pfile) { /* Define all of the common macros. */ - rs6000_target_modify_macros (true, target_flags, + rs6000_target_modify_macros (true, rs6000_isa_flags, rs6000_builtin_mask_calculate ()); if (TARGET_FRE) Index: gcc/config/rs6000/rs6000.opt =================================================================== --- gcc/config/rs6000/rs6000.opt (revision 191811) +++ gcc/config/rs6000/rs6000.opt (working copy) @@ -22,6 +22,17 @@ HeaderInclude config/rs6000/rs6000-opts.h +;; ISA flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags + +;; Miscellaneous flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags_explicit + ;; Current processor TargetVariable enum processor_type rs6000_cpu = PROCESSOR_PPC603 @@ -80,86 +91,82 @@ unsigned int rs6000_recip_control ;; Mask of what builtin functions are allowed TargetVariable -unsigned int rs6000_builtin_mask +HOST_WIDE_INT rs6000_builtin_mask ;; Debug flags TargetVariable unsigned int rs6000_debug -;; Save for target_flags_explicit -TargetSave -int rs6000_target_flags_explicit - ;; This option existed in the past, but now is always on. mpowerpc Target RejectNegative Undocumented Ignore mpowerpc64 -Target Report Mask(POWERPC64) +Target Report Mask(POWERPC64) Var(rs6000_isa_flags) Use PowerPC-64 instruction set mpowerpc-gpopt -Target Report Mask(PPC_GPOPT) Save +Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) Use PowerPC General Purpose group optional instructions mpowerpc-gfxopt -Target Report Mask(PPC_GFXOPT) Save +Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) Use PowerPC Graphics group optional instructions mmfcrf -Target Report Mask(MFCRF) Save +Target Report Mask(MFCRF) Var(rs6000_isa_flags) Use PowerPC V2.01 single field mfcr instruction mpopcntb -Target Report Mask(POPCNTB) Save +Target Report Mask(POPCNTB) Var(rs6000_isa_flags) Use PowerPC V2.02 popcntb instruction mfprnd -Target Report Mask(FPRND) Save +Target Report Mask(FPRND) Var(rs6000_isa_flags) Use PowerPC V2.02 floating point rounding instructions mcmpb -Target Report Mask(CMPB) Save +Target Report Mask(CMPB) Var(rs6000_isa_flags) Use PowerPC V2.05 compare bytes instruction mmfpgpr -Target Report Mask(MFPGPR) Save +Target Report Mask(MFPGPR) Var(rs6000_isa_flags) Use extended PowerPC V2.05 move floating point to/from GPR instructions maltivec -Target Report Mask(ALTIVEC) Save +Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) Use AltiVec instructions mhard-dfp -Target Report Mask(DFP) Save +Target Report Mask(DFP) Var(rs6000_isa_flags) Use decimal floating point instructions mmulhw -Target Report Mask(MULHW) Save +Target Report Mask(MULHW) Var(rs6000_isa_flags) Use 4xx half-word multiply instructions mdlmzb -Target Report Mask(DLMZB) Save +Target Report Mask(DLMZB) Var(rs6000_isa_flags) Use 4xx string-search dlmzb instruction mmultiple -Target Report Mask(MULTIPLE) Save +Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) Generate load/store multiple instructions mstring -Target Report Mask(STRING) Save +Target Report Mask(STRING) Var(rs6000_isa_flags) Generate string instructions for block moves msoft-float -Target Report RejectNegative Mask(SOFT_FLOAT) +Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) Do not use hardware floating point mhard-float -Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) +Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) Use hardware floating point mpopcntd -Target Report Mask(POPCNTD) Save +Target Report Mask(POPCNTD) Var(rs6000_isa_flags) Use PowerPC V2.06 popcntd instruction mfriz @@ -171,7 +178,7 @@ Target RejectNegative Joined Var(rs6000_ Vector library ABI to use mvsx -Target Report Mask(VSX) Save +Target Report Mask(VSX) Var(rs6000_isa_flags) Use vector/scalar (VSX) instructions mvsx-scalar-double @@ -211,11 +218,11 @@ Target Undocumented Report Var(TARGET_VE ; Explicitly control whether we vectorize the builtins or not. mno-update -Target Report RejectNegative Mask(NO_UPDATE) Save +Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) Do not generate load/store with update instructions mupdate -Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) +Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) Generate load/store with update instructions msingle-pic-base @@ -258,7 +265,7 @@ Target Report RejectNegative Joined Var( Generate software reciprocal divide and square root for better throughput. mrecip-precision -Target Report Mask(RECIP_PRECISION) Save +Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) Assume that the reciprocal estimate instructions provide more accuracy. mno-fp-in-toc @@ -285,7 +292,7 @@ Place symbol+offset constants in TOC ; This is at the cost of having 2 extra loads and one extra store per ; function, and one less allocable register. mminimal-toc -Target Report Mask(MINIMAL_TOC) +Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) Use only one TOC entry per procedure mfull-toc @@ -309,7 +316,7 @@ Target Report Var(rs6000_block_move_inli Specify how many bytes should be moved inline before calling out to memcpy/memmove misel -Target Report Mask(ISEL) Save +Target Report Mask(ISEL) Var(rs6000_isa_flags) Generate isel instructions misel=no Index: gcc/config/rs6000/linux64.h =================================================================== --- gcc/config/rs6000/linux64.h (revision 191811) +++ gcc/config/rs6000/linux64.h (working copy) @@ -81,7 +81,7 @@ extern int dot_symbols; -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "linux" @@ -103,14 +103,14 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ - if (target_flags & MASK_RELOCATABLE) \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error (INVALID_64BIT, "relocatable"); \ } \ - if (target_flags & MASK_EABI) \ + if (rs6000_isa_flags & OPTION_MASK_EABI) \ { \ - target_flags &= ~MASK_EABI; \ + rs6000_isa_flags &= ~OPTION_MASK_EABI; \ error (INVALID_64BIT, "eabi"); \ } \ if (TARGET_PROTOTYPE) \ @@ -118,12 +118,13 @@ extern int dot_symbols; target_prototype = 0; \ error (INVALID_64BIT, "prototype"); \ } \ - if ((target_flags & MASK_POWERPC64) == 0) \ + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ error ("-m64 requires a PowerPC64 cpu"); \ } \ - if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ + if ((rs6000_isa_flags_explicit \ + & OPTION_MASK_MINIMAL_TOC) != 0) \ { \ if (global_options_set.x_rs6000_current_cmodel \ && rs6000_current_cmodel != CMODEL_SMALL) \ @@ -213,20 +214,20 @@ extern int dot_symbols; #ifndef RS6000_BI_ARCH /* 64-bit PowerPC Linux is always big-endian. */ -#undef TARGET_LITTLE_ENDIAN -#define TARGET_LITTLE_ENDIAN 0 +#undef OPTION_LITTLE_ENDIAN +#define OPTION_LITTLE_ENDIAN 0 /* 64-bit PowerPC Linux always has a TOC. */ #undef TARGET_TOC #define TARGET_TOC 1 /* Some things from sysv4.h we don't do when 64 bit. */ -#undef TARGET_RELOCATABLE -#define TARGET_RELOCATABLE 0 -#undef TARGET_EABI -#define TARGET_EABI 0 -#undef TARGET_PROTOTYPE -#define TARGET_PROTOTYPE 0 +#undef OPTION_RELOCATABLE +#define OPTION_RELOCATABLE 0 +#undef OPTION_EABI +#define OPTION_EABI 0 +#undef OPTION_PROTOTYPE +#define OPTION_PROTOTYPE 0 #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP 0 Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 191811) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -213,7 +213,7 @@ static GTY(()) section *toc_section; struct builtin_description { - const unsigned int mask; + const HOST_WIDE_INT mask; const enum insn_code icode; const char *const name; const enum rs6000_builtins code; @@ -287,7 +287,7 @@ typedef rtx (*gen_2arg_fn_t) (rtx, rtx, /* Pointer to function (in rs6000-c.c) that can define or undefine target macros that have changed. Languages that don't support the preprocessor don't link in rs6000-c.c, so we can't call it directly. */ -void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned); +void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT); \f /* Target cpu costs. */ @@ -893,7 +893,7 @@ struct processor_costs ppca2_cost = { struct rs6000_builtin_info_type { const char *name; const enum insn_code icode; - const unsigned mask; + const HOST_WIDE_INT mask; const unsigned attr; }; @@ -1015,6 +1015,9 @@ bool (*rs6000_cannot_change_mode_class_p const int INSN_NOT_AVAILABLE = -1; +static void rs6000_print_isa_options (FILE *, int, const char *, + HOST_WIDE_INT); + /* Hash table stuff for keeping track of TOC entries. */ struct GTY(()) toc_hash_struct @@ -1115,7 +1118,8 @@ static const struct attribute_spec rs600 { NULL, 0, 0, false, false, false, NULL, false } }; \f -#ifndef MASK_STRICT_ALIGN +#ifndef OPTION_MASK_STRICT_ALIGN +#define OPTION_MASK_STRICT_ALIGN 0 #define MASK_STRICT_ALIGN 0 #endif #ifndef TARGET_PROFILE_KERNEL @@ -1458,53 +1462,12 @@ static const struct attribute_spec rs600 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok \f -/* Simplifications for entries below. */ - -enum { - POWERPC_7400_MASK = MASK_PPC_GFXOPT | MASK_ALTIVEC -}; - -/* Some OSs don't support saving the high part of 64-bit registers on context - switch. Other OSs don't support saving Altivec registers. On those OSs, we - don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants - either, the user must explicitly specify them and we won't interfere with - the user's specification. */ - -enum { - POWERPC_MASKS = (MASK_PPC_GPOPT | MASK_STRICT_ALIGN - | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC - | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW - | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP - | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE - | MASK_RECIP_PRECISION) -}; - -/* Masks for instructions set at various powerpc ISAs. */ -enum { - ISA_2_1_MASKS = MASK_MFCRF, - ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB), - ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND), - - /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add - ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, - fre, fsqrt, etc. were no longer documented as optional. Group masks by - server and embedded. */ - ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION - | MASK_PPC_GFXOPT | MASK_PPC_GPOPT), - ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP), - - /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but - altivec is a win so enable it. */ - ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD), - ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC - | MASK_VSX) -}; - +/* Processor table. */ struct rs6000_ptt { const char *const name; /* Canonical processor name. */ const enum processor_type processor; /* Processor type enum value. */ - const int target_enable; /* Target flags to enable. */ + const HOST_WIDE_INT target_enable; /* Target flags to enable. */ }; static struct rs6000_ptt const processor_target_table[] = @@ -1715,9 +1678,10 @@ rs6000_debug_reg_print (int first_regno, } } -#define DEBUG_FMT_D "%-32s= %d\n" -#define DEBUG_FMT_X "%-32s= 0x%x\n" -#define DEBUG_FMT_S "%-32s= %s\n" +#define DEBUG_FMT_ID "%-32s= " +#define DEBUG_FMT_D DEBUG_FMT_ID "%d\n" +#define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: " +#define DEBUG_FMT_S DEBUG_FMT_ID "%s\n" /* Print various interesting information with -mdebug=reg. */ static void @@ -1728,11 +1692,13 @@ rs6000_debug_reg_global (void) int m; char costly_num[20]; char nop_num[20]; + char flags_buffer[40]; const char *costly_str; const char *nop_str; const char *trace_str; const char *abi_str; const char *cmodel_str; + struct cl_target_option cl_opts; /* Map enum rs6000_vector to string. */ static const char *rs6000_debug_vector_unit[] = { @@ -1812,12 +1778,42 @@ rs6000_debug_reg_global (void) } if (rs6000_cpu_index >= 0) - fprintf (stderr, DEBUG_FMT_S, "cpu", - processor_target_table[rs6000_cpu_index].name); + { + const char *name = processor_target_table[rs6000_cpu_index].name; + HOST_WIDE_INT flags + = processor_target_table[rs6000_cpu_index].target_enable; + + sprintf (flags_buffer, "-mcpu=%s flags", name); + rs6000_print_isa_options (stderr, 0, flags_buffer, flags); + } + else + fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>"); if (rs6000_tune_index >= 0) - fprintf (stderr, DEBUG_FMT_S, "tune", - processor_target_table[rs6000_tune_index].name); + { + const char *name = processor_target_table[rs6000_tune_index].name; + HOST_WIDE_INT flags + = processor_target_table[rs6000_tune_index].target_enable; + + sprintf (flags_buffer, "-mtune=%s flags", name); + rs6000_print_isa_options (stderr, 0, flags_buffer, flags); + } + else + fprintf (stderr, DEBUG_FMT_S, "tune", "<none>"); + + cl_target_option_save (&cl_opts, &global_options); + rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags", rs6000_isa_flags); + + rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit", + rs6000_isa_flags_explicit); + + rs6000_print_isa_options (stderr, 0, "rs6000_builtin_mask", + rs6000_builtin_mask); + + rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT); + + fprintf (stderr, DEBUG_FMT_S, "--with-cpu default", + OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>"); switch (rs6000_sched_costly_dep) { @@ -1935,7 +1931,15 @@ rs6000_debug_reg_global (void) if (rs6000_float_gprs) fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true"); + if (TARGET_LINK_STACK) + fprintf (stderr, DEBUG_FMT_S, "link_stack", "true"); + + fprintf (stderr, DEBUG_FMT_S, "plt-format", + TARGET_SECURE_PLT ? "secure" : "bss"); + fprintf (stderr, DEBUG_FMT_S, "struct-return", + aix_struct_return ? "aix" : "sysv"); fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]); + fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]); fprintf (stderr, DEBUG_FMT_S, "align_branch", tf[!!rs6000_align_branch_targets]); fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size); @@ -1947,7 +1951,6 @@ rs6000_debug_reg_global (void) (int)END_BUILTINS); fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins", (int)RS6000_BUILTIN_COUNT); - fprintf (stderr, DEBUG_FMT_X, "Builtin mask", rs6000_builtin_mask); } /* Initialize the various global tables that are based on register size. */ @@ -2311,21 +2314,21 @@ darwin_rs6000_override_options (void) if (TARGET_64BIT && ! TARGET_POWERPC64) { - target_flags |= MASK_POWERPC64; + rs6000_isa_flags |= OPTION_MASK_POWERPC64; warning (0, "-m64 requires PowerPC64 architecture, enabling"); } if (flag_mkernel) { rs6000_default_long_calls = 1; - target_flags |= MASK_SOFT_FLOAT; + rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; } /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes Altivec. */ if (!flag_mkernel && !flag_apple_kext && TARGET_64BIT - && ! (target_flags_explicit & MASK_ALTIVEC)) - target_flags |= MASK_ALTIVEC; + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)) + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; /* Unless the user (not the configurer) has explicitly overridden it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to @@ -2333,10 +2336,10 @@ darwin_rs6000_override_options (void) if (!flag_mkernel && !flag_apple_kext && strverscmp (darwin_macosx_version_min, "10.5") >= 0 - && ! (target_flags_explicit & MASK_ALTIVEC) + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC) && ! global_options_set.x_rs6000_cpu_index) { - target_flags |= MASK_ALTIVEC; + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; } } #endif @@ -2353,7 +2356,7 @@ darwin_rs6000_override_options (void) bits, and some options like SPE and PAIRED are no longer in target_flags. */ -unsigned +HOST_WIDE_INT rs6000_builtin_mask_calculate (void) { return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) @@ -2380,7 +2383,7 @@ rs6000_option_override_internal (bool gl /* The default cpu requested at configure time, if any. */ const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT; - int set_masks; + HOST_WIDE_INT set_masks; int cpu_index; int tune_index; struct cl_target_option *main_target_opt @@ -2417,18 +2420,24 @@ rs6000_option_override_internal (bool gl rs6000_pointer_size = 32; } - set_masks = POWERPC_MASKS | MASK_SOFT_FLOAT; + /* Some OSs don't support saving the high part of 64-bit registers on context + switch. Other OSs don't support saving Altivec registers. On those OSs, + we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings; + if the user wants either, the user must explicitly specify them and we + won't interfere with the user's specification. */ + + set_masks = POWERPC_MASKS; #ifdef OS_MISSING_POWERPC64 if (OS_MISSING_POWERPC64) - set_masks &= ~MASK_POWERPC64; + set_masks &= ~OPTION_MASK_POWERPC64; #endif #ifdef OS_MISSING_ALTIVEC if (OS_MISSING_ALTIVEC) - set_masks &= ~MASK_ALTIVEC; + set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX); #endif /* Don't override by the processor default if given explicitly. */ - set_masks &= ~target_flags_explicit; + set_masks &= ~rs6000_isa_flags_explicit; /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed the cpu in a target attribute or pragma, but did not specify a tuning @@ -2457,9 +2466,14 @@ rs6000_option_override_internal (bool gl gcc_assert (cpu_index >= 0); - target_flags &= ~set_masks; - target_flags |= (processor_target_table[cpu_index].target_enable - & set_masks); + rs6000_isa_flags &= ~set_masks; + rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable + & set_masks); + + /* If no -mcpu=<xxx>, inherit any default options that were cleared via + POWERPC_MASKS. */ + if (!have_cpu) + rs6000_isa_flags |= (TARGET_DEFAULT & ~rs6000_isa_flags_explicit); if (rs6000_tune_index >= 0) tune_index = rs6000_tune_index; @@ -2544,7 +2558,8 @@ rs6000_option_override_internal (bool gl use instructions that would be microcoded on the Cell, use the load/store multiple and string instructions. */ if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode) - target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); + rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE + | OPTION_MASK_STRING); /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu is a 750, because the hardware doesn't support the @@ -2556,15 +2571,15 @@ rs6000_option_override_internal (bool gl { if (TARGET_MULTIPLE) { - target_flags &= ~MASK_MULTIPLE; - if ((target_flags_explicit & MASK_MULTIPLE) != 0) + rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE; + if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0) warning (0, "-mmultiple is not supported on little endian systems"); } if (TARGET_STRING) { - target_flags &= ~MASK_STRING; - if ((target_flags_explicit & MASK_STRING) != 0) + rs6000_isa_flags &= ~OPTION_MASK_STRING; + if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0) warning (0, "-mstring is not supported on little endian systems"); } } @@ -2576,10 +2591,10 @@ rs6000_option_override_internal (bool gl if (!TARGET_HARD_FLOAT || !TARGET_FPRS || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx requires hardware floating point"); else - target_flags &= ~ MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; } else if (TARGET_PAIRED_FLOAT) msg = N_("-mvsx and -mpaired are incompatible"); @@ -2590,9 +2605,10 @@ rs6000_option_override_internal (bool gl msg = N_("-mvsx used with little endian code"); else if (TARGET_AVOID_XFORM > 0) msg = N_("-mvsx needs indexed addressing"); - else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC)) + else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit + & OPTION_MASK_ALTIVEC)) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx and -mno-altivec are incompatible"); else msg = N_("-mno-altivec disables vsx"); @@ -2601,27 +2617,27 @@ rs6000_option_override_internal (bool gl if (msg) { warning (0, msg); - target_flags &= ~ MASK_VSX; - target_flags_explicit |= MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; + rs6000_isa_flags_explicit |= OPTION_MASK_VSX; } } /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-<option> to disable the code. */ if (TARGET_VSX) - target_flags |= (ISA_2_6_MASKS_SERVER & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit); else if (TARGET_POPCNTD) - target_flags |= (ISA_2_6_MASKS_EMBEDDED & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit); else if (TARGET_DFP) - target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~rs6000_isa_flags_explicit); else if (TARGET_CMPB) - target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit); else if (TARGET_FPRND) - target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_4_MASKS & ~rs6000_isa_flags_explicit); else if (TARGET_POPCNTB) - target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_2_MASKS & ~rs6000_isa_flags_explicit); else if (TARGET_ALTIVEC) - target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit); + rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit); /* E500mc does "better" if we inline more aggressively. Respect the user's opinion, though. */ @@ -2700,7 +2716,8 @@ rs6000_option_override_internal (bool gl unless the altivec ABI was set. This is set by default for 64-bit, but not for 32-bit. */ if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi) - target_flags &= ~((MASK_VSX | MASK_ALTIVEC) & ~target_flags_explicit); + rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC) + & ~rs6000_isa_flags_explicit); /* Enable Altivec ABI for AIX -maltivec. */ if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX)) @@ -2782,14 +2799,14 @@ rs6000_option_override_internal (bool gl rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE; rs6000_double_float = TARGET_E500_DOUBLE; - target_flags &= ~MASK_STRING; + rs6000_isa_flags &= ~OPTION_MASK_STRING; break; default: - if (have_cpu && !(target_flags_explicit & MASK_ISEL)) - target_flags &= ~MASK_ISEL; + if (have_cpu && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL)) + rs6000_isa_flags &= ~OPTION_MASK_ISEL; break; } @@ -3166,11 +3183,12 @@ rs6000_option_override_internal (bool gl target_flags. */ rs6000_builtin_mask = rs6000_builtin_mask_calculate (); if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) - fprintf (stderr, "new builtin mask = 0x%x%s%s%s%s\n", rs6000_builtin_mask, - (rs6000_builtin_mask & RS6000_BTM_ALTIVEC) ? ", altivec" : "", - (rs6000_builtin_mask & RS6000_BTM_VSX) ? ", vsx" : "", - (rs6000_builtin_mask & RS6000_BTM_PAIRED) ? ", paired" : "", - (rs6000_builtin_mask & RS6000_BTM_SPE) ? ", spe" : ""); + { + fprintf (stderr, + "new builtin mask = " HOST_WIDE_INT_PRINT_HEX ", ", + rs6000_builtin_mask); + rs6000_print_isa_options (stderr, 0, NULL, rs6000_builtin_mask); + } /* Initialize all of the registers. */ rs6000_init_hard_regno_mode_ok (global_init_p); @@ -10432,7 +10450,7 @@ altivec_expand_dst_builtin (tree exp, rt bool *expandedp) { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl); tree arg0, arg1, arg2; enum machine_mode mode0, mode1; rtx pat, op0, op1, op2; @@ -10834,7 +10852,7 @@ static rtx paired_expand_builtin (tree exp, rtx target, bool * expandedp) { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl); const struct builtin_description *d; size_t i; @@ -10899,7 +10917,7 @@ spe_expand_builtin (tree exp, rtx target { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); tree arg1, arg0; - unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl); enum insn_code icode; enum machine_mode tmode, mode0; rtx pat, op0; @@ -11264,7 +11282,7 @@ rs6000_invalid_builtin (enum rs6000_buil { size_t uns_fncode = (size_t)fncode; const char *name = rs6000_builtin_info[uns_fncode].name; - unsigned fnmask = rs6000_builtin_info[uns_fncode].mask; + HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask; gcc_assert (name != NULL); if ((fnmask & RS6000_BTM_CELL) != 0) @@ -11301,7 +11319,7 @@ rs6000_expand_builtin (tree exp, rtx tar size_t i; rtx ret; bool success; - unsigned mask = rs6000_builtin_info[uns_fcode].mask; + HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask; bool func_valid_p = ((rs6000_builtin_mask & mask) == mask); if (TARGET_DEBUG_BUILTIN) @@ -11684,7 +11702,7 @@ rs6000_init_builtins (void) static tree rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) { - unsigned fnmask; + HOST_WIDE_INT fnmask; if (code >= RS6000_BUILTIN_COUNT) return error_mark_node; @@ -12556,7 +12574,7 @@ rs6000_common_init_builtins (void) tree v2si_ftype_qi = NULL_TREE; tree v2si_ftype_v2si_qi = NULL_TREE; tree v2si_ftype_int_qi = NULL_TREE; - unsigned builtin_mask = rs6000_builtin_mask; + HOST_WIDE_INT builtin_mask = rs6000_builtin_mask; if (!TARGET_PAIRED_FLOAT) { @@ -12578,7 +12596,7 @@ rs6000_common_init_builtins (void) for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) { tree type; - unsigned mask = d->mask; + HOST_WIDE_INT mask = d->mask; if ((mask & builtin_mask) != mask) { @@ -12619,7 +12637,7 @@ rs6000_common_init_builtins (void) { enum machine_mode mode0, mode1, mode2; tree type; - unsigned mask = d->mask; + HOST_WIDE_INT mask = d->mask; if ((mask & builtin_mask) != mask) { @@ -12682,7 +12700,7 @@ rs6000_common_init_builtins (void) { enum machine_mode mode0, mode1; tree type; - unsigned mask = d->mask; + HOST_WIDE_INT mask = d->mask; if ((mask & builtin_mask) != mask) { @@ -25246,7 +25264,7 @@ rs6000_darwin_file_start (void) { const char *arg; const char *name; - int if_set; + HOST_WIDE_INT if_set; } mapping[] = { { "ppc64", "ppc64", MASK_64BIT }, { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, @@ -25285,7 +25303,7 @@ rs6000_darwin_file_start (void) i = 0; while (mapping[i].arg != NULL && strcmp (mapping[i].arg, cpu_id) != 0 - && (mapping[i].if_set & target_flags) == 0) + && (mapping[i].if_set & rs6000_isa_flags) == 0) i++; fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name); @@ -27379,55 +27397,55 @@ rs6000_final_prescan_insn (rtx insn, rtx struct rs6000_opt_mask { const char *name; /* option name */ - int mask; /* mask to set */ + HOST_WIDE_INT mask; /* mask to set */ bool invert; /* invert sense of mask */ bool valid_target; /* option is a target option */ }; static struct rs6000_opt_mask const rs6000_opt_masks[] = { - { "altivec", MASK_ALTIVEC, false, true }, - { "cmpb", MASK_CMPB, false, true }, - { "dlmzb", MASK_DLMZB, false, true }, - { "fprnd", MASK_FPRND, false, true }, - { "hard-dfp", MASK_DFP, false, true }, - { "isel", MASK_ISEL, false, true }, - { "mfcrf", MASK_MFCRF, false, true }, - { "mfpgpr", MASK_MFPGPR, false, true }, - { "mulhw", MASK_MULHW, false, true }, - { "multiple", MASK_MULTIPLE, false, true }, - { "update", MASK_NO_UPDATE, true , true }, - { "popcntb", MASK_POPCNTB, false, true }, - { "popcntd", MASK_POPCNTD, false, true }, - { "powerpc-gfxopt", MASK_PPC_GFXOPT, false, true }, - { "powerpc-gpopt", MASK_PPC_GPOPT, false, true }, - { "recip-precision", MASK_RECIP_PRECISION, false, true }, - { "string", MASK_STRING, false, true }, - { "vsx", MASK_VSX, false, true }, -#ifdef MASK_64BIT + { "altivec", OPTION_MASK_ALTIVEC, false, true }, + { "cmpb", OPTION_MASK_CMPB, false, true }, + { "dlmzb", OPTION_MASK_DLMZB, false, true }, + { "fprnd", OPTION_MASK_FPRND, false, true }, + { "hard-dfp", OPTION_MASK_DFP, false, true }, + { "isel", OPTION_MASK_ISEL, false, true }, + { "mfcrf", OPTION_MASK_MFCRF, false, true }, + { "mfpgpr", OPTION_MASK_MFPGPR, false, true }, + { "mulhw", OPTION_MASK_MULHW, false, true }, + { "multiple", OPTION_MASK_MULTIPLE, false, true }, + { "update", OPTION_MASK_NO_UPDATE, true , true }, + { "popcntb", OPTION_MASK_POPCNTB, false, true }, + { "popcntd", OPTION_MASK_POPCNTD, false, true }, + { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true }, + { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true }, + { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true }, + { "string", OPTION_MASK_STRING, false, true }, + { "vsx", OPTION_MASK_VSX, false, true }, +#ifdef OPTION_MASK_64BIT #if TARGET_AIX_OS - { "aix64", MASK_64BIT, false, false }, - { "aix32", MASK_64BIT, true, false }, + { "aix64", OPTION_MASK_64BIT, false, false }, + { "aix32", OPTION_MASK_64BIT, true, false }, #else - { "64", MASK_64BIT, false, false }, - { "32", MASK_64BIT, true, false }, + { "64", OPTION_MASK_64BIT, false, false }, + { "32", OPTION_MASK_64BIT, true, false }, #endif #endif -#ifdef MASK_EABI - { "eabi", MASK_EABI, false, false }, +#ifdef OPTION_MASK_EABI + { "eabi", OPTION_MASK_EABI, false, false }, #endif -#ifdef MASK_LITTLE_ENDIAN - { "little", MASK_LITTLE_ENDIAN, false, false }, - { "big", MASK_LITTLE_ENDIAN, true, false }, +#ifdef OPTION_MASK_LITTLE_ENDIAN + { "little", OPTION_MASK_LITTLE_ENDIAN, false, false }, + { "big", OPTION_MASK_LITTLE_ENDIAN, true, false }, #endif -#ifdef MASK_RELOCATABLE - { "relocatable", MASK_RELOCATABLE, false, false }, +#ifdef OPTION_MASK_RELOCATABLE + { "relocatable", OPTION_MASK_RELOCATABLE, false, false }, #endif -#ifdef MASK_STRICT_ALIGN - { "strict-align", MASK_STRICT_ALIGN, false, false }, +#ifdef OPTION_MASK_STRICT_ALIGN + { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false }, #endif - { "soft-float", MASK_SOFT_FLOAT, false, false }, - { "string", MASK_STRING, false, false }, + { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false }, + { "string", OPTION_MASK_STRING, false, false }, }; /* Builtin mask mapping for printing the flags. */ @@ -27531,27 +27549,27 @@ rs6000_inner_target_options (tree args, for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++) if (strcmp (r, rs6000_opt_masks[i].name) == 0) { - int mask = rs6000_opt_masks[i].mask; + HOST_WIDE_INT mask = rs6000_opt_masks[i].mask; if (!rs6000_opt_masks[i].valid_target) not_valid_p = true; else { error_p = false; - target_flags_explicit |= mask; + rs6000_isa_flags_explicit |= mask; /* VSX needs altivec, so -mvsx automagically sets altivec. */ - if (mask == MASK_VSX && !invert) - mask |= MASK_ALTIVEC; + if (mask == OPTION_MASK_VSX && !invert) + mask |= OPTION_MASK_ALTIVEC; if (rs6000_opt_masks[i].invert) invert = !invert; if (invert) - target_flags &= ~mask; + rs6000_isa_flags &= ~mask; else - target_flags |= mask; + rs6000_isa_flags |= mask; } break; } @@ -27755,8 +27773,8 @@ rs6000_pragma_target_parse (tree args, t tree prev_tree = build_target_option_node (); tree cur_tree; struct cl_target_option *prev_opt, *cur_opt; - unsigned prev_bumask, cur_bumask, diff_bumask; - int prev_flags, cur_flags, diff_flags; + HOST_WIDE_INT prev_flags, cur_flags, diff_flags; + HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask; if (TARGET_DEBUG_TARGET) { @@ -27806,14 +27824,14 @@ rs6000_pragma_target_parse (tree args, t { prev_opt = TREE_TARGET_OPTION (prev_tree); prev_bumask = prev_opt->x_rs6000_builtin_mask; - prev_flags = prev_opt->x_target_flags; + prev_flags = prev_opt->x_rs6000_isa_flags; cur_opt = TREE_TARGET_OPTION (cur_tree); - cur_flags = cur_opt->x_target_flags; + cur_flags = cur_opt->x_rs6000_isa_flags; cur_bumask = cur_opt->x_rs6000_builtin_mask; diff_bumask = (prev_bumask ^ cur_bumask); - diff_flags = (prev_flags ^ cur_flags); + diff_flags = (prev_flags ^ cur_flags); if ((diff_flags != 0) || (diff_bumask != 0)) { @@ -27916,7 +27934,8 @@ rs6000_set_current_function (tree fndecl static void rs6000_function_specific_save (struct cl_target_option *ptr) { - ptr->rs6000_target_flags_explicit = target_flags_explicit; + ptr->x_rs6000_isa_flags = rs6000_isa_flags; + ptr->x_rs6000_isa_flags_explicit = rs6000_isa_flags_explicit; } /* Restore the current options */ @@ -27924,47 +27943,91 @@ rs6000_function_specific_save (struct cl static void rs6000_function_specific_restore (struct cl_target_option *ptr) { - target_flags_explicit = ptr->rs6000_target_flags_explicit; + rs6000_isa_flags = ptr->x_rs6000_isa_flags; + rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit; (void) rs6000_option_override_internal (false); } -/* Print the current options */ +/* Helper function to print the current isa or misc options on a line. */ static void -rs6000_function_specific_print (FILE *file, int indent, - struct cl_target_option *ptr) +rs6000_print_isa_or_misc_options (FILE *file, + int indent, + const char *string, + HOST_WIDE_INT flags, + const struct rs6000_opt_mask *opts, + size_t num_elements) { size_t i; - int flags = ptr->x_target_flags; - unsigned bu_mask = ptr->x_rs6000_builtin_mask; + size_t start_column = 0; + size_t cur_column; + size_t max_column = 76; + const char *comma = ""; + const char *nl = "\n"; - /* Print the various mask options. */ - for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++) - if ((flags & rs6000_opt_masks[i].mask) != 0) - { - flags &= ~ rs6000_opt_masks[i].mask; - fprintf (file, "%*s-m%s%s\n", indent, "", - rs6000_opt_masks[i].invert ? "no-" : "", - rs6000_opt_masks[i].name); - } + if (indent) + start_column += fprintf (file, "%*s", indent, ""); - /* Print the various options that are variables. */ - for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++) + if (!flags) { - size_t j = rs6000_opt_vars[i].target_offset; - if (((signed char *) ptr)[j]) - fprintf (file, "%*s-m%s\n", indent, "", - rs6000_opt_vars[i].name); + fprintf (stderr, DEBUG_FMT_S, string, "<none>"); + return; } - /* Print the various builtin flags. */ - fprintf (file, "%*sbuiltin mask = 0x%x\n", indent, "", bu_mask); - for (i = 0; i < ARRAY_SIZE (rs6000_builtin_mask_names); i++) - if ((bu_mask & rs6000_builtin_mask_names[i].mask) != 0) - { - fprintf (file, "%*s%s builtins supported\n", indent, "", - rs6000_builtin_mask_names[i].name); - } + start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags); + + /* Print the various mask options. */ + cur_column = start_column; + for (i = 0; i < num_elements; i++) + { + if ((flags & opts[i].mask) != 0) + { + const char *no_str = rs6000_opt_masks[i].invert ? "no-" : ""; + size_t len = (strlen (comma) + + (sizeof ("-m") - 1) + + strlen (no_str) + + strlen (rs6000_opt_masks[i].name)); + + cur_column += len; + if (cur_column > max_column) + { + fprintf (stderr, ", \\\n%*s", (int)start_column, ""); + cur_column = start_column + len; + comma = ""; + nl = "\n\n"; + } + + fprintf (file, "%s-m%s%s", comma, no_str, rs6000_opt_masks[i].name); + flags &= ~ opts[i].mask; + comma = ", "; + } + } + + fputs (nl, file); +} + +/* Helper function to print the current isa options on a line. */ + +static void +rs6000_print_isa_options (FILE *file, int indent, const char *string, + HOST_WIDE_INT flags) +{ + rs6000_print_isa_or_misc_options (file, indent, string, flags, + &rs6000_opt_masks[0], + ARRAY_SIZE (rs6000_opt_masks)); +} + +/* Print the current options */ + +static void +rs6000_function_specific_print (FILE *file, int indent, + struct cl_target_option *ptr) +{ + rs6000_print_isa_options (file, indent, "Isa options set", + ptr->x_rs6000_isa_flags); + + rs6000_print_isa_options (file, indent, "Isa options explicit", + ptr->x_rs6000_isa_flags_explicit); } \f @@ -27994,8 +28057,8 @@ rs6000_can_inline_p (tree caller, tree c /* Callee's options should a subset of the caller's, i.e. a vsx function can inline an altivec function but a non-vsx function can't inline a vsx function. */ - if ((caller_opts->x_target_flags & callee_opts->x_target_flags) - == callee_opts->x_target_flags) + if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags) + == callee_opts->x_rs6000_isa_flags) ret = true; } Index: gcc/config/rs6000/aix52.h =================================================================== --- gcc/config/rs6000/aix52.h (revision 191811) +++ gcc/config/rs6000/aix52.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 191811) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -218,55 +218,55 @@ extern const char *host_detect_local_cpu optional field operand for mfcr. */ #ifndef HAVE_AS_MFCRF -#undef TARGET_MFCRF -#define TARGET_MFCRF 0 +#undef OPTION_MFCRF +#define OPTION_MFCRF 0 #endif /* Define TARGET_POPCNTB if the target assembler does not support the popcount byte instruction. */ #ifndef HAVE_AS_POPCNTB -#undef TARGET_POPCNTB -#define TARGET_POPCNTB 0 +#undef OPTION_POPCNTB +#define OPTION_POPCNTB 0 #endif /* Define TARGET_FPRND if the target assembler does not support the fp rounding instructions. */ #ifndef HAVE_AS_FPRND -#undef TARGET_FPRND -#define TARGET_FPRND 0 +#undef OPTION_FPRND +#define OPTION_FPRND 0 #endif /* Define TARGET_CMPB if the target assembler does not support the cmpb instruction. */ #ifndef HAVE_AS_CMPB -#undef TARGET_CMPB -#define TARGET_CMPB 0 +#undef OPTION_CMPB +#define OPTION_CMPB 0 #endif /* Define TARGET_MFPGPR if the target assembler does not support the mffpr and mftgpr instructions. */ #ifndef HAVE_AS_MFPGPR -#undef TARGET_MFPGPR -#define TARGET_MFPGPR 0 +#undef OPTION_MFPGPR +#define OPTION_MFPGPR 0 #endif /* Define TARGET_DFP if the target assembler does not support decimal floating point instructions. */ #ifndef HAVE_AS_DFP -#undef TARGET_DFP -#define TARGET_DFP 0 +#undef OPTION_DFP +#define OPTION_DFP 0 #endif /* Define TARGET_POPCNTD if the target assembler does not support the popcount word and double word instructions. */ #ifndef HAVE_AS_POPCNTD -#undef TARGET_POPCNTD -#define TARGET_POPCNTD 0 +#undef OPTION_POPCNTD +#define OPTION_POPCNTD 0 #endif /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If @@ -465,6 +465,93 @@ extern int rs6000_vector_align[]; #define TARGET_FCTIDUZ TARGET_POPCNTD #define TARGET_FCTIWUZ TARGET_POPCNTD +/* Map OPTION_<xxx> back into TARGET_<xxx> options in rs6000_isa_flags. */ +#define TARGET_ALTIVEC OPTION_ALTIVEC +#define TARGET_CMPB OPTION_CMPB +#define TARGET_DFP OPTION_DFP +#define TARGET_DLMZB OPTION_DLMZB +#define TARGET_EABI OPTION_EABI +#define TARGET_FPRND OPTION_FPRND +#define TARGET_HARD_FLOAT OPTION_HARD_FLOAT +#define TARGET_ISEL OPTION_ISEL +#define TARGET_MFCRF OPTION_MFCRF +#define TARGET_MFPGPR OPTION_MFPGPR +#define TARGET_MULHW OPTION_MULHW +#define TARGET_MULTIPLE OPTION_MULTIPLE +#define TARGET_NO_UPDATE OPTION_NO_UPDATE +#define TARGET_POPCNTB OPTION_POPCNTB +#define TARGET_POPCNTD OPTION_POPCNTD +#define TARGET_PPC_GFXOPT OPTION_PPC_GFXOPT +#define TARGET_PPC_GPOPT OPTION_PPC_GPOPT +#define TARGET_RECIP_PRECISION OPTION_RECIP_PRECISION +#define TARGET_SOFT_FLOAT OPTION_SOFT_FLOAT +#define TARGET_STRICT_ALIGN OPTION_STRICT_ALIGN +#define TARGET_STRING OPTION_STRING +#define TARGET_UPDATE OPTION_UPDATE +#define TARGET_VSX OPTION_VSX + +#define MASK_ALTIVEC OPTION_MASK_ALTIVEC +#define MASK_CMPB OPTION_MASK_CMPB +#define MASK_DFP OPTION_MASK_DFP +#define MASK_DLMZB OPTION_MASK_DLMZB +#define MASK_EABI OPTION_MASK_EABI +#define MASK_FPRND OPTION_MASK_FPRND +#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT +#define MASK_ISEL OPTION_MASK_ISEL +#define MASK_MFCRF OPTION_MASK_MFCRF +#define MASK_MFPGPR OPTION_MASK_MFPGPR +#define MASK_MULHW OPTION_MASK_MULHW +#define MASK_MULTIPLE OPTION_MASK_MULTIPLE +#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE +#define MASK_POPCNTB OPTION_MASK_POPCNTB +#define MASK_POPCNTD OPTION_MASK_POPCNTD +#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT +#define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT +#define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION +#define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT +#define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN +#define MASK_STRING OPTION_MASK_STRING +#define MASK_UPDATE OPTION_MASK_UPDATE +#define MASK_VSX OPTION_MASK_VSX + +#ifndef IN_LIBGCC2 +#define TARGET_POWERPC64 OPTION_POWERPC64 +#define MASK_POWERPC64 OPTION_MASK_POWERPC64 +#endif + +#ifdef OPTION_64BIT +#define TARGET_64BIT OPTION_64BIT +#define MASK_64BIT OPTION_MASK_64BIT +#endif + +#ifdef OPTION_RELOCATABLE +#define TARGET_RELOCATABLE OPTION_RELOCATABLE +#define MASK_RELOCATABLE OPTION_MASK_RELOCATABLE +#endif + +#ifdef OPTION_LITTLE_ENDIAN +#define TARGET_LITTLE_ENDIAN OPTION_LITTLE_ENDIAN +#define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN +#endif + +#ifdef OPTION_MINIMAL_TOC +#define TARGET_MINIMAL_TOC OPTION_MINIMAL_TOC +#define MASK_MINIMAL_TOC OPTION_MASK_MINIMAL_TOC +#endif + +#ifdef OPTION_REGNAMES +#define TARGET_REGNAMES OPTION_REGNAMES +#define MASK_REGNAMES OPTION_MASK_REGNAMES +#endif + +#ifdef OPTION_PROTOTYPE +#define TARGET_PROTOTYPE OPTION_PROTOTYPE +#define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE +#endif + +/* Explicit ISA options that were set. */ +#define rs6000_isa_flags_explicit global_options_set.x_rs6000_isa_flags + /* For power systems, we want to enable Altivec and VSX builtins even if the user did not use -maltivec or -mvsx to allow the builtins to be used inside of #pragma GCC target or the target attribute to change the code level for a Index: gcc/config/rs6000/aix64.opt =================================================================== --- gcc/config/rs6000/aix64.opt (revision 191811) +++ gcc/config/rs6000/aix64.opt (working copy) @@ -20,11 +20,11 @@ ; <http://www.gnu.org/licenses/>. maix64 -Target Report RejectNegative Negative(maix32) Mask(64BIT) +Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags) Compile for 64-bit pointers maix32 -Target Report RejectNegative Negative(maix64) InverseMask(64BIT) +Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags) Compile for 32-bit pointers mpe Index: gcc/config/rs6000/freebsd64.h =================================================================== --- gcc/config/rs6000/freebsd64.h (revision 191811) +++ gcc/config/rs6000/freebsd64.h (working copy) @@ -57,7 +57,7 @@ extern int dot_symbols; -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "freebsd" @@ -79,14 +79,14 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ - if (target_flags & MASK_RELOCATABLE) \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error (INVALID_64BIT, "relocatable"); \ } \ - if (target_flags & MASK_EABI) \ + if (rs6000_isa_flags & OPTION_MASK_EABI) \ { \ - target_flags &= ~MASK_EABI; \ + rs6000_isa_flags &= ~OPTION_MASK_EABI; \ error (INVALID_64BIT, "eabi"); \ } \ if (TARGET_PROTOTYPE) \ @@ -94,12 +94,13 @@ extern int dot_symbols; target_prototype = 0; \ error (INVALID_64BIT, "prototype"); \ } \ - if ((target_flags & MASK_POWERPC64) == 0) \ + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ error ("-m64 requires a PowerPC64 cpu"); \ } \ - if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ + if ((rs6000_isa_flags_explicit \ + & OPTION_MASK_MINIMAL_TOC) != 0) \ { \ if (global_options_set.x_rs6000_current_cmodel \ && rs6000_current_cmodel != CMODEL_SMALL) \ Index: gcc/config/rs6000/aix61.h =================================================================== --- gcc/config/rs6000/aix61.h (revision 191811) +++ gcc/config/rs6000/aix61.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/sysv4.opt =================================================================== --- gcc/config/rs6000/sysv4.opt (revision 191811) +++ gcc/config/rs6000/sysv4.opt (working copy) @@ -49,12 +49,12 @@ Target Report Var(TARGET_NO_BITFIELD_TYP Align to the base type of the bit-field mstrict-align -Target Report Mask(STRICT_ALIGN) +Target Report Mask(STRICT_ALIGN) Var(rs6000_isa_flags) Align to the base type of the bit-field Don't assume that unaligned accesses are handled by the system mrelocatable -Target Report Mask(RELOCATABLE) +Target Report Mask(RELOCATABLE) Var(rs6000_isa_flags) Produce code relocatable at runtime mrelocatable-lib @@ -62,19 +62,19 @@ Target Produce code relocatable at runtime mlittle-endian -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code mlittle -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code mbig-endian -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code mbig -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code ;; FIXME: This does nothing. What should be done? @@ -96,7 +96,7 @@ Target RejectNegative no description yet meabi -Target Report Mask(EABI) +Target Report Mask(EABI) Var(rs6000_isa_flags) Use EABI mbit-word @@ -138,11 +138,11 @@ Target RejectNegative no description yet m64 -Target Report RejectNegative Negative(m32) Mask(64BIT) +Target Report RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target Report RejectNegative Negative(m64) InverseMask(64BIT) +Target Report RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code mnewlib Index: gcc/config/rs6000/rs6000-cpus.def =================================================================== --- gcc/config/rs6000/rs6000-cpus.def (revision 191811) +++ gcc/config/rs6000/rs6000-cpus.def (working copy) @@ -18,6 +18,57 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ +/* ISA masks. */ +#ifndef ISA_2_1_MASKS +#define ISA_2_1_MASKS OPTION_MASK_MFCRF +#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB) +#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND) + + /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add + ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, + fre, fsqrt, etc. were no longer documented as optional. Group masks by + server and embedded. */ +#define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT) + +#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP) + + /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but + altivec is a win so enable it. */ +#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD) +#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_ALTIVEC \ + | OPTION_MASK_VSX) + +#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) + +/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ +#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_DFP \ + | OPTION_MASK_DLMZB \ + | OPTION_MASK_FPRND \ + | OPTION_MASK_ISEL \ + | OPTION_MASK_MFCRF \ + | OPTION_MASK_MFPGPR \ + | OPTION_MASK_MULHW \ + | OPTION_MASK_NO_UPDATE \ + | OPTION_MASK_POPCNTB \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_POWERPC64 \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_SOFT_FLOAT \ + | OPTION_MASK_STRICT_ALIGN \ + | OPTION_MASK_VSX) + +#endif + /* This table occasionally claims that a processor does not support a particular feature even though it does, but the feature is slower than the alternative. Thus, it shouldn't be relied on as a complete description of Index: gcc/config/rs6000/freebsd.h =================================================================== --- gcc/config/rs6000/freebsd.h (revision 191811) +++ gcc/config/rs6000/freebsd.h (working copy) @@ -72,7 +72,7 @@ -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) Index: gcc/config/rs6000/option-defaults.h =================================================================== --- gcc/config/rs6000/option-defaults.h (revision 191811) +++ gcc/config/rs6000/option-defaults.h (working copy) @@ -35,11 +35,12 @@ #define OPT_32 "m32" #endif -#ifndef MASK_64BIT +#ifndef OPTION_MASK_64BIT +#define OPTION_MASK_64BIT 0 #define MASK_64BIT 0 #endif -#if TARGET_DEFAULT & MASK_64BIT +#if TARGET_DEFAULT & OPTION_MASK_64BIT #define OPT_ARCH64 "!"OPT_32 #define OPT_ARCH32 OPT_32 #else Index: gcc/config/rs6000/rs6000-protos.h =================================================================== --- gcc/config/rs6000/rs6000-protos.h (revision 191811) +++ gcc/config/rs6000/rs6000-protos.h (working copy) @@ -176,7 +176,7 @@ extern void rs6000_call_indirect_aix (rt extern void rs6000_aix_asm_output_dwarf_table_ref (char *); extern void get_ppc476_thunk_name (char name[32]); extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins); -extern unsigned rs6000_builtin_mask_calculate (void); +extern HOST_WIDE_INT rs6000_builtin_mask_calculate (void); /* Declare functions in rs6000-c.c */ @@ -185,8 +185,9 @@ extern void rs6000_cpu_cpp_builtins (str #ifdef TREE_CODE extern bool rs6000_pragma_target_parse (tree, tree); #endif -extern void rs6000_target_modify_macros (bool, int, unsigned); -extern void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned); +extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT, HOST_WIDE_INT); +extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, + HOST_WIDE_INT); #if TARGET_MACHO char *output_call (rtx, rtx *, int, int); Index: gcc/config/rs6000/aix51.h =================================================================== --- gcc/config/rs6000/aix51.h (revision 191811) +++ gcc/config/rs6000/aix51.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_POWERPC64 && ! TARGET_64BIT) \ Index: gcc/config/rs6000/sysv4.h =================================================================== --- gcc/config/rs6000/sysv4.h (revision 191811) +++ gcc/config/rs6000/sysv4.h (working copy) @@ -40,9 +40,10 @@ #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc" -#define TARGET_TOC ((target_flags & MASK_64BIT) \ - || ((target_flags & (MASK_RELOCATABLE \ - | MASK_MINIMAL_TOC)) \ +#define TARGET_TOC ((rs6000_isa_flags & OPTION_MASK_64BIT) \ + || ((rs6000_isa_flags \ + & (OPTION_MASK_RELOCATABLE \ + | OPTION_MASK_MINIMAL_TOC)) \ && flag_pic > 1) \ || DEFAULT_ABI == ABI_AIX) @@ -77,13 +78,13 @@ do { \ else if (!strcmp (rs6000_abi_name, "sysv-noeabi")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags &= ~ MASK_EABI; \ + rs6000_isa_flags &= ~ OPTION_MASK_EABI; \ } \ else if (!strcmp (rs6000_abi_name, "sysv-eabi") \ || !strcmp (rs6000_abi_name, "eabi")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags |= MASK_EABI; \ + rs6000_isa_flags |= OPTION_MASK_EABI; \ } \ else if (!strcmp (rs6000_abi_name, "aixdesc")) \ rs6000_current_abi = ABI_AIX; \ @@ -102,8 +103,8 @@ do { \ else if (!strcmp (rs6000_abi_name, "i960-old")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags |= (MASK_LITTLE_ENDIAN | MASK_EABI); \ - target_flags &= ~MASK_STRICT_ALIGN; \ + rs6000_isa_flags |= (OPTION_MASK_LITTLE_ENDIAN | OPTION_MASK_EABI); \ + rs6000_isa_flags &= ~OPTION_MASK_STRICT_ALIGN; \ TARGET_NO_BITFIELD_WORD = 1; \ } \ else \ @@ -168,13 +169,13 @@ do { \ \ if (TARGET_RELOCATABLE && !TARGET_MINIMAL_TOC) \ { \ - target_flags |= MASK_MINIMAL_TOC; \ + rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; \ error ("-mrelocatable and -mno-minimal-toc are incompatible"); \ } \ \ if (TARGET_RELOCATABLE && rs6000_current_abi == ABI_AIX) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error ("-mrelocatable and -mcall-%s are incompatible", \ rs6000_abi_name); \ } \ @@ -188,7 +189,7 @@ do { \ \ if (rs6000_current_abi == ABI_AIX && TARGET_LITTLE_ENDIAN) \ { \ - target_flags &= ~MASK_LITTLE_ENDIAN; \ + rs6000_isa_flags &= ~OPTION_MASK_LITTLE_ENDIAN; \ error ("-mcall-aixdesc must be big endian"); \ } \ \ @@ -200,7 +201,7 @@ do { \ /* Treat -fPIC the same as -mrelocatable. */ \ if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX) \ { \ - target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; \ + rs6000_isa_flags |= OPTION_MASK_RELOCATABLE | OPTION_MASK_MINIMAL_TOC; \ TARGET_NO_FP_IN_TOC = 1; \ } \ \ @@ -212,9 +213,9 @@ do { \ #ifndef RS6000_BI_ARCH # define SUBSUBTARGET_OVERRIDE_OPTIONS \ do { \ - if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) \ + if ((TARGET_DEFAULT ^ rs6000_isa_flags) & OPTION_MASK_64BIT) \ error ("-m%s not supported in this configuration", \ - (target_flags & MASK_64BIT) ? "64" : "32"); \ + (rs6000_isa_flags & OPTION_MASK_64BIT) ? "64" : "32"); \ } while (0) #endif @@ -500,8 +501,8 @@ extern int fixuplabelno; #define TARGET_OS_SYSV_CPP_BUILTINS() \ do \ { \ - if (target_flags_explicit \ - & MASK_RELOCATABLE) \ + if (rs6000_isa_flags_explicit \ + & OPTION_MASK_RELOCATABLE) \ builtin_define ("_RELOCATABLE"); \ } \ while (0) ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2b 2012-09-27 22:57 ` [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2b Michael Meissner @ 2012-10-04 1:42 ` David Edelsohn 2012-10-05 19:49 ` Michael Meissner 0 siblings, 1 reply; 13+ messages in thread From: David Edelsohn @ 2012-10-04 1:42 UTC (permalink / raw) To: Michael Meissner, gcc-patches, bergner, segher, iain, andreast-list @@ -1115,7 +1118,8 @@ static const struct attribute_spec rs600 { NULL, 0, 0, false, false, false, NULL, false } }; \f -#ifndef MASK_STRICT_ALIGN +#ifndef OPTION_MASK_STRICT_ALIGN +#define OPTION_MASK_STRICT_ALIGN 0 #define MASK_STRICT_ALIGN 0 #endif #ifndef TARGET_PROFILE_KERNEL Why does this fragment define OPTION_MASK_STRICT_ALIGN but does not remove definition of MASK_STRICT_ALIGN? Similarly for -#ifndef MASK_64BIT +#ifndef OPTION_MASK_64BIT +#define OPTION_MASK_64BIT 0 #define MASK_64BIT 0 #endif Why define both OPTION_MASK_64BIT and MASK_64BIT? And +/* Map OPTION_<xxx> back into TARGET_<xxx> options in rs6000_isa_flags. */ Why set up correspondence for all OPTION_xxx flags back to TARGET_xxx flags? Thanks, David ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2b 2012-10-04 1:42 ` David Edelsohn @ 2012-10-05 19:49 ` Michael Meissner 2012-10-16 16:13 ` [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f Michael Meissner 0 siblings, 1 reply; 13+ messages in thread From: Michael Meissner @ 2012-10-05 19:49 UTC (permalink / raw) To: David Edelsohn Cc: Michael Meissner, gcc-patches, bergner, segher, iain, andreast-list On Wed, Oct 03, 2012 at 09:42:05PM -0400, David Edelsohn wrote: > @@ -1115,7 +1118,8 @@ static const struct attribute_spec rs600 > { NULL, 0, 0, false, false, false, NULL, false } > }; > \f > -#ifndef MASK_STRICT_ALIGN > +#ifndef OPTION_MASK_STRICT_ALIGN > +#define OPTION_MASK_STRICT_ALIGN 0 > #define MASK_STRICT_ALIGN 0 > #endif > #ifndef TARGET_PROFILE_KERNEL > > Why does this fragment define OPTION_MASK_STRICT_ALIGN but does not > remove definition of MASK_STRICT_ALIGN? To amplify a little bit more, in the first patch, I completely removed all MASK_<xxx> names. However, this causes rs6000-cpus.def to be completely rewritten, and as you point out, that makes it very hard to verify that we are getting the same behavior. So in the second patch, I added mappings from OPTION_MASK_<xxx> to MASK_<xxx> so that rs6000-cpus.def would not change, but in the places where I changed target_flags to rs6000_isa_flags, I also changed to use the new names. These code fragments in rs6000.h are for the non-linux systems that don't use the sysv4.opt switches (which provides -mstrict-align, and hence defines MASK_STRICT_ALIGN or OPTION_MASK_STRICT_ALIGN in the new scheme). > Similarly for > > -#ifndef MASK_64BIT > +#ifndef OPTION_MASK_64BIT > +#define OPTION_MASK_64BIT 0 > #define MASK_64BIT 0 > #endif > > Why define both OPTION_MASK_64BIT and MASK_64BIT? This is for the embedded targets that don't handle the switches from sysv4.opt nor aix64.opt that define the respective -m64 and -maix64 options. -- Michael Meissner, IBM 5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA meissner@linux.vnet.ibm.com fax +1 (978) 399-6899 ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f 2012-10-05 19:49 ` Michael Meissner @ 2012-10-16 16:13 ` Michael Meissner 2012-10-17 19:42 ` David Edelsohn 0 siblings, 1 reply; 13+ messages in thread From: Michael Meissner @ 2012-10-16 16:13 UTC (permalink / raw) To: Michael Meissner, David Edelsohn, gcc-patches, bergner, segher, iain, andreast-list [-- Attachment #1: Type: text/plain, Size: 8047 bytes --] While Joseph and I are iterating on global changes to the options machinery, David had said patch #2b was ok for just powerpc specific changes. I took patch #2b, and adjusted it for the 3 patches I already checked in. I rewrote the ChangeLog entries to try and be more explicit in what was going on. This bootstraped and had no regressions. Is this ok to check in? 2012-10-16 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.opt (rs6000_isa_flags): New flag word to replace target_flags that gives us 63 possible switches. (x_rs6000_isa_flags): Save area for rs6000_isa_flags. (x_rs6000_isa_flags_explicit): Save area for rs6000_isa_flags_explicit. (rs6000_target_flags_explicit): Delete in favor of x_rs6000_isa_flags_explicit. (-mpowerpc64): Change all switches that used to be in target_flags to now be in rs6000_isa_flags. In using rs6000_isa_flags, the options machinary will generate names of the form OPITON_<xxx> instead of TARGET_<xxx> and OPTION_MASK_<xxx> instead of MASK_<xxx>. (-mpowerpc-gpopt): Likewise. (-mpowerpc-gfxopt): Likewise. (-mmfcrf): Likewise. (-mpopcntb): Likewise. (-mfprnd): Likewise. (-mcmpb): Likewise. (-mmfpgpr): Likewise. (-maltivec): Likewise. (-mhard-dfp): Likewise. (-mmulhw): Likewise. (-mdlmzb): Likewise. (-mmultiple): Likewise. (-mstring): Likewise. (-msoft-float): Likewise. (-mhard-float): Likewise. (-mpopcntd): Likewise. (-mvsx): Likewise. (-mno-update): Likewise. (-mupdate): Likewise. (-mrecip-precision): Likewise. (-mminimal-toc): Likewise. (-misel): Likewise. * config/rs6000/aix64.opt (-maix64): Likewise. (-maix32): Likewise. * config/rs6000/sysv4.opt (-mstrict-align): Likewise. (-mrelocatable): Likewise. (-mlittle-endian): Likewise. (-mlittle): Likewise. (-mbig-endian): LIkewise. (-mbig): Likewise. (-meabi): Likewise. (-m64): Likewise. (-m32): Likewise. * config/rs6000/darwin.opt (-m64): Likewise. (-m32): Likewise. * config/rs6000/rs6000-cpus.def (ISA_2_1_MASKS): Move the various masks used in rs6000.c here, since they are more logically in this file. Convert from being enums to just #defines, since the types of these masks is now HOST_WIDE_INT instead of int. For POWERPC_MASKS, add MASK_SOFT_FLOAT, since the only use case or'ed in the mask. Change the use in rs6000.c not to do the OR of MASK_SOFT_FLOAT. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. * config/rs6000/rs6000.c (ISA_2_1_MASKS): Likewise. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. (rs6000_option_override_internal): Likewise. * config/rs6000/rs6000.c (darwin_rs6000_override_options): Change all uses of target_flags to rs6000_isa_flags. Change all uses of target_flags_explicit to rs6000_isa_flags_explicit. Change the use of MASK_<xxx> to OPTION_MASK_<xxx> that options.h defines when we use a secondary flags word. Save/restore/print the new flags word when switching contexts with different target attributes. (rs6000_option_override_internal): Likewise. (rs6000_darwin_file_start): Likewise. (rs6000_opt_masks): Likewise. (rs6000_inner_target_options): Likewise. (rs6000_pragma_target_parse): Likewise. (rs6000_set_current_function): Likewise. (rs6000_function_specific_save): Likewise. (rs6000_function_specific_restore): Likewise. (rs6000_function_specific_print): Likewise. (rs6000_can_inline_p): Likewise. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. (rs6000_cpu_cpp_builtins): Likewise. * common/config/rs6000/rs6000-driver.c (rs6000_handle_option): Likewise. * config/rs6000/rs6000.h (OPTION_MFCRF): Replace TARGET_<xxx> with OPTION_<xxx> if the assembler doesn't support mfcrf, popcntb, fprnd, cmpb, mfpgpr, dfp, popcntd instructions. (TARGET_MFCRF): Likewise. (OPTION_POPCNTB): Likewise. (TARGET_POPCNTB): Likewise. (OPTION_FPRND): Likewise. (TARGET_FPRND): Likewise. (OPTION_CMPB): Likewise. (TARGET_CMPB): Likewise. (OPTION_HARD_DFP): Likewise. (TARGET_HARD_DFP): Likewise. (OPTION_POPCNTD): Likewise. (TARGET_POPCNTD): LIkewise. (TARGET_ALTIVEC): In moving to using Var(...) for all of the isa switches, the options machinery now uses OPTION_<xxx> instead of TARGET_<xxx> for whether the switch was set, OPTION_MASK_<xxx> instead of MASK_<xxx> for the mask name. Use #define to map the old name into the new name. For switches that are defined in aix64.opt, sysv4.opt, and darwin.opt, only do the definition if those switches were defined. (TARGET_CMPB): Likewise. (TARGET_DFP): Likewise. (TARGET_DLMZB): Likewise. (TARGET_EABI): Likewise. (TARGET_FPRND): Likewise. (TARGET_HARD_FLOAT): Likewise. (TARGET_ISEL): Likewise. (TARGET_MFCRF): Likewise. (TARGET_MFPGPR): Likewise. (TARGET_MULHW): Likewise. (TARGET_MULTIPLE): Likewise. (TARGET_NO_UPDATE): Likewise. (TARGET_POPCNTB): Likewise. (TARGET_POPCNTD): Likewise. (TARGET_PPC_GFXOPT): Likewise. (TARGET_PPC_GPOPT): Likewise. (TARGET_RECIP_PRECISION): Likewise. (TARGET_SOFT_FLOAT): Likewise. (TARGET_STRICT_ALIGN): Likewise. (TARGET_STRING): Likewise. (TARGET_UPDATE): Likewise. (TARGET_VSX): Likewise. (MASK_ALTIVEC): Likewise. (MASK_CMPB): Likewise. (MASK_DFP): Likewise. (MASK_DLMZB): Likewise. (MASK_EABI): Likewise. (MASK_FPRND): Likewise. (MASK_HARD_FLOAT): Likewise. (MASK_ISEL): Likewise. (MASK_MFCRF): Likewise. (MASK_MFPGPR): Likewise. (MASK_MULHW): Likewise. (MASK_MULTIPLE): Likewise. (MASK_NO_UPDATE): Likewise. (MASK_POPCNTB): Likewise. (MASK_POPCNTD): Likewise. (MASK_PPC_GFXOPT): Likewise. (MASK_PPC_GPOPT): Likewise. (MASK_RECIP_PRECISION): Likewise. (MASK_SOFT_FLOAT): Likewise. (MASK_STRICT_ALIGN): Likewise. (MASK_STRING): Likewise. (MASK_UPDATE): Likewise. (MASK_VSX): Likewise. (TARGET_POWERPC64): Likewise. (MASK_POWERPC64): Likewise. (TARGET_64BIT): Likewise. (MASK_64BIT): Likewise. (TARGET_RELOCATABLE): Likewise. (MASK_RELOCATABLE): Likewise. (TARGET_LITTLE_ENDIAN): Likewise. (MASK_LITTLE_ENDIAN): Likewise. (TARGET_MINIMAL_TOC): Likewise. (MASK_MINIMAL_TOC): Likewise. (TARGET_REGNAMES): Likewise. (MASK_REGNAMES): Likewise. (TARGET_PROTOTYPE): Likewise. (MASK_PROTOTYPE): Likewise. (rs6000_isa_flags_explicit): Define in terms of the global_options_set structure. * gcc/config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Change use of target_flags to rs6000_isa_flags, target_flags_explicit to rs6000_isa_flags_explicit, and MASK_<xxx> to OPTION_MASK_<xxx>. * gcc/config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/freebsd64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * gcc/config/rs6000/linux64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (OPTION_LITTLE_ENDIAN): Likewise. (OPTION_RELOCATABLE): Likewise. (OPTION_EABI): Likewise. (OPTION_PROTOTYPE): Likewise. * gcc/config/rs6000/linux.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * gcc/config/rs6000/option-defaults.h (OPTION_MASK_64BIT): Likewise. (OPT_ARCH32): Likewise. (OPT_ARCH64): Likewise. * gcc/config/rs6000/sysv4.h (TARGET_TOC): Likewise. (SUBTARGET_OVERRIDE_OPTIONS): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (TARGET_OS_SYSV_CPP_BUILTINS): Likewise. * config/rs6000/t-rs6000 (rs6000.o): Add rs6000-cpus.def as a dependency. -- Michael Meissner, IBM 5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA meissner@linux.vnet.ibm.com fax +1 (978) 399-6899 [-- Attachment #2: gcc-power7.patch364c --] [-- Type: text/plain, Size: 56139 bytes --] Index: gcc/config/rs6000/rs6000.opt =================================================================== --- gcc/config/rs6000/rs6000.opt (revision 192474) +++ gcc/config/rs6000/rs6000.opt (working copy) @@ -22,6 +22,17 @@ HeaderInclude config/rs6000/rs6000-opts.h +;; ISA flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags + +;; Miscellaneous flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags_explicit + ;; Current processor TargetVariable enum processor_type rs6000_cpu = PROCESSOR_PPC603 @@ -86,80 +97,76 @@ HOST_WIDE_INT rs6000_builtin_mask TargetVariable unsigned int rs6000_debug -;; Save for target_flags_explicit -TargetSave -int rs6000_target_flags_explicit - ;; This option existed in the past, but now is always on. mpowerpc Target RejectNegative Undocumented Ignore mpowerpc64 -Target Report Mask(POWERPC64) +Target Report Mask(POWERPC64) Var(rs6000_isa_flags) Use PowerPC-64 instruction set mpowerpc-gpopt -Target Report Mask(PPC_GPOPT) Save +Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) Use PowerPC General Purpose group optional instructions mpowerpc-gfxopt -Target Report Mask(PPC_GFXOPT) Save +Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) Use PowerPC Graphics group optional instructions mmfcrf -Target Report Mask(MFCRF) Save +Target Report Mask(MFCRF) Var(rs6000_isa_flags) Use PowerPC V2.01 single field mfcr instruction mpopcntb -Target Report Mask(POPCNTB) Save +Target Report Mask(POPCNTB) Var(rs6000_isa_flags) Use PowerPC V2.02 popcntb instruction mfprnd -Target Report Mask(FPRND) Save +Target Report Mask(FPRND) Var(rs6000_isa_flags) Use PowerPC V2.02 floating point rounding instructions mcmpb -Target Report Mask(CMPB) Save +Target Report Mask(CMPB) Var(rs6000_isa_flags) Use PowerPC V2.05 compare bytes instruction mmfpgpr -Target Report Mask(MFPGPR) Save +Target Report Mask(MFPGPR) Var(rs6000_isa_flags) Use extended PowerPC V2.05 move floating point to/from GPR instructions maltivec -Target Report Mask(ALTIVEC) Save +Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) Use AltiVec instructions mhard-dfp -Target Report Mask(DFP) Save +Target Report Mask(DFP) Var(rs6000_isa_flags) Use decimal floating point instructions mmulhw -Target Report Mask(MULHW) Save +Target Report Mask(MULHW) Var(rs6000_isa_flags) Use 4xx half-word multiply instructions mdlmzb -Target Report Mask(DLMZB) Save +Target Report Mask(DLMZB) Var(rs6000_isa_flags) Use 4xx string-search dlmzb instruction mmultiple -Target Report Mask(MULTIPLE) Save +Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) Generate load/store multiple instructions mstring -Target Report Mask(STRING) Save +Target Report Mask(STRING) Var(rs6000_isa_flags) Generate string instructions for block moves msoft-float -Target Report RejectNegative Mask(SOFT_FLOAT) +Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) Do not use hardware floating point mhard-float -Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) +Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) Use hardware floating point mpopcntd -Target Report Mask(POPCNTD) Save +Target Report Mask(POPCNTD) Var(rs6000_isa_flags) Use PowerPC V2.06 popcntd instruction mfriz @@ -171,7 +178,7 @@ Target RejectNegative Joined Var(rs6000_ Vector library ABI to use mvsx -Target Report Mask(VSX) Save +Target Report Mask(VSX) Var(rs6000_isa_flags) Use vector/scalar (VSX) instructions mvsx-scalar-double @@ -211,11 +218,11 @@ Target Undocumented Report Var(TARGET_VE ; Explicitly control whether we vectorize the builtins or not. mno-update -Target Report RejectNegative Mask(NO_UPDATE) Save +Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) Do not generate load/store with update instructions mupdate -Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) +Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) Generate load/store with update instructions msingle-pic-base @@ -258,7 +265,7 @@ Target Report RejectNegative Joined Var( Generate software reciprocal divide and square root for better throughput. mrecip-precision -Target Report Mask(RECIP_PRECISION) Save +Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) Assume that the reciprocal estimate instructions provide more accuracy. mno-fp-in-toc @@ -285,7 +292,7 @@ Place symbol+offset constants in TOC ; This is at the cost of having 2 extra loads and one extra store per ; function, and one less allocable register. mminimal-toc -Target Report Mask(MINIMAL_TOC) +Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) Use only one TOC entry per procedure mfull-toc @@ -309,7 +316,7 @@ Target Report Var(rs6000_block_move_inli Specify how many bytes should be moved inline before calling out to memcpy/memmove misel -Target Report Mask(ISEL) Save +Target Report Mask(ISEL) Var(rs6000_isa_flags) Generate isel instructions misel=no Index: gcc/config/rs6000/aix64.opt =================================================================== --- gcc/config/rs6000/aix64.opt (revision 192474) +++ gcc/config/rs6000/aix64.opt (working copy) @@ -20,11 +20,11 @@ ; <http://www.gnu.org/licenses/>. maix64 -Target Report RejectNegative Negative(maix32) Mask(64BIT) +Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags) Compile for 64-bit pointers maix32 -Target Report RejectNegative Negative(maix64) InverseMask(64BIT) +Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags) Compile for 32-bit pointers mpe Index: gcc/config/rs6000/sysv4.opt =================================================================== --- gcc/config/rs6000/sysv4.opt (revision 192474) +++ gcc/config/rs6000/sysv4.opt (working copy) @@ -49,12 +49,12 @@ Target Report Var(TARGET_NO_BITFIELD_TYP Align to the base type of the bit-field mstrict-align -Target Report Mask(STRICT_ALIGN) +Target Report Mask(STRICT_ALIGN) Var(rs6000_isa_flags) Align to the base type of the bit-field Don't assume that unaligned accesses are handled by the system mrelocatable -Target Report Mask(RELOCATABLE) +Target Report Mask(RELOCATABLE) Var(rs6000_isa_flags) Produce code relocatable at runtime mrelocatable-lib @@ -62,19 +62,19 @@ Target Produce code relocatable at runtime mlittle-endian -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code mlittle -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code mbig-endian -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code mbig -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code ;; FIXME: This does nothing. What should be done? @@ -96,7 +96,7 @@ Target RejectNegative no description yet meabi -Target Report Mask(EABI) +Target Report Mask(EABI) Var(rs6000_isa_flags) Use EABI mbit-word @@ -138,11 +138,11 @@ Target RejectNegative no description yet m64 -Target Report RejectNegative Negative(m32) Mask(64BIT) +Target Report RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target Report RejectNegative Negative(m64) InverseMask(64BIT) +Target Report RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code mnewlib Index: gcc/config/rs6000/darwin.opt =================================================================== --- gcc/config/rs6000/darwin.opt (revision 192474) +++ gcc/config/rs6000/darwin.opt (working copy) @@ -34,9 +34,9 @@ findirect-data Driver RejectNegative Alias(mfix-and-continue) m64 -Target RejectNegative Negative(m32) Mask(64BIT) +Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target RejectNegative Negative(m64) InverseMask(64BIT) +Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code Index: gcc/config/rs6000/rs6000-cpus.def =================================================================== --- gcc/config/rs6000/rs6000-cpus.def (revision 192474) +++ gcc/config/rs6000/rs6000-cpus.def (working copy) @@ -18,6 +18,57 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ +/* ISA masks. */ +#ifndef ISA_2_1_MASKS +#define ISA_2_1_MASKS OPTION_MASK_MFCRF +#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB) +#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND) + + /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add + ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, + fre, fsqrt, etc. were no longer documented as optional. Group masks by + server and embedded. */ +#define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT) + +#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP) + + /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but + altivec is a win so enable it. */ +#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD) +#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_ALTIVEC \ + | OPTION_MASK_VSX) + +#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) + +/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ +#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_DFP \ + | OPTION_MASK_DLMZB \ + | OPTION_MASK_FPRND \ + | OPTION_MASK_ISEL \ + | OPTION_MASK_MFCRF \ + | OPTION_MASK_MFPGPR \ + | OPTION_MASK_MULHW \ + | OPTION_MASK_NO_UPDATE \ + | OPTION_MASK_POPCNTB \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_POWERPC64 \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_SOFT_FLOAT \ + | OPTION_MASK_STRICT_ALIGN \ + | OPTION_MASK_VSX) + +#endif + /* This table occasionally claims that a processor does not support a particular feature even though it does, but the feature is slower than the alternative. Thus, it shouldn't be relied on as a complete description of Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 192474) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -1121,7 +1121,8 @@ static const struct attribute_spec rs600 { NULL, 0, 0, false, false, false, NULL, false } }; \f -#ifndef MASK_STRICT_ALIGN +#ifndef OPTION_MASK_STRICT_ALIGN +#define OPTION_MASK_STRICT_ALIGN 0 #define MASK_STRICT_ALIGN 0 #endif #ifndef TARGET_PROFILE_KERNEL @@ -1464,48 +1465,7 @@ static const struct attribute_spec rs600 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok \f -/* Simplifications for entries below. */ - -enum { - POWERPC_7400_MASK = MASK_PPC_GFXOPT | MASK_ALTIVEC -}; - -/* Some OSs don't support saving the high part of 64-bit registers on context - switch. Other OSs don't support saving Altivec registers. On those OSs, we - don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants - either, the user must explicitly specify them and we won't interfere with - the user's specification. */ - -enum { - POWERPC_MASKS = (MASK_PPC_GPOPT | MASK_STRICT_ALIGN - | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC - | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW - | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP - | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE - | MASK_RECIP_PRECISION) -}; - -/* Masks for instructions set at various powerpc ISAs. */ -enum { - ISA_2_1_MASKS = MASK_MFCRF, - ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB), - ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND), - - /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add - ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, - fre, fsqrt, etc. were no longer documented as optional. Group masks by - server and embedded. */ - ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION - | MASK_PPC_GFXOPT | MASK_PPC_GPOPT), - ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP), - - /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but - altivec is a win so enable it. */ - ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD), - ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC - | MASK_VSX) -}; - +/* Processor table. */ struct rs6000_ptt { const char *const name; /* Canonical processor name. */ @@ -2357,21 +2317,21 @@ darwin_rs6000_override_options (void) if (TARGET_64BIT && ! TARGET_POWERPC64) { - target_flags |= MASK_POWERPC64; + rs6000_isa_flags |= OPTION_MASK_POWERPC64; warning (0, "-m64 requires PowerPC64 architecture, enabling"); } if (flag_mkernel) { rs6000_default_long_calls = 1; - target_flags |= MASK_SOFT_FLOAT; + rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; } /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes Altivec. */ if (!flag_mkernel && !flag_apple_kext && TARGET_64BIT - && ! (target_flags_explicit & MASK_ALTIVEC)) - target_flags |= MASK_ALTIVEC; + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)) + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; /* Unless the user (not the configurer) has explicitly overridden it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to @@ -2379,10 +2339,10 @@ darwin_rs6000_override_options (void) if (!flag_mkernel && !flag_apple_kext && strverscmp (darwin_macosx_version_min, "10.5") >= 0 - && ! (target_flags_explicit & MASK_ALTIVEC) + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC) && ! global_options_set.x_rs6000_cpu_index) { - target_flags |= MASK_ALTIVEC; + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; } } #endif @@ -2463,18 +2423,24 @@ rs6000_option_override_internal (bool gl rs6000_pointer_size = 32; } - set_masks = POWERPC_MASKS | MASK_SOFT_FLOAT; + /* Some OSs don't support saving the high part of 64-bit registers on context + switch. Other OSs don't support saving Altivec registers. On those OSs, + we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings; + if the user wants either, the user must explicitly specify them and we + won't interfere with the user's specification. */ + + set_masks = POWERPC_MASKS; #ifdef OS_MISSING_POWERPC64 if (OS_MISSING_POWERPC64) - set_masks &= ~MASK_POWERPC64; + set_masks &= ~OPTION_MASK_POWERPC64; #endif #ifdef OS_MISSING_ALTIVEC if (OS_MISSING_ALTIVEC) - set_masks &= ~MASK_ALTIVEC; + set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX); #endif /* Don't override by the processor default if given explicitly. */ - set_masks &= ~target_flags_explicit; + set_masks &= ~rs6000_isa_flags_explicit; /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed the cpu in a target attribute or pragma, but did not specify a tuning @@ -2512,13 +2478,18 @@ rs6000_option_override_internal (bool gl TARGET_DEFAULT. */ if (have_cpu) { - target_flags &= ~set_masks; - target_flags |= (processor_target_table[cpu_index].target_enable - & set_masks); + rs6000_isa_flags &= ~set_masks; + rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable + & set_masks); } else - target_flags |= (processor_target_table[cpu_index].target_enable - & ~target_flags_explicit); + rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable + & ~rs6000_isa_flags_explicit); + + /* If no -mcpu=<xxx>, inherit any default options that were cleared via + POWERPC_MASKS. */ + if (!have_cpu) + rs6000_isa_flags |= (TARGET_DEFAULT & ~rs6000_isa_flags_explicit); if (rs6000_tune_index >= 0) tune_index = rs6000_tune_index; @@ -2603,7 +2574,8 @@ rs6000_option_override_internal (bool gl use instructions that would be microcoded on the Cell, use the load/store multiple and string instructions. */ if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode) - target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); + rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE + | OPTION_MASK_STRING); /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu is a 750, because the hardware doesn't support the @@ -2615,15 +2587,15 @@ rs6000_option_override_internal (bool gl { if (TARGET_MULTIPLE) { - target_flags &= ~MASK_MULTIPLE; - if ((target_flags_explicit & MASK_MULTIPLE) != 0) + rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE; + if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0) warning (0, "-mmultiple is not supported on little endian systems"); } if (TARGET_STRING) { - target_flags &= ~MASK_STRING; - if ((target_flags_explicit & MASK_STRING) != 0) + rs6000_isa_flags &= ~OPTION_MASK_STRING; + if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0) warning (0, "-mstring is not supported on little endian systems"); } } @@ -2635,10 +2607,10 @@ rs6000_option_override_internal (bool gl if (!TARGET_HARD_FLOAT || !TARGET_FPRS || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx requires hardware floating point"); else - target_flags &= ~ MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; } else if (TARGET_PAIRED_FLOAT) msg = N_("-mvsx and -mpaired are incompatible"); @@ -2649,9 +2621,10 @@ rs6000_option_override_internal (bool gl msg = N_("-mvsx used with little endian code"); else if (TARGET_AVOID_XFORM > 0) msg = N_("-mvsx needs indexed addressing"); - else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC)) + else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit + & OPTION_MASK_ALTIVEC)) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx and -mno-altivec are incompatible"); else msg = N_("-mno-altivec disables vsx"); @@ -2660,27 +2633,27 @@ rs6000_option_override_internal (bool gl if (msg) { warning (0, msg); - target_flags &= ~ MASK_VSX; - target_flags_explicit |= MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; + rs6000_isa_flags_explicit |= OPTION_MASK_VSX; } } /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-<option> to disable the code. */ if (TARGET_VSX) - target_flags |= (ISA_2_6_MASKS_SERVER & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit); else if (TARGET_POPCNTD) - target_flags |= (ISA_2_6_MASKS_EMBEDDED & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit); else if (TARGET_DFP) - target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~rs6000_isa_flags_explicit); else if (TARGET_CMPB) - target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit); else if (TARGET_FPRND) - target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_4_MASKS & ~rs6000_isa_flags_explicit); else if (TARGET_POPCNTB) - target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_2_MASKS & ~rs6000_isa_flags_explicit); else if (TARGET_ALTIVEC) - target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit); + rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit); /* E500mc does "better" if we inline more aggressively. Respect the user's opinion, though. */ @@ -2759,7 +2732,8 @@ rs6000_option_override_internal (bool gl unless the altivec ABI was set. This is set by default for 64-bit, but not for 32-bit. */ if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi) - target_flags &= ~((MASK_VSX | MASK_ALTIVEC) & ~target_flags_explicit); + rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC) + & ~rs6000_isa_flags_explicit); /* Enable Altivec ABI for AIX -maltivec. */ if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX)) @@ -2837,14 +2811,14 @@ rs6000_option_override_internal (bool gl rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE; rs6000_double_float = TARGET_E500_DOUBLE; - target_flags &= ~MASK_STRING; + rs6000_isa_flags &= ~OPTION_MASK_STRING; break; default: - if (have_cpu && !(target_flags_explicit & MASK_ISEL)) - target_flags &= ~MASK_ISEL; + if (have_cpu && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL)) + rs6000_isa_flags &= ~OPTION_MASK_ISEL; break; } @@ -25330,7 +25304,7 @@ rs6000_darwin_file_start (void) i = 0; while (mapping[i].arg != NULL && strcmp (mapping[i].arg, cpu_id) != 0 - && (mapping[i].if_set & target_flags) == 0) + && (mapping[i].if_set & rs6000_isa_flags) == 0) i++; fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name); @@ -27431,48 +27405,48 @@ struct rs6000_opt_mask { static struct rs6000_opt_mask const rs6000_opt_masks[] = { - { "altivec", MASK_ALTIVEC, false, true }, - { "cmpb", MASK_CMPB, false, true }, - { "dlmzb", MASK_DLMZB, false, true }, - { "fprnd", MASK_FPRND, false, true }, - { "hard-dfp", MASK_DFP, false, true }, - { "isel", MASK_ISEL, false, true }, - { "mfcrf", MASK_MFCRF, false, true }, - { "mfpgpr", MASK_MFPGPR, false, true }, - { "mulhw", MASK_MULHW, false, true }, - { "multiple", MASK_MULTIPLE, false, true }, - { "update", MASK_NO_UPDATE, true , true }, - { "popcntb", MASK_POPCNTB, false, true }, - { "popcntd", MASK_POPCNTD, false, true }, - { "powerpc-gfxopt", MASK_PPC_GFXOPT, false, true }, - { "powerpc-gpopt", MASK_PPC_GPOPT, false, true }, - { "recip-precision", MASK_RECIP_PRECISION, false, true }, - { "string", MASK_STRING, false, true }, - { "vsx", MASK_VSX, false, true }, -#ifdef MASK_64BIT + { "altivec", OPTION_MASK_ALTIVEC, false, true }, + { "cmpb", OPTION_MASK_CMPB, false, true }, + { "dlmzb", OPTION_MASK_DLMZB, false, true }, + { "fprnd", OPTION_MASK_FPRND, false, true }, + { "hard-dfp", OPTION_MASK_DFP, false, true }, + { "isel", OPTION_MASK_ISEL, false, true }, + { "mfcrf", OPTION_MASK_MFCRF, false, true }, + { "mfpgpr", OPTION_MASK_MFPGPR, false, true }, + { "mulhw", OPTION_MASK_MULHW, false, true }, + { "multiple", OPTION_MASK_MULTIPLE, false, true }, + { "update", OPTION_MASK_NO_UPDATE, true , true }, + { "popcntb", OPTION_MASK_POPCNTB, false, true }, + { "popcntd", OPTION_MASK_POPCNTD, false, true }, + { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true }, + { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true }, + { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true }, + { "string", OPTION_MASK_STRING, false, true }, + { "vsx", OPTION_MASK_VSX, false, true }, +#ifdef OPTION_MASK_64BIT #if TARGET_AIX_OS - { "aix64", MASK_64BIT, false, false }, - { "aix32", MASK_64BIT, true, false }, + { "aix64", OPTION_MASK_64BIT, false, false }, + { "aix32", OPTION_MASK_64BIT, true, false }, #else - { "64", MASK_64BIT, false, false }, - { "32", MASK_64BIT, true, false }, + { "64", OPTION_MASK_64BIT, false, false }, + { "32", OPTION_MASK_64BIT, true, false }, #endif #endif -#ifdef MASK_EABI - { "eabi", MASK_EABI, false, false }, +#ifdef OPTION_MASK_EABI + { "eabi", OPTION_MASK_EABI, false, false }, #endif -#ifdef MASK_LITTLE_ENDIAN - { "little", MASK_LITTLE_ENDIAN, false, false }, - { "big", MASK_LITTLE_ENDIAN, true, false }, +#ifdef OPTION_MASK_LITTLE_ENDIAN + { "little", OPTION_MASK_LITTLE_ENDIAN, false, false }, + { "big", OPTION_MASK_LITTLE_ENDIAN, true, false }, #endif -#ifdef MASK_RELOCATABLE - { "relocatable", MASK_RELOCATABLE, false, false }, +#ifdef OPTION_MASK_RELOCATABLE + { "relocatable", OPTION_MASK_RELOCATABLE, false, false }, #endif -#ifdef MASK_STRICT_ALIGN - { "strict-align", MASK_STRICT_ALIGN, false, false }, +#ifdef OPTION_MASK_STRICT_ALIGN + { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false }, #endif - { "soft-float", MASK_SOFT_FLOAT, false, false }, - { "string", MASK_STRING, false, false }, + { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false }, + { "string", OPTION_MASK_STRING, false, false }, }; /* Builtin mask mapping for printing the flags. */ @@ -27583,20 +27557,20 @@ rs6000_inner_target_options (tree args, else { error_p = false; - target_flags_explicit |= mask; + rs6000_isa_flags_explicit |= mask; /* VSX needs altivec, so -mvsx automagically sets altivec. */ - if (mask == MASK_VSX && !invert) - mask |= MASK_ALTIVEC; + if (mask == OPTION_MASK_VSX && !invert) + mask |= OPTION_MASK_ALTIVEC; if (rs6000_opt_masks[i].invert) invert = !invert; if (invert) - target_flags &= ~mask; + rs6000_isa_flags &= ~mask; else - target_flags |= mask; + rs6000_isa_flags |= mask; } break; } @@ -27851,14 +27825,14 @@ rs6000_pragma_target_parse (tree args, t { prev_opt = TREE_TARGET_OPTION (prev_tree); prev_bumask = prev_opt->x_rs6000_builtin_mask; - prev_flags = prev_opt->x_target_flags; + prev_flags = prev_opt->x_rs6000_isa_flags; cur_opt = TREE_TARGET_OPTION (cur_tree); - cur_flags = cur_opt->x_target_flags; + cur_flags = cur_opt->x_rs6000_isa_flags; cur_bumask = cur_opt->x_rs6000_builtin_mask; diff_bumask = (prev_bumask ^ cur_bumask); - diff_flags = (prev_flags ^ cur_flags); + diff_flags = (prev_flags ^ cur_flags); if ((diff_flags != 0) || (diff_bumask != 0)) { @@ -27961,7 +27935,8 @@ rs6000_set_current_function (tree fndecl static void rs6000_function_specific_save (struct cl_target_option *ptr) { - ptr->rs6000_target_flags_explicit = target_flags_explicit; + ptr->x_rs6000_isa_flags = rs6000_isa_flags; + ptr->x_rs6000_isa_flags_explicit = rs6000_isa_flags_explicit; } /* Restore the current options */ @@ -27969,7 +27944,8 @@ rs6000_function_specific_save (struct cl static void rs6000_function_specific_restore (struct cl_target_option *ptr) { - target_flags_explicit = ptr->rs6000_target_flags_explicit; + rs6000_isa_flags = ptr->x_rs6000_isa_flags; + rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit; (void) rs6000_option_override_internal (false); } @@ -27980,10 +27956,10 @@ rs6000_function_specific_print (FILE *fi struct cl_target_option *ptr) { rs6000_print_isa_options (file, indent, "Isa options set", - ptr->x_target_flags); + ptr->x_rs6000_isa_flags); rs6000_print_isa_options (file, indent, "Isa options explicit", - ptr->rs6000_target_flags_explicit); + ptr->x_rs6000_isa_flags_explicit); } /* Helper function to print the current isa or misc options on a line. */ @@ -28093,8 +28069,8 @@ rs6000_can_inline_p (tree caller, tree c /* Callee's options should a subset of the caller's, i.e. a vsx function can inline an altivec function but a non-vsx function can't inline a vsx function. */ - if ((caller_opts->x_target_flags & callee_opts->x_target_flags) - == callee_opts->x_target_flags) + if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags) + == callee_opts->x_rs6000_isa_flags) ret = true; } Index: gcc/config/rs6000/rs6000-c.c =================================================================== --- gcc/config/rs6000/rs6000-c.c (revision 192474) +++ gcc/config/rs6000/rs6000-c.c (working copy) @@ -295,31 +295,31 @@ rs6000_target_modify_macros (bool define (define_p) ? "define" : "undef", flags, bu_mask); - /* target_flags based options. */ + /* rs6000_isa_flags based options. */ rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); - if ((flags & MASK_PPC_GPOPT) != 0) + if ((flags & OPTION_MASK_PPC_GPOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ"); - if ((flags & MASK_PPC_GFXOPT) != 0) + if ((flags & OPTION_MASK_PPC_GFXOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR"); - if ((flags & MASK_POWERPC64) != 0) + if ((flags & OPTION_MASK_POWERPC64) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"); - if ((flags & MASK_MFCRF) != 0) + if ((flags & OPTION_MASK_MFCRF) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4"); - if ((flags & MASK_POPCNTB) != 0) + if ((flags & OPTION_MASK_POPCNTB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5"); - if ((flags & MASK_FPRND) != 0) + if ((flags & OPTION_MASK_FPRND) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X"); - if ((flags & MASK_CMPB) != 0) + if ((flags & OPTION_MASK_CMPB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); - if ((flags & MASK_MFPGPR) != 0) + if ((flags & OPTION_MASK_MFPGPR) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X"); - if ((flags & MASK_POPCNTD) != 0) + if ((flags & OPTION_MASK_POPCNTD) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); - if ((flags & MASK_SOFT_FLOAT) != 0) + if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); - if ((flags & MASK_RECIP_PRECISION) != 0) + if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__"); - if ((flags & MASK_ALTIVEC) != 0) + if ((flags & OPTION_MASK_ALTIVEC) != 0) { const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__"; rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__"); @@ -329,7 +329,7 @@ rs6000_target_modify_macros (bool define if (!flag_iso) rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__"); } - if ((flags & MASK_VSX) != 0) + if ((flags & OPTION_MASK_VSX) != 0) rs6000_define_or_undefine_macro (define_p, "__VSX__"); /* options from the builtin masks. */ @@ -345,7 +345,7 @@ void rs6000_cpu_cpp_builtins (cpp_reader *pfile) { /* Define all of the common macros. */ - rs6000_target_modify_macros (true, target_flags, + rs6000_target_modify_macros (true, rs6000_isa_flags, rs6000_builtin_mask_calculate ()); if (TARGET_FRE) Index: gcc/common/config/rs6000/rs6000-common.c =================================================================== --- gcc/common/config/rs6000/rs6000-common.c (revision 192474) +++ gcc/common/config/rs6000/rs6000-common.c (working copy) @@ -82,23 +82,23 @@ rs6000_handle_option (struct gcc_options switch (code) { case OPT_mfull_toc: - opts->x_target_flags &= ~MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_MINIMAL_TOC; opts->x_TARGET_NO_FP_IN_TOC = 0; opts->x_TARGET_NO_SUM_IN_TOC = 0; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; #ifdef TARGET_USES_SYSV4_OPT /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be just the same as -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; #endif break; #ifdef TARGET_USES_SYSV4_OPT case OPT_mtoc: /* Make -mtoc behave like -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; break; #endif @@ -107,9 +107,10 @@ rs6000_handle_option (struct gcc_options #else case OPT_m64: #endif - opts->x_target_flags |= MASK_POWERPC64; - opts->x_target_flags |= ~opts_set->x_target_flags & MASK_PPC_GFXOPT; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; + opts->x_rs6000_isa_flags |= (~opts_set->x_rs6000_isa_flags + & OPTION_MASK_PPC_GFXOPT); + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; #ifdef TARGET_USES_AIX64_OPT @@ -117,8 +118,8 @@ rs6000_handle_option (struct gcc_options #else case OPT_m32: #endif - opts->x_target_flags &= ~MASK_POWERPC64; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_POWERPC64; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; case OPT_mminimal_toc: @@ -181,8 +182,8 @@ rs6000_handle_option (struct gcc_options case OPT_mrelocatable: if (value == 1) { - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; opts->x_TARGET_NO_FP_IN_TOC = 1; } break; @@ -190,14 +191,16 @@ rs6000_handle_option (struct gcc_options case OPT_mrelocatable_lib: if (value == 1) { - opts->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); + opts_set->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); opts->x_TARGET_NO_FP_IN_TOC = 1; } else { - opts->x_target_flags &= ~MASK_RELOCATABLE; - opts_set->x_target_flags |= MASK_RELOCATABLE; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_RELOCATABLE; } break; #endif @@ -227,15 +230,15 @@ rs6000_handle_option (struct gcc_options "-msingle-float option equivalent to -mhard-float"); /* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_double_float = 0; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_mdouble_float: /* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_single_float = 1; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_msimple_fpu: @@ -259,8 +262,8 @@ rs6000_handle_option (struct gcc_options { /* If -mfpu is not none, then turn off SOFT_FLOAT, turn on HARD_FLOAT. */ - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; opts->x_rs6000_xilinx_fpu = 1; if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL) opts->x_rs6000_single_float = 1; @@ -272,8 +275,8 @@ rs6000_handle_option (struct gcc_options else { /* -mfpu=none is equivalent to -msoft-float. */ - opts->x_target_flags |= MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0; } break; @@ -297,8 +300,4 @@ rs6000_handle_option (struct gcc_options #undef TARGET_OPTION_OPTIMIZATION_TABLE #define TARGET_OPTION_OPTIMIZATION_TABLE rs6000_option_optimization_table -#undef TARGET_DEFAULT_TARGET_FLAGS -#define TARGET_DEFAULT_TARGET_FLAGS \ - (TARGET_DEFAULT) - struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 192474) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -218,55 +218,55 @@ extern const char *host_detect_local_cpu optional field operand for mfcr. */ #ifndef HAVE_AS_MFCRF -#undef TARGET_MFCRF -#define TARGET_MFCRF 0 +#undef OPTION_MFCRF +#define OPTION_MFCRF 0 #endif /* Define TARGET_POPCNTB if the target assembler does not support the popcount byte instruction. */ #ifndef HAVE_AS_POPCNTB -#undef TARGET_POPCNTB -#define TARGET_POPCNTB 0 +#undef OPTION_POPCNTB +#define OPTION_POPCNTB 0 #endif /* Define TARGET_FPRND if the target assembler does not support the fp rounding instructions. */ #ifndef HAVE_AS_FPRND -#undef TARGET_FPRND -#define TARGET_FPRND 0 +#undef OPTION_FPRND +#define OPTION_FPRND 0 #endif /* Define TARGET_CMPB if the target assembler does not support the cmpb instruction. */ #ifndef HAVE_AS_CMPB -#undef TARGET_CMPB -#define TARGET_CMPB 0 +#undef OPTION_CMPB +#define OPTION_CMPB 0 #endif /* Define TARGET_MFPGPR if the target assembler does not support the mffpr and mftgpr instructions. */ #ifndef HAVE_AS_MFPGPR -#undef TARGET_MFPGPR -#define TARGET_MFPGPR 0 +#undef OPTION_MFPGPR +#define OPTION_MFPGPR 0 #endif /* Define TARGET_DFP if the target assembler does not support decimal floating point instructions. */ #ifndef HAVE_AS_DFP -#undef TARGET_DFP -#define TARGET_DFP 0 +#undef OPTION_DFP +#define OPTION_DFP 0 #endif /* Define TARGET_POPCNTD if the target assembler does not support the popcount word and double word instructions. */ #ifndef HAVE_AS_POPCNTD -#undef TARGET_POPCNTD -#define TARGET_POPCNTD 0 +#undef OPTION_POPCNTD +#define OPTION_POPCNTD 0 #endif /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If @@ -465,6 +465,93 @@ extern int rs6000_vector_align[]; #define TARGET_FCTIDUZ TARGET_POPCNTD #define TARGET_FCTIWUZ TARGET_POPCNTD +/* Map OPTION_<xxx> back into TARGET_<xxx> options in rs6000_isa_flags. */ +#define TARGET_ALTIVEC OPTION_ALTIVEC +#define TARGET_CMPB OPTION_CMPB +#define TARGET_DFP OPTION_DFP +#define TARGET_DLMZB OPTION_DLMZB +#define TARGET_EABI OPTION_EABI +#define TARGET_FPRND OPTION_FPRND +#define TARGET_HARD_FLOAT OPTION_HARD_FLOAT +#define TARGET_ISEL OPTION_ISEL +#define TARGET_MFCRF OPTION_MFCRF +#define TARGET_MFPGPR OPTION_MFPGPR +#define TARGET_MULHW OPTION_MULHW +#define TARGET_MULTIPLE OPTION_MULTIPLE +#define TARGET_NO_UPDATE OPTION_NO_UPDATE +#define TARGET_POPCNTB OPTION_POPCNTB +#define TARGET_POPCNTD OPTION_POPCNTD +#define TARGET_PPC_GFXOPT OPTION_PPC_GFXOPT +#define TARGET_PPC_GPOPT OPTION_PPC_GPOPT +#define TARGET_RECIP_PRECISION OPTION_RECIP_PRECISION +#define TARGET_SOFT_FLOAT OPTION_SOFT_FLOAT +#define TARGET_STRICT_ALIGN OPTION_STRICT_ALIGN +#define TARGET_STRING OPTION_STRING +#define TARGET_UPDATE OPTION_UPDATE +#define TARGET_VSX OPTION_VSX + +#define MASK_ALTIVEC OPTION_MASK_ALTIVEC +#define MASK_CMPB OPTION_MASK_CMPB +#define MASK_DFP OPTION_MASK_DFP +#define MASK_DLMZB OPTION_MASK_DLMZB +#define MASK_EABI OPTION_MASK_EABI +#define MASK_FPRND OPTION_MASK_FPRND +#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT +#define MASK_ISEL OPTION_MASK_ISEL +#define MASK_MFCRF OPTION_MASK_MFCRF +#define MASK_MFPGPR OPTION_MASK_MFPGPR +#define MASK_MULHW OPTION_MASK_MULHW +#define MASK_MULTIPLE OPTION_MASK_MULTIPLE +#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE +#define MASK_POPCNTB OPTION_MASK_POPCNTB +#define MASK_POPCNTD OPTION_MASK_POPCNTD +#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT +#define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT +#define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION +#define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT +#define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN +#define MASK_STRING OPTION_MASK_STRING +#define MASK_UPDATE OPTION_MASK_UPDATE +#define MASK_VSX OPTION_MASK_VSX + +#ifndef IN_LIBGCC2 +#define TARGET_POWERPC64 OPTION_POWERPC64 +#define MASK_POWERPC64 OPTION_MASK_POWERPC64 +#endif + +#ifdef OPTION_64BIT +#define TARGET_64BIT OPTION_64BIT +#define MASK_64BIT OPTION_MASK_64BIT +#endif + +#ifdef OPTION_RELOCATABLE +#define TARGET_RELOCATABLE OPTION_RELOCATABLE +#define MASK_RELOCATABLE OPTION_MASK_RELOCATABLE +#endif + +#ifdef OPTION_LITTLE_ENDIAN +#define TARGET_LITTLE_ENDIAN OPTION_LITTLE_ENDIAN +#define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN +#endif + +#ifdef OPTION_MINIMAL_TOC +#define TARGET_MINIMAL_TOC OPTION_MINIMAL_TOC +#define MASK_MINIMAL_TOC OPTION_MASK_MINIMAL_TOC +#endif + +#ifdef OPTION_REGNAMES +#define TARGET_REGNAMES OPTION_REGNAMES +#define MASK_REGNAMES OPTION_MASK_REGNAMES +#endif + +#ifdef OPTION_PROTOTYPE +#define TARGET_PROTOTYPE OPTION_PROTOTYPE +#define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE +#endif + +/* Explicit ISA options that were set. */ +#define rs6000_isa_flags_explicit global_options_set.x_rs6000_isa_flags + /* For power systems, we want to enable Altivec and VSX builtins even if the user did not use -maltivec or -mvsx to allow the builtins to be used inside of #pragma GCC target or the target attribute to change the code level for a Index: gcc/config/rs6000/aix43.h =================================================================== --- gcc/config/rs6000/aix43.h (revision 192474) +++ gcc/config/rs6000/aix43.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/aix51.h =================================================================== --- gcc/config/rs6000/aix51.h (revision 192474) +++ gcc/config/rs6000/aix51.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_POWERPC64 && ! TARGET_64BIT) \ Index: gcc/config/rs6000/aix52.h =================================================================== --- gcc/config/rs6000/aix52.h (revision 192474) +++ gcc/config/rs6000/aix52.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/aix53.h =================================================================== --- gcc/config/rs6000/aix53.h (revision 192474) +++ gcc/config/rs6000/aix53.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/aix61.h =================================================================== --- gcc/config/rs6000/aix61.h (revision 192474) +++ gcc/config/rs6000/aix61.h (working copy) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/freebsd64.h =================================================================== --- gcc/config/rs6000/freebsd64.h (revision 192474) +++ gcc/config/rs6000/freebsd64.h (working copy) @@ -57,7 +57,7 @@ extern int dot_symbols; -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "freebsd" @@ -79,14 +79,14 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ - if (target_flags & MASK_RELOCATABLE) \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error (INVALID_64BIT, "relocatable"); \ } \ - if (target_flags & MASK_EABI) \ + if (rs6000_isa_flags & OPTION_MASK_EABI) \ { \ - target_flags &= ~MASK_EABI; \ + rs6000_isa_flags &= ~OPTION_MASK_EABI; \ error (INVALID_64BIT, "eabi"); \ } \ if (TARGET_PROTOTYPE) \ @@ -94,12 +94,13 @@ extern int dot_symbols; target_prototype = 0; \ error (INVALID_64BIT, "prototype"); \ } \ - if ((target_flags & MASK_POWERPC64) == 0) \ + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ error ("-m64 requires a PowerPC64 cpu"); \ } \ - if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ + if ((rs6000_isa_flags_explicit \ + & OPTION_MASK_MINIMAL_TOC) != 0) \ { \ if (global_options_set.x_rs6000_current_cmodel \ && rs6000_current_cmodel != CMODEL_SMALL) \ Index: gcc/config/rs6000/freebsd.h =================================================================== --- gcc/config/rs6000/freebsd.h (revision 192474) +++ gcc/config/rs6000/freebsd.h (working copy) @@ -72,7 +72,7 @@ -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) Index: gcc/config/rs6000/linux64.h =================================================================== --- gcc/config/rs6000/linux64.h (revision 192474) +++ gcc/config/rs6000/linux64.h (working copy) @@ -81,7 +81,7 @@ extern int dot_symbols; -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "linux" @@ -103,14 +103,14 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ - if (target_flags & MASK_RELOCATABLE) \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error (INVALID_64BIT, "relocatable"); \ } \ - if (target_flags & MASK_EABI) \ + if (rs6000_isa_flags & OPTION_MASK_EABI) \ { \ - target_flags &= ~MASK_EABI; \ + rs6000_isa_flags &= ~OPTION_MASK_EABI; \ error (INVALID_64BIT, "eabi"); \ } \ if (TARGET_PROTOTYPE) \ @@ -118,12 +118,13 @@ extern int dot_symbols; target_prototype = 0; \ error (INVALID_64BIT, "prototype"); \ } \ - if ((target_flags & MASK_POWERPC64) == 0) \ + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ error ("-m64 requires a PowerPC64 cpu"); \ } \ - if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ + if ((rs6000_isa_flags_explicit \ + & OPTION_MASK_MINIMAL_TOC) != 0) \ { \ if (global_options_set.x_rs6000_current_cmodel \ && rs6000_current_cmodel != CMODEL_SMALL) \ @@ -213,20 +214,20 @@ extern int dot_symbols; #ifndef RS6000_BI_ARCH /* 64-bit PowerPC Linux is always big-endian. */ -#undef TARGET_LITTLE_ENDIAN -#define TARGET_LITTLE_ENDIAN 0 +#undef OPTION_LITTLE_ENDIAN +#define OPTION_LITTLE_ENDIAN 0 /* 64-bit PowerPC Linux always has a TOC. */ #undef TARGET_TOC #define TARGET_TOC 1 /* Some things from sysv4.h we don't do when 64 bit. */ -#undef TARGET_RELOCATABLE -#define TARGET_RELOCATABLE 0 -#undef TARGET_EABI -#define TARGET_EABI 0 -#undef TARGET_PROTOTYPE -#define TARGET_PROTOTYPE 0 +#undef OPTION_RELOCATABLE +#define OPTION_RELOCATABLE 0 +#undef OPTION_EABI +#define OPTION_EABI 0 +#undef OPTION_PROTOTYPE +#define OPTION_PROTOTYPE 0 #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP 0 Index: gcc/config/rs6000/linux.h =================================================================== --- gcc/config/rs6000/linux.h (revision 192474) +++ gcc/config/rs6000/linux.h (working copy) @@ -109,7 +109,7 @@ -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #define TARGET_POSIX_IO Index: gcc/config/rs6000/option-defaults.h =================================================================== --- gcc/config/rs6000/option-defaults.h (revision 192474) +++ gcc/config/rs6000/option-defaults.h (working copy) @@ -35,11 +35,12 @@ #define OPT_32 "m32" #endif -#ifndef MASK_64BIT +#ifndef OPTION_MASK_64BIT +#define OPTION_MASK_64BIT 0 #define MASK_64BIT 0 #endif -#if TARGET_DEFAULT & MASK_64BIT +#if TARGET_DEFAULT & OPTION_MASK_64BIT #define OPT_ARCH64 "!"OPT_32 #define OPT_ARCH32 OPT_32 #else Index: gcc/config/rs6000/sysv4.h =================================================================== --- gcc/config/rs6000/sysv4.h (revision 192474) +++ gcc/config/rs6000/sysv4.h (working copy) @@ -40,9 +40,10 @@ #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc" -#define TARGET_TOC ((target_flags & MASK_64BIT) \ - || ((target_flags & (MASK_RELOCATABLE \ - | MASK_MINIMAL_TOC)) \ +#define TARGET_TOC ((rs6000_isa_flags & OPTION_MASK_64BIT) \ + || ((rs6000_isa_flags \ + & (OPTION_MASK_RELOCATABLE \ + | OPTION_MASK_MINIMAL_TOC)) \ && flag_pic > 1) \ || DEFAULT_ABI == ABI_AIX) @@ -77,13 +78,13 @@ do { \ else if (!strcmp (rs6000_abi_name, "sysv-noeabi")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags &= ~ MASK_EABI; \ + rs6000_isa_flags &= ~ OPTION_MASK_EABI; \ } \ else if (!strcmp (rs6000_abi_name, "sysv-eabi") \ || !strcmp (rs6000_abi_name, "eabi")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags |= MASK_EABI; \ + rs6000_isa_flags |= OPTION_MASK_EABI; \ } \ else if (!strcmp (rs6000_abi_name, "aixdesc")) \ rs6000_current_abi = ABI_AIX; \ @@ -102,8 +103,8 @@ do { \ else if (!strcmp (rs6000_abi_name, "i960-old")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags |= (MASK_LITTLE_ENDIAN | MASK_EABI); \ - target_flags &= ~MASK_STRICT_ALIGN; \ + rs6000_isa_flags |= (OPTION_MASK_LITTLE_ENDIAN | OPTION_MASK_EABI); \ + rs6000_isa_flags &= ~OPTION_MASK_STRICT_ALIGN; \ TARGET_NO_BITFIELD_WORD = 1; \ } \ else \ @@ -168,13 +169,13 @@ do { \ \ if (TARGET_RELOCATABLE && !TARGET_MINIMAL_TOC) \ { \ - target_flags |= MASK_MINIMAL_TOC; \ + rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; \ error ("-mrelocatable and -mno-minimal-toc are incompatible"); \ } \ \ if (TARGET_RELOCATABLE && rs6000_current_abi == ABI_AIX) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error ("-mrelocatable and -mcall-%s are incompatible", \ rs6000_abi_name); \ } \ @@ -188,7 +189,7 @@ do { \ \ if (rs6000_current_abi == ABI_AIX && TARGET_LITTLE_ENDIAN) \ { \ - target_flags &= ~MASK_LITTLE_ENDIAN; \ + rs6000_isa_flags &= ~OPTION_MASK_LITTLE_ENDIAN; \ error ("-mcall-aixdesc must be big endian"); \ } \ \ @@ -200,7 +201,7 @@ do { \ /* Treat -fPIC the same as -mrelocatable. */ \ if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX) \ { \ - target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; \ + rs6000_isa_flags |= OPTION_MASK_RELOCATABLE | OPTION_MASK_MINIMAL_TOC; \ TARGET_NO_FP_IN_TOC = 1; \ } \ \ @@ -212,9 +213,9 @@ do { \ #ifndef RS6000_BI_ARCH # define SUBSUBTARGET_OVERRIDE_OPTIONS \ do { \ - if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) \ + if ((TARGET_DEFAULT ^ rs6000_isa_flags) & OPTION_MASK_64BIT) \ error ("-m%s not supported in this configuration", \ - (target_flags & MASK_64BIT) ? "64" : "32"); \ + (rs6000_isa_flags & OPTION_MASK_64BIT) ? "64" : "32"); \ } while (0) #endif @@ -500,8 +501,8 @@ extern int fixuplabelno; #define TARGET_OS_SYSV_CPP_BUILTINS() \ do \ { \ - if (target_flags_explicit \ - & MASK_RELOCATABLE) \ + if (rs6000_isa_flags_explicit \ + & OPTION_MASK_RELOCATABLE) \ builtin_define ("_RELOCATABLE"); \ } \ while (0) Index: gcc/config/rs6000/t-rs6000 =================================================================== --- gcc/config/rs6000/t-rs6000 (revision 192474) +++ gcc/config/rs6000/t-rs6000 (working copy) @@ -26,7 +26,8 @@ rs6000.o: $(CONFIG_H) $(SYSTEM_H) corety $(OBSTACK_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) except.h function.h \ output.h dbxout.h $(BASIC_BLOCK_H) toplev.h $(GGC_H) $(HASHTAB_H) \ $(TM_P_H) $(TARGET_H) $(TARGET_DEF_H) langhooks.h reload.h gt-rs6000.h \ - cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) dumpfile.h + cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) dumpfile.h \ + $(srcdir)/config/rs6000/rs6000-cpus.def rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.c \ $(srcdir)/config/rs6000/rs6000-protos.h \ ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f 2012-10-16 16:13 ` [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f Michael Meissner @ 2012-10-17 19:42 ` David Edelsohn 2012-10-17 20:48 ` Michael Meissner 0 siblings, 1 reply; 13+ messages in thread From: David Edelsohn @ 2012-10-17 19:42 UTC (permalink / raw) To: Michael Meissner, gcc-patches, bergner, segher, iain, andreast-list Mike, This patch is okay with the appropriate changes to adapt to the common infrastructure improvements. We will continue to iterate on this. Are there any testcases that would be useful? A lot of other testcases use target flags, so those probably will point out problems. Thanks, David On Tue, Oct 16, 2012 at 11:56 AM, Michael Meissner <meissner@linux.vnet.ibm.com> wrote: > While Joseph and I are iterating on global changes to the options machinery, > David had said patch #2b was ok for just powerpc specific changes. I took > patch #2b, and adjusted it for the 3 patches I already checked in. I rewrote > the ChangeLog entries to try and be more explicit in what was going on. This > bootstraped and had no regressions. Is this ok to check in? > > 2012-10-16 Michael Meissner <meissner@linux.vnet.ibm.com> > > * config/rs6000/rs6000.opt (rs6000_isa_flags): New flag word to > replace target_flags that gives us 63 possible switches. > (x_rs6000_isa_flags): Save area for rs6000_isa_flags. > (x_rs6000_isa_flags_explicit): Save area for > rs6000_isa_flags_explicit. > (rs6000_target_flags_explicit): Delete in favor of > x_rs6000_isa_flags_explicit. > (-mpowerpc64): Change all switches that used to be in target_flags > to now be in rs6000_isa_flags. In using rs6000_isa_flags, the > options machinary will generate names of the form OPITON_<xxx> > instead of TARGET_<xxx> and OPTION_MASK_<xxx> instead of > MASK_<xxx>. > (-mpowerpc-gpopt): Likewise. > (-mpowerpc-gfxopt): Likewise. > (-mmfcrf): Likewise. > (-mpopcntb): Likewise. > (-mfprnd): Likewise. > (-mcmpb): Likewise. > (-mmfpgpr): Likewise. > (-maltivec): Likewise. > (-mhard-dfp): Likewise. > (-mmulhw): Likewise. > (-mdlmzb): Likewise. > (-mmultiple): Likewise. > (-mstring): Likewise. > (-msoft-float): Likewise. > (-mhard-float): Likewise. > (-mpopcntd): Likewise. > (-mvsx): Likewise. > (-mno-update): Likewise. > (-mupdate): Likewise. > (-mrecip-precision): Likewise. > (-mminimal-toc): Likewise. > (-misel): Likewise. > * config/rs6000/aix64.opt (-maix64): Likewise. > (-maix32): Likewise. > * config/rs6000/sysv4.opt (-mstrict-align): Likewise. > (-mrelocatable): Likewise. > (-mlittle-endian): Likewise. > (-mlittle): Likewise. > (-mbig-endian): LIkewise. > (-mbig): Likewise. > (-meabi): Likewise. > (-m64): Likewise. > (-m32): Likewise. > * config/rs6000/darwin.opt (-m64): Likewise. > (-m32): Likewise. > > * config/rs6000/rs6000-cpus.def (ISA_2_1_MASKS): Move the various > masks used in rs6000.c here, since they are more logically in this > file. Convert from being enums to just #defines, since the types > of these masks is now HOST_WIDE_INT instead of int. For > POWERPC_MASKS, add MASK_SOFT_FLOAT, since the only use case or'ed > in the mask. Change the use in rs6000.c not to do the OR of > MASK_SOFT_FLOAT. > (ISA_2_1_MASKS): Likewise. > (ISA_2_2_MASKS): Likewise. > (ISA_2_4_MASKS): Likewise. > (ISA_2_5_MASKS_EMBEDDED): Likewise. > (ISA_2_5_MASKS_SERVER): Likewise. > (POWERPC_7400_MASK): Likewise. > (POWERPC_MASKS): Likewise. > * config/rs6000/rs6000.c (ISA_2_1_MASKS): Likewise. > (ISA_2_1_MASKS): Likewise. > (ISA_2_2_MASKS): Likewise. > (ISA_2_4_MASKS): Likewise. > (ISA_2_5_MASKS_EMBEDDED): Likewise. > (ISA_2_5_MASKS_SERVER): Likewise. > (POWERPC_7400_MASK): Likewise. > (POWERPC_MASKS): Likewise. > (rs6000_option_override_internal): Likewise. > > * config/rs6000/rs6000.c (darwin_rs6000_override_options): Change > all uses of target_flags to rs6000_isa_flags. Change all uses of > target_flags_explicit to rs6000_isa_flags_explicit. Change the > use of MASK_<xxx> to OPTION_MASK_<xxx> that options.h defines when > we use a secondary flags word. Save/restore/print the new flags > word when switching contexts with different target attributes. > (rs6000_option_override_internal): Likewise. > (rs6000_darwin_file_start): Likewise. > (rs6000_opt_masks): Likewise. > (rs6000_inner_target_options): Likewise. > (rs6000_pragma_target_parse): Likewise. > (rs6000_set_current_function): Likewise. > (rs6000_function_specific_save): Likewise. > (rs6000_function_specific_restore): Likewise. > (rs6000_function_specific_print): Likewise. > (rs6000_can_inline_p): Likewise. > * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): > Likewise. > (rs6000_cpu_cpp_builtins): Likewise. > * common/config/rs6000/rs6000-driver.c (rs6000_handle_option): > Likewise. > > * config/rs6000/rs6000.h (OPTION_MFCRF): Replace TARGET_<xxx> with > OPTION_<xxx> if the assembler doesn't support mfcrf, popcntb, > fprnd, cmpb, mfpgpr, dfp, popcntd instructions. > (TARGET_MFCRF): Likewise. > (OPTION_POPCNTB): Likewise. > (TARGET_POPCNTB): Likewise. > (OPTION_FPRND): Likewise. > (TARGET_FPRND): Likewise. > (OPTION_CMPB): Likewise. > (TARGET_CMPB): Likewise. > (OPTION_HARD_DFP): Likewise. > (TARGET_HARD_DFP): Likewise. > (OPTION_POPCNTD): Likewise. > (TARGET_POPCNTD): LIkewise. > (TARGET_ALTIVEC): In moving to using Var(...) for all of the isa > switches, the options machinery now uses OPTION_<xxx> instead of > TARGET_<xxx> for whether the switch was set, OPTION_MASK_<xxx> > instead of MASK_<xxx> for the mask name. Use #define to map the > old name into the new name. For switches that are defined in > aix64.opt, sysv4.opt, and darwin.opt, only do the definition if > those switches were defined. > (TARGET_CMPB): Likewise. > (TARGET_DFP): Likewise. > (TARGET_DLMZB): Likewise. > (TARGET_EABI): Likewise. > (TARGET_FPRND): Likewise. > (TARGET_HARD_FLOAT): Likewise. > (TARGET_ISEL): Likewise. > (TARGET_MFCRF): Likewise. > (TARGET_MFPGPR): Likewise. > (TARGET_MULHW): Likewise. > (TARGET_MULTIPLE): Likewise. > (TARGET_NO_UPDATE): Likewise. > (TARGET_POPCNTB): Likewise. > (TARGET_POPCNTD): Likewise. > (TARGET_PPC_GFXOPT): Likewise. > (TARGET_PPC_GPOPT): Likewise. > (TARGET_RECIP_PRECISION): Likewise. > (TARGET_SOFT_FLOAT): Likewise. > (TARGET_STRICT_ALIGN): Likewise. > (TARGET_STRING): Likewise. > (TARGET_UPDATE): Likewise. > (TARGET_VSX): Likewise. > (MASK_ALTIVEC): Likewise. > (MASK_CMPB): Likewise. > (MASK_DFP): Likewise. > (MASK_DLMZB): Likewise. > (MASK_EABI): Likewise. > (MASK_FPRND): Likewise. > (MASK_HARD_FLOAT): Likewise. > (MASK_ISEL): Likewise. > (MASK_MFCRF): Likewise. > (MASK_MFPGPR): Likewise. > (MASK_MULHW): Likewise. > (MASK_MULTIPLE): Likewise. > (MASK_NO_UPDATE): Likewise. > (MASK_POPCNTB): Likewise. > (MASK_POPCNTD): Likewise. > (MASK_PPC_GFXOPT): Likewise. > (MASK_PPC_GPOPT): Likewise. > (MASK_RECIP_PRECISION): Likewise. > (MASK_SOFT_FLOAT): Likewise. > (MASK_STRICT_ALIGN): Likewise. > (MASK_STRING): Likewise. > (MASK_UPDATE): Likewise. > (MASK_VSX): Likewise. > (TARGET_POWERPC64): Likewise. > (MASK_POWERPC64): Likewise. > (TARGET_64BIT): Likewise. > (MASK_64BIT): Likewise. > (TARGET_RELOCATABLE): Likewise. > (MASK_RELOCATABLE): Likewise. > (TARGET_LITTLE_ENDIAN): Likewise. > (MASK_LITTLE_ENDIAN): Likewise. > (TARGET_MINIMAL_TOC): Likewise. > (MASK_MINIMAL_TOC): Likewise. > (TARGET_REGNAMES): Likewise. > (MASK_REGNAMES): Likewise. > (TARGET_PROTOTYPE): Likewise. > (MASK_PROTOTYPE): Likewise. > (rs6000_isa_flags_explicit): Define in terms of the > global_options_set structure. > > * gcc/config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): > Change use of target_flags to rs6000_isa_flags, > target_flags_explicit to rs6000_isa_flags_explicit, and MASK_<xxx> > to OPTION_MASK_<xxx>. > * gcc/config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): > Likewise. > * gcc/config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): > Likewise. > * gcc/config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): > Likewise. > * gcc/config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): > Likewise. > * gcc/config/rs6000/freebsd64.h (RELOCATABLE_NEEDS_FIXUP): > Likewise. > (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. > * gcc/config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP): > Likewise. > * gcc/config/rs6000/linux64.h (RELOCATABLE_NEEDS_FIXUP): > Likewise. > (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. > (OPTION_LITTLE_ENDIAN): Likewise. > (OPTION_RELOCATABLE): Likewise. > (OPTION_EABI): Likewise. > (OPTION_PROTOTYPE): Likewise. > * gcc/config/rs6000/linux.h (RELOCATABLE_NEEDS_FIXUP): Likewise. > * gcc/config/rs6000/option-defaults.h (OPTION_MASK_64BIT): > Likewise. > (OPT_ARCH32): Likewise. > (OPT_ARCH64): Likewise. > * gcc/config/rs6000/sysv4.h (TARGET_TOC): Likewise. > (SUBTARGET_OVERRIDE_OPTIONS): Likewise. > (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. > (TARGET_OS_SYSV_CPP_BUILTINS): Likewise. > > * config/rs6000/t-rs6000 (rs6000.o): Add rs6000-cpus.def as a > dependency. > > -- > Michael Meissner, IBM > 5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA > meissner@linux.vnet.ibm.com fax +1 (978) 399-6899 ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f 2012-10-17 19:42 ` David Edelsohn @ 2012-10-17 20:48 ` Michael Meissner 2012-10-18 15:46 ` Eric Botcazou 0 siblings, 1 reply; 13+ messages in thread From: Michael Meissner @ 2012-10-17 20:48 UTC (permalink / raw) To: David Edelsohn Cc: Michael Meissner, gcc-patches, bergner, segher, iain, andreast-list [-- Attachment #1: Type: text/plain, Size: 6613 bytes --] This is the patch I checked in, after adjusting it for the change in opth-gen.awk yesterday to use TARGET_<xxx> instead of OPTION_<xxx> for target flags. I also added a comment David asked for about why TARGET_DEFAULT was being set, when the previous code did not have it (since it was set via the hook that sets target_flags). 2012-10-17 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.opt (rs6000_isa_flags): New flag word to replace target_flags that gives us 63 possible switches. (x_rs6000_isa_flags): Save area for rs6000_isa_flags. (x_rs6000_isa_flags_explicit): Save area for rs6000_isa_flags_explicit. (rs6000_target_flags_explicit): Delete in favor of x_rs6000_isa_flags_explicit. (-mpowerpc64): Change all switches that used to be in target_flags to now be in rs6000_isa_flags. In using rs6000_isa_flags, the options machinary will generate names of the form OPITON_<xxx> instead of TARGET_<xxx> and OPTION_MASK_<xxx> instead of MASK_<xxx>. (-mpowerpc-gpopt): Likewise. (-mpowerpc-gfxopt): Likewise. (-mmfcrf): Likewise. (-mpopcntb): Likewise. (-mfprnd): Likewise. (-mcmpb): Likewise. (-mmfpgpr): Likewise. (-maltivec): Likewise. (-mhard-dfp): Likewise. (-mmulhw): Likewise. (-mdlmzb): Likewise. (-mmultiple): Likewise. (-mstring): Likewise. (-msoft-float): Likewise. (-mhard-float): Likewise. (-mpopcntd): Likewise. (-mvsx): Likewise. (-mno-update): Likewise. (-mupdate): Likewise. (-mrecip-precision): Likewise. (-mminimal-toc): Likewise. (-misel): Likewise. * config/rs6000/aix64.opt (-maix64): Likewise. (-maix32): Likewise. * config/rs6000/sysv4.opt (-mstrict-align): Likewise. (-mrelocatable): Likewise. (-mlittle-endian): Likewise. (-mlittle): Likewise. (-mbig-endian): LIkewise. (-mbig): Likewise. (-meabi): Likewise. (-m64): Likewise. (-m32): Likewise. * config/rs6000/darwin.opt (-m64): Likewise. (-m32): Likewise. * config/rs6000/rs6000-cpus.def (ISA_2_1_MASKS): Move the various masks used in rs6000.c here, since they are more logically in this file. Convert from being enums to just #defines, since the types of these masks is now HOST_WIDE_INT instead of int. For POWERPC_MASKS, add MASK_SOFT_FLOAT, since the only use case or'ed in the mask. Change the use in rs6000.c not to do the OR of MASK_SOFT_FLOAT. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. * config/rs6000/rs6000.c (ISA_2_1_MASKS): Likewise. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. (rs6000_option_override_internal): Likewise. * config/rs6000/rs6000.c (darwin_rs6000_override_options): Change all uses of target_flags to rs6000_isa_flags. Change all uses of target_flags_explicit to rs6000_isa_flags_explicit. Change the use of MASK_<xxx> to OPTION_MASK_<xxx> that options.h defines when we use a secondary flags word. Save/restore/print the new flags word when switching contexts with different target attributes. (rs6000_option_override_internal): Likewise. (rs6000_darwin_file_start): Likewise. (rs6000_opt_masks): Likewise. (rs6000_inner_target_options): Likewise. (rs6000_pragma_target_parse): Likewise. (rs6000_set_current_function): Likewise. (rs6000_function_specific_save): Likewise. (rs6000_function_specific_restore): Likewise. (rs6000_function_specific_print): Likewise. (rs6000_can_inline_p): Likewise. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. (rs6000_cpu_cpp_builtins): Likewise. * common/config/rs6000/rs6000-driver.c (rs6000_handle_option): Likewise. * config/rs6000/rs6000.h (MASK_ALTIVEC): In moving to using Var(...) for all of the isa switches, the options machinery now uses OPTION_MASK_<xxx> instead of MASK_<xxx> for the mask name. Use #define to map the old name into the new name. For switches that are defined in aix64.opt, sysv4.opt, and darwin.opt, only do the definition if those switches were defined. (MASK_ALTIVEC): Likewise. (MASK_CMPB): Likewise. (MASK_DFP): Likewise. (MASK_DLMZB): Likewise. (MASK_EABI): Likewise. (MASK_FPRND): Likewise. (MASK_HARD_FLOAT): Likewise. (MASK_ISEL): Likewise. (MASK_MFCRF): Likewise. (MASK_MFPGPR): Likewise. (MASK_MULHW): Likewise. (MASK_MULTIPLE): Likewise. (MASK_NO_UPDATE): Likewise. (MASK_POPCNTB): Likewise. (MASK_POPCNTD): Likewise. (MASK_PPC_GFXOPT): Likewise. (MASK_PPC_GPOPT): Likewise. (MASK_RECIP_PRECISION): Likewise. (MASK_SOFT_FLOAT): Likewise. (MASK_STRICT_ALIGN): Likewise. (MASK_STRING): Likewise. (MASK_UPDATE): Likewise. (MASK_VSX): Likewise. (MASK_POWERPC64): Likewise. (MASK_64BIT): Likewise. (MASK_RELOCATABLE): Likewise. (MASK_LITTLE_ENDIAN): Likewise. (MASK_MINIMAL_TOC): Likewise. (MASK_REGNAMES): Likewise. (MASK_PROTOTYPE): Likewise. (rs6000_isa_flags_explicit): Define in terms of the global_options_set structure. * gcc/config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Change use of target_flags to rs6000_isa_flags, target_flags_explicit to rs6000_isa_flags_explicit, and MASK_<xxx> to OPTION_MASK_<xxx>. * gcc/config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/freebsd64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * gcc/config/rs6000/linux64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (OPTION_LITTLE_ENDIAN): Likewise. (OPTION_RELOCATABLE): Likewise. (OPTION_EABI): Likewise. (OPTION_PROTOTYPE): Likewise. * gcc/config/rs6000/linux.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * gcc/config/rs6000/option-defaults.h (OPTION_MASK_64BIT): Likewise. (OPT_ARCH32): Likewise. (OPT_ARCH64): Likewise. * gcc/config/rs6000/sysv4.h (TARGET_TOC): Likewise. (SUBTARGET_OVERRIDE_OPTIONS): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (TARGET_OS_SYSV_CPP_BUILTINS): Likewise. * config/rs6000/t-rs6000 (rs6000.o): Add rs6000-cpus.def as a dependency. -- Michael Meissner, IBM 5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA meissner@linux.vnet.ibm.com fax +1 (978) 399-6899 [-- Attachment #2: gcc-power7.patch366b --] [-- Type: text/plain, Size: 53559 bytes --] Index: gcc/config/rs6000/aix53.h =================================================================== --- gcc/config/rs6000/aix53.h (revision 192544) +++ gcc/config/rs6000/aix53.h (revision 192545) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/linux.h =================================================================== --- gcc/config/rs6000/linux.h (revision 192544) +++ gcc/config/rs6000/linux.h (revision 192545) @@ -109,7 +109,7 @@ -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #define TARGET_POSIX_IO Index: gcc/config/rs6000/t-rs6000 =================================================================== --- gcc/config/rs6000/t-rs6000 (revision 192544) +++ gcc/config/rs6000/t-rs6000 (revision 192545) @@ -26,7 +26,8 @@ rs6000.o: $(CONFIG_H) $(SYSTEM_H) corety $(OBSTACK_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) except.h function.h \ output.h dbxout.h $(BASIC_BLOCK_H) toplev.h $(GGC_H) $(HASHTAB_H) \ $(TM_P_H) $(TARGET_H) $(TARGET_DEF_H) langhooks.h reload.h gt-rs6000.h \ - cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) dumpfile.h + cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) dumpfile.h \ + $(srcdir)/config/rs6000/rs6000-cpus.def rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.c \ $(srcdir)/config/rs6000/rs6000-protos.h \ Index: gcc/config/rs6000/aix43.h =================================================================== --- gcc/config/rs6000/aix43.h (revision 192544) +++ gcc/config/rs6000/aix43.h (revision 192545) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/darwin.opt =================================================================== --- gcc/config/rs6000/darwin.opt (revision 192544) +++ gcc/config/rs6000/darwin.opt (revision 192545) @@ -34,9 +34,9 @@ findirect-data Driver RejectNegative Alias(mfix-and-continue) m64 -Target RejectNegative Negative(m32) Mask(64BIT) +Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target RejectNegative Negative(m64) InverseMask(64BIT) +Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code Index: gcc/config/rs6000/rs6000.opt =================================================================== --- gcc/config/rs6000/rs6000.opt (revision 192544) +++ gcc/config/rs6000/rs6000.opt (revision 192545) @@ -22,6 +22,17 @@ HeaderInclude config/rs6000/rs6000-opts.h +;; ISA flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags + +;; Miscellaneous flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags_explicit + ;; Current processor TargetVariable enum processor_type rs6000_cpu = PROCESSOR_PPC603 @@ -86,80 +97,76 @@ HOST_WIDE_INT rs6000_builtin_mask TargetVariable unsigned int rs6000_debug -;; Save for target_flags_explicit -TargetSave -int rs6000_target_flags_explicit - ;; This option existed in the past, but now is always on. mpowerpc Target RejectNegative Undocumented Ignore mpowerpc64 -Target Report Mask(POWERPC64) +Target Report Mask(POWERPC64) Var(rs6000_isa_flags) Use PowerPC-64 instruction set mpowerpc-gpopt -Target Report Mask(PPC_GPOPT) Save +Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) Use PowerPC General Purpose group optional instructions mpowerpc-gfxopt -Target Report Mask(PPC_GFXOPT) Save +Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) Use PowerPC Graphics group optional instructions mmfcrf -Target Report Mask(MFCRF) Save +Target Report Mask(MFCRF) Var(rs6000_isa_flags) Use PowerPC V2.01 single field mfcr instruction mpopcntb -Target Report Mask(POPCNTB) Save +Target Report Mask(POPCNTB) Var(rs6000_isa_flags) Use PowerPC V2.02 popcntb instruction mfprnd -Target Report Mask(FPRND) Save +Target Report Mask(FPRND) Var(rs6000_isa_flags) Use PowerPC V2.02 floating point rounding instructions mcmpb -Target Report Mask(CMPB) Save +Target Report Mask(CMPB) Var(rs6000_isa_flags) Use PowerPC V2.05 compare bytes instruction mmfpgpr -Target Report Mask(MFPGPR) Save +Target Report Mask(MFPGPR) Var(rs6000_isa_flags) Use extended PowerPC V2.05 move floating point to/from GPR instructions maltivec -Target Report Mask(ALTIVEC) Save +Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) Use AltiVec instructions mhard-dfp -Target Report Mask(DFP) Save +Target Report Mask(DFP) Var(rs6000_isa_flags) Use decimal floating point instructions mmulhw -Target Report Mask(MULHW) Save +Target Report Mask(MULHW) Var(rs6000_isa_flags) Use 4xx half-word multiply instructions mdlmzb -Target Report Mask(DLMZB) Save +Target Report Mask(DLMZB) Var(rs6000_isa_flags) Use 4xx string-search dlmzb instruction mmultiple -Target Report Mask(MULTIPLE) Save +Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) Generate load/store multiple instructions mstring -Target Report Mask(STRING) Save +Target Report Mask(STRING) Var(rs6000_isa_flags) Generate string instructions for block moves msoft-float -Target Report RejectNegative Mask(SOFT_FLOAT) +Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) Do not use hardware floating point mhard-float -Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) +Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) Use hardware floating point mpopcntd -Target Report Mask(POPCNTD) Save +Target Report Mask(POPCNTD) Var(rs6000_isa_flags) Use PowerPC V2.06 popcntd instruction mfriz @@ -171,7 +178,7 @@ Target RejectNegative Joined Var(rs6000_ Vector library ABI to use mvsx -Target Report Mask(VSX) Save +Target Report Mask(VSX) Var(rs6000_isa_flags) Use vector/scalar (VSX) instructions mvsx-scalar-double @@ -211,11 +218,11 @@ Target Undocumented Report Var(TARGET_VE ; Explicitly control whether we vectorize the builtins or not. mno-update -Target Report RejectNegative Mask(NO_UPDATE) Save +Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) Do not generate load/store with update instructions mupdate -Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) +Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) Generate load/store with update instructions msingle-pic-base @@ -258,7 +265,7 @@ Target Report RejectNegative Joined Var( Generate software reciprocal divide and square root for better throughput. mrecip-precision -Target Report Mask(RECIP_PRECISION) Save +Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) Assume that the reciprocal estimate instructions provide more accuracy. mno-fp-in-toc @@ -285,7 +292,7 @@ Place symbol+offset constants in TOC ; This is at the cost of having 2 extra loads and one extra store per ; function, and one less allocable register. mminimal-toc -Target Report Mask(MINIMAL_TOC) +Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) Use only one TOC entry per procedure mfull-toc @@ -309,7 +316,7 @@ Target Report Var(rs6000_block_move_inli Specify how many bytes should be moved inline before calling out to memcpy/memmove misel -Target Report Mask(ISEL) Save +Target Report Mask(ISEL) Var(rs6000_isa_flags) Generate isel instructions misel=no Index: gcc/config/rs6000/rs6000-c.c =================================================================== --- gcc/config/rs6000/rs6000-c.c (revision 192544) +++ gcc/config/rs6000/rs6000-c.c (revision 192545) @@ -295,31 +295,31 @@ rs6000_target_modify_macros (bool define (define_p) ? "define" : "undef", flags, bu_mask); - /* target_flags based options. */ + /* rs6000_isa_flags based options. */ rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); - if ((flags & MASK_PPC_GPOPT) != 0) + if ((flags & OPTION_MASK_PPC_GPOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ"); - if ((flags & MASK_PPC_GFXOPT) != 0) + if ((flags & OPTION_MASK_PPC_GFXOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR"); - if ((flags & MASK_POWERPC64) != 0) + if ((flags & OPTION_MASK_POWERPC64) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"); - if ((flags & MASK_MFCRF) != 0) + if ((flags & OPTION_MASK_MFCRF) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4"); - if ((flags & MASK_POPCNTB) != 0) + if ((flags & OPTION_MASK_POPCNTB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5"); - if ((flags & MASK_FPRND) != 0) + if ((flags & OPTION_MASK_FPRND) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X"); - if ((flags & MASK_CMPB) != 0) + if ((flags & OPTION_MASK_CMPB) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); - if ((flags & MASK_MFPGPR) != 0) + if ((flags & OPTION_MASK_MFPGPR) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X"); - if ((flags & MASK_POPCNTD) != 0) + if ((flags & OPTION_MASK_POPCNTD) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); - if ((flags & MASK_SOFT_FLOAT) != 0) + if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); - if ((flags & MASK_RECIP_PRECISION) != 0) + if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__"); - if ((flags & MASK_ALTIVEC) != 0) + if ((flags & OPTION_MASK_ALTIVEC) != 0) { const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__"; rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__"); @@ -329,7 +329,7 @@ rs6000_target_modify_macros (bool define if (!flag_iso) rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__"); } - if ((flags & MASK_VSX) != 0) + if ((flags & OPTION_MASK_VSX) != 0) rs6000_define_or_undefine_macro (define_p, "__VSX__"); /* options from the builtin masks. */ @@ -345,7 +345,7 @@ void rs6000_cpu_cpp_builtins (cpp_reader *pfile) { /* Define all of the common macros. */ - rs6000_target_modify_macros (true, target_flags, + rs6000_target_modify_macros (true, rs6000_isa_flags, rs6000_builtin_mask_calculate ()); if (TARGET_FRE) Index: gcc/config/rs6000/linux64.h =================================================================== --- gcc/config/rs6000/linux64.h (revision 192544) +++ gcc/config/rs6000/linux64.h (revision 192545) @@ -81,7 +81,7 @@ extern int dot_symbols; -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "linux" @@ -103,14 +103,14 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ - if (target_flags & MASK_RELOCATABLE) \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error (INVALID_64BIT, "relocatable"); \ } \ - if (target_flags & MASK_EABI) \ + if (rs6000_isa_flags & OPTION_MASK_EABI) \ { \ - target_flags &= ~MASK_EABI; \ + rs6000_isa_flags &= ~OPTION_MASK_EABI; \ error (INVALID_64BIT, "eabi"); \ } \ if (TARGET_PROTOTYPE) \ @@ -118,12 +118,13 @@ extern int dot_symbols; target_prototype = 0; \ error (INVALID_64BIT, "prototype"); \ } \ - if ((target_flags & MASK_POWERPC64) == 0) \ + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ error ("-m64 requires a PowerPC64 cpu"); \ } \ - if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ + if ((rs6000_isa_flags_explicit \ + & OPTION_MASK_MINIMAL_TOC) != 0) \ { \ if (global_options_set.x_rs6000_current_cmodel \ && rs6000_current_cmodel != CMODEL_SMALL) \ @@ -213,20 +214,20 @@ extern int dot_symbols; #ifndef RS6000_BI_ARCH /* 64-bit PowerPC Linux is always big-endian. */ -#undef TARGET_LITTLE_ENDIAN -#define TARGET_LITTLE_ENDIAN 0 +#undef OPTION_LITTLE_ENDIAN +#define OPTION_LITTLE_ENDIAN 0 /* 64-bit PowerPC Linux always has a TOC. */ #undef TARGET_TOC #define TARGET_TOC 1 /* Some things from sysv4.h we don't do when 64 bit. */ -#undef TARGET_RELOCATABLE -#define TARGET_RELOCATABLE 0 -#undef TARGET_EABI -#define TARGET_EABI 0 -#undef TARGET_PROTOTYPE -#define TARGET_PROTOTYPE 0 +#undef OPTION_RELOCATABLE +#define OPTION_RELOCATABLE 0 +#undef OPTION_EABI +#define OPTION_EABI 0 +#undef OPTION_PROTOTYPE +#define OPTION_PROTOTYPE 0 #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP 0 Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 192544) +++ gcc/config/rs6000/rs6000.c (revision 192545) @@ -1121,7 +1121,8 @@ static const struct attribute_spec rs600 { NULL, 0, 0, false, false, false, NULL, false } }; \f -#ifndef MASK_STRICT_ALIGN +#ifndef OPTION_MASK_STRICT_ALIGN +#define OPTION_MASK_STRICT_ALIGN 0 #define MASK_STRICT_ALIGN 0 #endif #ifndef TARGET_PROFILE_KERNEL @@ -1464,48 +1465,7 @@ static const struct attribute_spec rs600 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok \f -/* Simplifications for entries below. */ - -enum { - POWERPC_7400_MASK = MASK_PPC_GFXOPT | MASK_ALTIVEC -}; - -/* Some OSs don't support saving the high part of 64-bit registers on context - switch. Other OSs don't support saving Altivec registers. On those OSs, we - don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants - either, the user must explicitly specify them and we won't interfere with - the user's specification. */ - -enum { - POWERPC_MASKS = (MASK_PPC_GPOPT | MASK_STRICT_ALIGN - | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC - | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW - | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP - | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE - | MASK_RECIP_PRECISION) -}; - -/* Masks for instructions set at various powerpc ISAs. */ -enum { - ISA_2_1_MASKS = MASK_MFCRF, - ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB), - ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND), - - /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add - ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, - fre, fsqrt, etc. were no longer documented as optional. Group masks by - server and embedded. */ - ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION - | MASK_PPC_GFXOPT | MASK_PPC_GPOPT), - ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP), - - /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but - altivec is a win so enable it. */ - ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD), - ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC - | MASK_VSX) -}; - +/* Processor table. */ struct rs6000_ptt { const char *const name; /* Canonical processor name. */ @@ -2357,21 +2317,21 @@ darwin_rs6000_override_options (void) if (TARGET_64BIT && ! TARGET_POWERPC64) { - target_flags |= MASK_POWERPC64; + rs6000_isa_flags |= OPTION_MASK_POWERPC64; warning (0, "-m64 requires PowerPC64 architecture, enabling"); } if (flag_mkernel) { rs6000_default_long_calls = 1; - target_flags |= MASK_SOFT_FLOAT; + rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; } /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes Altivec. */ if (!flag_mkernel && !flag_apple_kext && TARGET_64BIT - && ! (target_flags_explicit & MASK_ALTIVEC)) - target_flags |= MASK_ALTIVEC; + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)) + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; /* Unless the user (not the configurer) has explicitly overridden it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to @@ -2379,10 +2339,10 @@ darwin_rs6000_override_options (void) if (!flag_mkernel && !flag_apple_kext && strverscmp (darwin_macosx_version_min, "10.5") >= 0 - && ! (target_flags_explicit & MASK_ALTIVEC) + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC) && ! global_options_set.x_rs6000_cpu_index) { - target_flags |= MASK_ALTIVEC; + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; } } #endif @@ -2463,18 +2423,24 @@ rs6000_option_override_internal (bool gl rs6000_pointer_size = 32; } - set_masks = POWERPC_MASKS | MASK_SOFT_FLOAT; + /* Some OSs don't support saving the high part of 64-bit registers on context + switch. Other OSs don't support saving Altivec registers. On those OSs, + we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings; + if the user wants either, the user must explicitly specify them and we + won't interfere with the user's specification. */ + + set_masks = POWERPC_MASKS; #ifdef OS_MISSING_POWERPC64 if (OS_MISSING_POWERPC64) - set_masks &= ~MASK_POWERPC64; + set_masks &= ~OPTION_MASK_POWERPC64; #endif #ifdef OS_MISSING_ALTIVEC if (OS_MISSING_ALTIVEC) - set_masks &= ~MASK_ALTIVEC; + set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX); #endif /* Don't override by the processor default if given explicitly. */ - set_masks &= ~target_flags_explicit; + set_masks &= ~rs6000_isa_flags_explicit; /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed the cpu in a target attribute or pragma, but did not specify a tuning @@ -2512,13 +2478,20 @@ rs6000_option_override_internal (bool gl TARGET_DEFAULT. */ if (have_cpu) { - target_flags &= ~set_masks; - target_flags |= (processor_target_table[cpu_index].target_enable - & set_masks); + rs6000_isa_flags &= ~set_masks; + rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable + & set_masks); } else - target_flags |= (processor_target_table[cpu_index].target_enable - & ~target_flags_explicit); + rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable + & ~rs6000_isa_flags_explicit); + + /* If no -mcpu=<xxx>, inherit any default options that were cleared via + POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize + target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched + to using rs6000_isa_flags, we need to do the initialization here. */ + if (!have_cpu) + rs6000_isa_flags |= (TARGET_DEFAULT & ~rs6000_isa_flags_explicit); if (rs6000_tune_index >= 0) tune_index = rs6000_tune_index; @@ -2603,7 +2576,8 @@ rs6000_option_override_internal (bool gl use instructions that would be microcoded on the Cell, use the load/store multiple and string instructions. */ if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode) - target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); + rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE + | OPTION_MASK_STRING); /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu is a 750, because the hardware doesn't support the @@ -2615,15 +2589,15 @@ rs6000_option_override_internal (bool gl { if (TARGET_MULTIPLE) { - target_flags &= ~MASK_MULTIPLE; - if ((target_flags_explicit & MASK_MULTIPLE) != 0) + rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE; + if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0) warning (0, "-mmultiple is not supported on little endian systems"); } if (TARGET_STRING) { - target_flags &= ~MASK_STRING; - if ((target_flags_explicit & MASK_STRING) != 0) + rs6000_isa_flags &= ~OPTION_MASK_STRING; + if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0) warning (0, "-mstring is not supported on little endian systems"); } } @@ -2635,10 +2609,10 @@ rs6000_option_override_internal (bool gl if (!TARGET_HARD_FLOAT || !TARGET_FPRS || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx requires hardware floating point"); else - target_flags &= ~ MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; } else if (TARGET_PAIRED_FLOAT) msg = N_("-mvsx and -mpaired are incompatible"); @@ -2649,9 +2623,10 @@ rs6000_option_override_internal (bool gl msg = N_("-mvsx used with little endian code"); else if (TARGET_AVOID_XFORM > 0) msg = N_("-mvsx needs indexed addressing"); - else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC)) + else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit + & OPTION_MASK_ALTIVEC)) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx and -mno-altivec are incompatible"); else msg = N_("-mno-altivec disables vsx"); @@ -2660,27 +2635,27 @@ rs6000_option_override_internal (bool gl if (msg) { warning (0, msg); - target_flags &= ~ MASK_VSX; - target_flags_explicit |= MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; + rs6000_isa_flags_explicit |= OPTION_MASK_VSX; } } /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-<option> to disable the code. */ if (TARGET_VSX) - target_flags |= (ISA_2_6_MASKS_SERVER & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit); else if (TARGET_POPCNTD) - target_flags |= (ISA_2_6_MASKS_EMBEDDED & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit); else if (TARGET_DFP) - target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~rs6000_isa_flags_explicit); else if (TARGET_CMPB) - target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit); else if (TARGET_FPRND) - target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_4_MASKS & ~rs6000_isa_flags_explicit); else if (TARGET_POPCNTB) - target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit); + rs6000_isa_flags |= (ISA_2_2_MASKS & ~rs6000_isa_flags_explicit); else if (TARGET_ALTIVEC) - target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit); + rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit); /* E500mc does "better" if we inline more aggressively. Respect the user's opinion, though. */ @@ -2759,7 +2734,8 @@ rs6000_option_override_internal (bool gl unless the altivec ABI was set. This is set by default for 64-bit, but not for 32-bit. */ if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi) - target_flags &= ~((MASK_VSX | MASK_ALTIVEC) & ~target_flags_explicit); + rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC) + & ~rs6000_isa_flags_explicit); /* Enable Altivec ABI for AIX -maltivec. */ if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX)) @@ -2837,14 +2813,14 @@ rs6000_option_override_internal (bool gl rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE; rs6000_double_float = TARGET_E500_DOUBLE; - target_flags &= ~MASK_STRING; + rs6000_isa_flags &= ~OPTION_MASK_STRING; break; default: - if (have_cpu && !(target_flags_explicit & MASK_ISEL)) - target_flags &= ~MASK_ISEL; + if (have_cpu && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL)) + rs6000_isa_flags &= ~OPTION_MASK_ISEL; break; } @@ -25330,7 +25306,7 @@ rs6000_darwin_file_start (void) i = 0; while (mapping[i].arg != NULL && strcmp (mapping[i].arg, cpu_id) != 0 - && (mapping[i].if_set & target_flags) == 0) + && (mapping[i].if_set & rs6000_isa_flags) == 0) i++; fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name); @@ -27431,48 +27407,48 @@ struct rs6000_opt_mask { static struct rs6000_opt_mask const rs6000_opt_masks[] = { - { "altivec", MASK_ALTIVEC, false, true }, - { "cmpb", MASK_CMPB, false, true }, - { "dlmzb", MASK_DLMZB, false, true }, - { "fprnd", MASK_FPRND, false, true }, - { "hard-dfp", MASK_DFP, false, true }, - { "isel", MASK_ISEL, false, true }, - { "mfcrf", MASK_MFCRF, false, true }, - { "mfpgpr", MASK_MFPGPR, false, true }, - { "mulhw", MASK_MULHW, false, true }, - { "multiple", MASK_MULTIPLE, false, true }, - { "update", MASK_NO_UPDATE, true , true }, - { "popcntb", MASK_POPCNTB, false, true }, - { "popcntd", MASK_POPCNTD, false, true }, - { "powerpc-gfxopt", MASK_PPC_GFXOPT, false, true }, - { "powerpc-gpopt", MASK_PPC_GPOPT, false, true }, - { "recip-precision", MASK_RECIP_PRECISION, false, true }, - { "string", MASK_STRING, false, true }, - { "vsx", MASK_VSX, false, true }, -#ifdef MASK_64BIT + { "altivec", OPTION_MASK_ALTIVEC, false, true }, + { "cmpb", OPTION_MASK_CMPB, false, true }, + { "dlmzb", OPTION_MASK_DLMZB, false, true }, + { "fprnd", OPTION_MASK_FPRND, false, true }, + { "hard-dfp", OPTION_MASK_DFP, false, true }, + { "isel", OPTION_MASK_ISEL, false, true }, + { "mfcrf", OPTION_MASK_MFCRF, false, true }, + { "mfpgpr", OPTION_MASK_MFPGPR, false, true }, + { "mulhw", OPTION_MASK_MULHW, false, true }, + { "multiple", OPTION_MASK_MULTIPLE, false, true }, + { "update", OPTION_MASK_NO_UPDATE, true , true }, + { "popcntb", OPTION_MASK_POPCNTB, false, true }, + { "popcntd", OPTION_MASK_POPCNTD, false, true }, + { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true }, + { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true }, + { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true }, + { "string", OPTION_MASK_STRING, false, true }, + { "vsx", OPTION_MASK_VSX, false, true }, +#ifdef OPTION_MASK_64BIT #if TARGET_AIX_OS - { "aix64", MASK_64BIT, false, false }, - { "aix32", MASK_64BIT, true, false }, + { "aix64", OPTION_MASK_64BIT, false, false }, + { "aix32", OPTION_MASK_64BIT, true, false }, #else - { "64", MASK_64BIT, false, false }, - { "32", MASK_64BIT, true, false }, + { "64", OPTION_MASK_64BIT, false, false }, + { "32", OPTION_MASK_64BIT, true, false }, #endif #endif -#ifdef MASK_EABI - { "eabi", MASK_EABI, false, false }, +#ifdef OPTION_MASK_EABI + { "eabi", OPTION_MASK_EABI, false, false }, #endif -#ifdef MASK_LITTLE_ENDIAN - { "little", MASK_LITTLE_ENDIAN, false, false }, - { "big", MASK_LITTLE_ENDIAN, true, false }, +#ifdef OPTION_MASK_LITTLE_ENDIAN + { "little", OPTION_MASK_LITTLE_ENDIAN, false, false }, + { "big", OPTION_MASK_LITTLE_ENDIAN, true, false }, #endif -#ifdef MASK_RELOCATABLE - { "relocatable", MASK_RELOCATABLE, false, false }, +#ifdef OPTION_MASK_RELOCATABLE + { "relocatable", OPTION_MASK_RELOCATABLE, false, false }, #endif -#ifdef MASK_STRICT_ALIGN - { "strict-align", MASK_STRICT_ALIGN, false, false }, +#ifdef OPTION_MASK_STRICT_ALIGN + { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false }, #endif - { "soft-float", MASK_SOFT_FLOAT, false, false }, - { "string", MASK_STRING, false, false }, + { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false }, + { "string", OPTION_MASK_STRING, false, false }, }; /* Builtin mask mapping for printing the flags. */ @@ -27583,20 +27559,20 @@ rs6000_inner_target_options (tree args, else { error_p = false; - target_flags_explicit |= mask; + rs6000_isa_flags_explicit |= mask; /* VSX needs altivec, so -mvsx automagically sets altivec. */ - if (mask == MASK_VSX && !invert) - mask |= MASK_ALTIVEC; + if (mask == OPTION_MASK_VSX && !invert) + mask |= OPTION_MASK_ALTIVEC; if (rs6000_opt_masks[i].invert) invert = !invert; if (invert) - target_flags &= ~mask; + rs6000_isa_flags &= ~mask; else - target_flags |= mask; + rs6000_isa_flags |= mask; } break; } @@ -27851,14 +27827,14 @@ rs6000_pragma_target_parse (tree args, t { prev_opt = TREE_TARGET_OPTION (prev_tree); prev_bumask = prev_opt->x_rs6000_builtin_mask; - prev_flags = prev_opt->x_target_flags; + prev_flags = prev_opt->x_rs6000_isa_flags; cur_opt = TREE_TARGET_OPTION (cur_tree); - cur_flags = cur_opt->x_target_flags; + cur_flags = cur_opt->x_rs6000_isa_flags; cur_bumask = cur_opt->x_rs6000_builtin_mask; diff_bumask = (prev_bumask ^ cur_bumask); - diff_flags = (prev_flags ^ cur_flags); + diff_flags = (prev_flags ^ cur_flags); if ((diff_flags != 0) || (diff_bumask != 0)) { @@ -27961,7 +27937,8 @@ rs6000_set_current_function (tree fndecl static void rs6000_function_specific_save (struct cl_target_option *ptr) { - ptr->rs6000_target_flags_explicit = target_flags_explicit; + ptr->x_rs6000_isa_flags = rs6000_isa_flags; + ptr->x_rs6000_isa_flags_explicit = rs6000_isa_flags_explicit; } /* Restore the current options */ @@ -27969,7 +27946,8 @@ rs6000_function_specific_save (struct cl static void rs6000_function_specific_restore (struct cl_target_option *ptr) { - target_flags_explicit = ptr->rs6000_target_flags_explicit; + rs6000_isa_flags = ptr->x_rs6000_isa_flags; + rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit; (void) rs6000_option_override_internal (false); } @@ -27980,10 +27958,10 @@ rs6000_function_specific_print (FILE *fi struct cl_target_option *ptr) { rs6000_print_isa_options (file, indent, "Isa options set", - ptr->x_target_flags); + ptr->x_rs6000_isa_flags); rs6000_print_isa_options (file, indent, "Isa options explicit", - ptr->rs6000_target_flags_explicit); + ptr->x_rs6000_isa_flags_explicit); } /* Helper function to print the current isa or misc options on a line. */ @@ -28093,8 +28071,8 @@ rs6000_can_inline_p (tree caller, tree c /* Callee's options should a subset of the caller's, i.e. a vsx function can inline an altivec function but a non-vsx function can't inline a vsx function. */ - if ((caller_opts->x_target_flags & callee_opts->x_target_flags) - == callee_opts->x_target_flags) + if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags) + == callee_opts->x_rs6000_isa_flags) ret = true; } Index: gcc/config/rs6000/aix52.h =================================================================== --- gcc/config/rs6000/aix52.h (revision 192544) +++ gcc/config/rs6000/aix52.h (revision 192545) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 192544) +++ gcc/config/rs6000/rs6000.h (revision 192545) @@ -465,6 +465,64 @@ extern int rs6000_vector_align[]; #define TARGET_FCTIDUZ TARGET_POPCNTD #define TARGET_FCTIWUZ TARGET_POPCNTD +/* In switching from using target_flags to using rs6000_isa_flags, the options + machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map + OPTION_MASK_<xxx> back into MASK_<xxx>. */ +#define MASK_ALTIVEC OPTION_MASK_ALTIVEC +#define MASK_CMPB OPTION_MASK_CMPB +#define MASK_DFP OPTION_MASK_DFP +#define MASK_DLMZB OPTION_MASK_DLMZB +#define MASK_EABI OPTION_MASK_EABI +#define MASK_FPRND OPTION_MASK_FPRND +#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT +#define MASK_ISEL OPTION_MASK_ISEL +#define MASK_MFCRF OPTION_MASK_MFCRF +#define MASK_MFPGPR OPTION_MASK_MFPGPR +#define MASK_MULHW OPTION_MASK_MULHW +#define MASK_MULTIPLE OPTION_MASK_MULTIPLE +#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE +#define MASK_POPCNTB OPTION_MASK_POPCNTB +#define MASK_POPCNTD OPTION_MASK_POPCNTD +#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT +#define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT +#define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION +#define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT +#define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN +#define MASK_STRING OPTION_MASK_STRING +#define MASK_UPDATE OPTION_MASK_UPDATE +#define MASK_VSX OPTION_MASK_VSX + +#ifndef IN_LIBGCC2 +#define MASK_POWERPC64 OPTION_MASK_POWERPC64 +#endif + +#ifdef TARGET_64BIT +#define MASK_64BIT OPTION_MASK_64BIT +#endif + +#ifdef TARGET_RELOCATABLE +#define MASK_RELOCATABLE OPTION_MASK_RELOCATABLE +#endif + +#ifdef TARGET_LITTLE_ENDIAN +#define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN +#endif + +#ifdef TARGET_MINIMAL_TOC +#define MASK_MINIMAL_TOC OPTION_MASK_MINIMAL_TOC +#endif + +#ifdef TARGET_REGNAMES +#define MASK_REGNAMES OPTION_MASK_REGNAMES +#endif + +#ifdef TARGET_PROTOTYPE +#define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE +#endif + +/* Explicit ISA options that were set. */ +#define rs6000_isa_flags_explicit global_options_set.x_rs6000_isa_flags + /* For power systems, we want to enable Altivec and VSX builtins even if the user did not use -maltivec or -mvsx to allow the builtins to be used inside of #pragma GCC target or the target attribute to change the code level for a Index: gcc/config/rs6000/aix64.opt =================================================================== --- gcc/config/rs6000/aix64.opt (revision 192544) +++ gcc/config/rs6000/aix64.opt (revision 192545) @@ -20,11 +20,11 @@ ; <http://www.gnu.org/licenses/>. maix64 -Target Report RejectNegative Negative(maix32) Mask(64BIT) +Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags) Compile for 64-bit pointers maix32 -Target Report RejectNegative Negative(maix64) InverseMask(64BIT) +Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags) Compile for 32-bit pointers mpe Index: gcc/config/rs6000/freebsd64.h =================================================================== --- gcc/config/rs6000/freebsd64.h (revision 192544) +++ gcc/config/rs6000/freebsd64.h (revision 192545) @@ -57,7 +57,7 @@ extern int dot_symbols; -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "freebsd" @@ -79,14 +79,14 @@ extern int dot_symbols; error (INVALID_64BIT, "call"); \ } \ dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \ - if (target_flags & MASK_RELOCATABLE) \ + if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error (INVALID_64BIT, "relocatable"); \ } \ - if (target_flags & MASK_EABI) \ + if (rs6000_isa_flags & OPTION_MASK_EABI) \ { \ - target_flags &= ~MASK_EABI; \ + rs6000_isa_flags &= ~OPTION_MASK_EABI; \ error (INVALID_64BIT, "eabi"); \ } \ if (TARGET_PROTOTYPE) \ @@ -94,12 +94,13 @@ extern int dot_symbols; target_prototype = 0; \ error (INVALID_64BIT, "prototype"); \ } \ - if ((target_flags & MASK_POWERPC64) == 0) \ + if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ error ("-m64 requires a PowerPC64 cpu"); \ } \ - if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \ + if ((rs6000_isa_flags_explicit \ + & OPTION_MASK_MINIMAL_TOC) != 0) \ { \ if (global_options_set.x_rs6000_current_cmodel \ && rs6000_current_cmodel != CMODEL_SMALL) \ Index: gcc/config/rs6000/aix61.h =================================================================== --- gcc/config/rs6000/aix61.h (revision 192544) +++ gcc/config/rs6000/aix61.h (revision 192545) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \ Index: gcc/config/rs6000/sysv4.opt =================================================================== --- gcc/config/rs6000/sysv4.opt (revision 192544) +++ gcc/config/rs6000/sysv4.opt (revision 192545) @@ -49,12 +49,12 @@ Target Report Var(TARGET_NO_BITFIELD_TYP Align to the base type of the bit-field mstrict-align -Target Report Mask(STRICT_ALIGN) +Target Report Mask(STRICT_ALIGN) Var(rs6000_isa_flags) Align to the base type of the bit-field Don't assume that unaligned accesses are handled by the system mrelocatable -Target Report Mask(RELOCATABLE) +Target Report Mask(RELOCATABLE) Var(rs6000_isa_flags) Produce code relocatable at runtime mrelocatable-lib @@ -62,19 +62,19 @@ Target Produce code relocatable at runtime mlittle-endian -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code mlittle -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code mbig-endian -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code mbig -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code ;; FIXME: This does nothing. What should be done? @@ -96,7 +96,7 @@ Target RejectNegative no description yet meabi -Target Report Mask(EABI) +Target Report Mask(EABI) Var(rs6000_isa_flags) Use EABI mbit-word @@ -138,11 +138,11 @@ Target RejectNegative no description yet m64 -Target Report RejectNegative Negative(m32) Mask(64BIT) +Target Report RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target Report RejectNegative Negative(m64) InverseMask(64BIT) +Target Report RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code mnewlib Index: gcc/config/rs6000/rs6000-cpus.def =================================================================== --- gcc/config/rs6000/rs6000-cpus.def (revision 192544) +++ gcc/config/rs6000/rs6000-cpus.def (revision 192545) @@ -18,6 +18,57 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ +/* ISA masks. */ +#ifndef ISA_2_1_MASKS +#define ISA_2_1_MASKS OPTION_MASK_MFCRF +#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB) +#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND) + + /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add + ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, + fre, fsqrt, etc. were no longer documented as optional. Group masks by + server and embedded. */ +#define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT) + +#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP) + + /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but + altivec is a win so enable it. */ +#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD) +#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_ALTIVEC \ + | OPTION_MASK_VSX) + +#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) + +/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ +#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_DFP \ + | OPTION_MASK_DLMZB \ + | OPTION_MASK_FPRND \ + | OPTION_MASK_ISEL \ + | OPTION_MASK_MFCRF \ + | OPTION_MASK_MFPGPR \ + | OPTION_MASK_MULHW \ + | OPTION_MASK_NO_UPDATE \ + | OPTION_MASK_POPCNTB \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_POWERPC64 \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_SOFT_FLOAT \ + | OPTION_MASK_STRICT_ALIGN \ + | OPTION_MASK_VSX) + +#endif + /* This table occasionally claims that a processor does not support a particular feature even though it does, but the feature is slower than the alternative. Thus, it shouldn't be relied on as a complete description of Index: gcc/config/rs6000/freebsd.h =================================================================== --- gcc/config/rs6000/freebsd.h (revision 192544) +++ gcc/config/rs6000/freebsd.h (revision 192545) @@ -72,7 +72,7 @@ -mrelocatable or -mrelocatable-lib is given. */ #undef RELOCATABLE_NEEDS_FIXUP #define RELOCATABLE_NEEDS_FIXUP \ - (target_flags & target_flags_explicit & MASK_RELOCATABLE) + (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) Index: gcc/config/rs6000/option-defaults.h =================================================================== --- gcc/config/rs6000/option-defaults.h (revision 192544) +++ gcc/config/rs6000/option-defaults.h (revision 192545) @@ -35,11 +35,12 @@ #define OPT_32 "m32" #endif -#ifndef MASK_64BIT +#ifndef OPTION_MASK_64BIT +#define OPTION_MASK_64BIT 0 #define MASK_64BIT 0 #endif -#if TARGET_DEFAULT & MASK_64BIT +#if TARGET_DEFAULT & OPTION_MASK_64BIT #define OPT_ARCH64 "!"OPT_32 #define OPT_ARCH32 OPT_32 #else Index: gcc/config/rs6000/aix51.h =================================================================== --- gcc/config/rs6000/aix51.h (revision 192544) +++ gcc/config/rs6000/aix51.h (revision 192545) @@ -26,7 +26,7 @@ do { \ if (TARGET_64BIT && ! TARGET_POWERPC64) \ { \ - target_flags |= MASK_POWERPC64; \ + rs6000_isa_flags |= OPTION_MASK_POWERPC64; \ warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \ } \ if (TARGET_POWERPC64 && ! TARGET_64BIT) \ Index: gcc/config/rs6000/sysv4.h =================================================================== --- gcc/config/rs6000/sysv4.h (revision 192544) +++ gcc/config/rs6000/sysv4.h (revision 192545) @@ -40,9 +40,10 @@ #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc" -#define TARGET_TOC ((target_flags & MASK_64BIT) \ - || ((target_flags & (MASK_RELOCATABLE \ - | MASK_MINIMAL_TOC)) \ +#define TARGET_TOC ((rs6000_isa_flags & OPTION_MASK_64BIT) \ + || ((rs6000_isa_flags \ + & (OPTION_MASK_RELOCATABLE \ + | OPTION_MASK_MINIMAL_TOC)) \ && flag_pic > 1) \ || DEFAULT_ABI == ABI_AIX) @@ -77,13 +78,13 @@ do { \ else if (!strcmp (rs6000_abi_name, "sysv-noeabi")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags &= ~ MASK_EABI; \ + rs6000_isa_flags &= ~ OPTION_MASK_EABI; \ } \ else if (!strcmp (rs6000_abi_name, "sysv-eabi") \ || !strcmp (rs6000_abi_name, "eabi")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags |= MASK_EABI; \ + rs6000_isa_flags |= OPTION_MASK_EABI; \ } \ else if (!strcmp (rs6000_abi_name, "aixdesc")) \ rs6000_current_abi = ABI_AIX; \ @@ -102,8 +103,8 @@ do { \ else if (!strcmp (rs6000_abi_name, "i960-old")) \ { \ rs6000_current_abi = ABI_V4; \ - target_flags |= (MASK_LITTLE_ENDIAN | MASK_EABI); \ - target_flags &= ~MASK_STRICT_ALIGN; \ + rs6000_isa_flags |= (OPTION_MASK_LITTLE_ENDIAN | OPTION_MASK_EABI); \ + rs6000_isa_flags &= ~OPTION_MASK_STRICT_ALIGN; \ TARGET_NO_BITFIELD_WORD = 1; \ } \ else \ @@ -168,13 +169,13 @@ do { \ \ if (TARGET_RELOCATABLE && !TARGET_MINIMAL_TOC) \ { \ - target_flags |= MASK_MINIMAL_TOC; \ + rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; \ error ("-mrelocatable and -mno-minimal-toc are incompatible"); \ } \ \ if (TARGET_RELOCATABLE && rs6000_current_abi == ABI_AIX) \ { \ - target_flags &= ~MASK_RELOCATABLE; \ + rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error ("-mrelocatable and -mcall-%s are incompatible", \ rs6000_abi_name); \ } \ @@ -188,7 +189,7 @@ do { \ \ if (rs6000_current_abi == ABI_AIX && TARGET_LITTLE_ENDIAN) \ { \ - target_flags &= ~MASK_LITTLE_ENDIAN; \ + rs6000_isa_flags &= ~OPTION_MASK_LITTLE_ENDIAN; \ error ("-mcall-aixdesc must be big endian"); \ } \ \ @@ -200,7 +201,7 @@ do { \ /* Treat -fPIC the same as -mrelocatable. */ \ if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX) \ { \ - target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; \ + rs6000_isa_flags |= OPTION_MASK_RELOCATABLE | OPTION_MASK_MINIMAL_TOC; \ TARGET_NO_FP_IN_TOC = 1; \ } \ \ @@ -212,9 +213,9 @@ do { \ #ifndef RS6000_BI_ARCH # define SUBSUBTARGET_OVERRIDE_OPTIONS \ do { \ - if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) \ + if ((TARGET_DEFAULT ^ rs6000_isa_flags) & OPTION_MASK_64BIT) \ error ("-m%s not supported in this configuration", \ - (target_flags & MASK_64BIT) ? "64" : "32"); \ + (rs6000_isa_flags & OPTION_MASK_64BIT) ? "64" : "32"); \ } while (0) #endif @@ -500,8 +501,8 @@ extern int fixuplabelno; #define TARGET_OS_SYSV_CPP_BUILTINS() \ do \ { \ - if (target_flags_explicit \ - & MASK_RELOCATABLE) \ + if (rs6000_isa_flags_explicit \ + & OPTION_MASK_RELOCATABLE) \ builtin_define ("_RELOCATABLE"); \ } \ while (0) Index: gcc/common/config/rs6000/rs6000-common.c =================================================================== --- gcc/common/config/rs6000/rs6000-common.c (revision 192544) +++ gcc/common/config/rs6000/rs6000-common.c (revision 192545) @@ -82,23 +82,23 @@ rs6000_handle_option (struct gcc_options switch (code) { case OPT_mfull_toc: - opts->x_target_flags &= ~MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_MINIMAL_TOC; opts->x_TARGET_NO_FP_IN_TOC = 0; opts->x_TARGET_NO_SUM_IN_TOC = 0; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; #ifdef TARGET_USES_SYSV4_OPT /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be just the same as -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; #endif break; #ifdef TARGET_USES_SYSV4_OPT case OPT_mtoc: /* Make -mtoc behave like -mminimal-toc. */ - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; break; #endif @@ -107,9 +107,10 @@ rs6000_handle_option (struct gcc_options #else case OPT_m64: #endif - opts->x_target_flags |= MASK_POWERPC64; - opts->x_target_flags |= ~opts_set->x_target_flags & MASK_PPC_GFXOPT; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; + opts->x_rs6000_isa_flags |= (~opts_set->x_rs6000_isa_flags + & OPTION_MASK_PPC_GFXOPT); + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; #ifdef TARGET_USES_AIX64_OPT @@ -117,8 +118,8 @@ rs6000_handle_option (struct gcc_options #else case OPT_m32: #endif - opts->x_target_flags &= ~MASK_POWERPC64; - opts_set->x_target_flags |= MASK_POWERPC64; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_POWERPC64; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64; break; case OPT_mminimal_toc: @@ -181,8 +182,8 @@ rs6000_handle_option (struct gcc_options case OPT_mrelocatable: if (value == 1) { - opts->x_target_flags |= MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; opts->x_TARGET_NO_FP_IN_TOC = 1; } break; @@ -190,14 +191,16 @@ rs6000_handle_option (struct gcc_options case OPT_mrelocatable_lib: if (value == 1) { - opts->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; - opts_set->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; + opts->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); + opts_set->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE + | OPTION_MASK_MINIMAL_TOC); opts->x_TARGET_NO_FP_IN_TOC = 1; } else { - opts->x_target_flags &= ~MASK_RELOCATABLE; - opts_set->x_target_flags |= MASK_RELOCATABLE; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_RELOCATABLE; } break; #endif @@ -227,15 +230,15 @@ rs6000_handle_option (struct gcc_options "-msingle-float option equivalent to -mhard-float"); /* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_double_float = 0; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_mdouble_float: /* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */ opts->x_rs6000_single_float = 1; - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; break; case OPT_msimple_fpu: @@ -259,8 +262,8 @@ rs6000_handle_option (struct gcc_options { /* If -mfpu is not none, then turn off SOFT_FLOAT, turn on HARD_FLOAT. */ - opts->x_target_flags &= ~MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; opts->x_rs6000_xilinx_fpu = 1; if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL) opts->x_rs6000_single_float = 1; @@ -272,8 +275,8 @@ rs6000_handle_option (struct gcc_options else { /* -mfpu=none is equivalent to -msoft-float. */ - opts->x_target_flags |= MASK_SOFT_FLOAT; - opts_set->x_target_flags |= MASK_SOFT_FLOAT; + opts->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; + opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0; } break; @@ -297,8 +300,4 @@ rs6000_handle_option (struct gcc_options #undef TARGET_OPTION_OPTIMIZATION_TABLE #define TARGET_OPTION_OPTIMIZATION_TABLE rs6000_option_optimization_table -#undef TARGET_DEFAULT_TARGET_FLAGS -#define TARGET_DEFAULT_TARGET_FLAGS \ - (TARGET_DEFAULT) - struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f 2012-10-17 20:48 ` Michael Meissner @ 2012-10-18 15:46 ` Eric Botcazou 0 siblings, 0 replies; 13+ messages in thread From: Eric Botcazou @ 2012-10-18 15:46 UTC (permalink / raw) To: Michael Meissner Cc: gcc-patches, David Edelsohn, bergner, segher, iain, andreast-list > 2012-10-17 Michael Meissner <meissner@linux.vnet.ibm.com> > > * config/rs6000/rs6000.opt (rs6000_isa_flags): New flag word to > replace target_flags that gives us 63 possible switches. > (x_rs6000_isa_flags): Save area for rs6000_isa_flags. > (x_rs6000_isa_flags_explicit): Save area for > rs6000_isa_flags_explicit. > (rs6000_target_flags_explicit): Delete in favor of > x_rs6000_isa_flags_explicit. > (-mpowerpc64): Change all switches that used to be in target_flags > to now be in rs6000_isa_flags. In using rs6000_isa_flags, the > options machinary will generate names of the form OPITON_<xxx> > instead of TARGET_<xxx> and OPTION_MASK_<xxx> instead of > MASK_<xxx>. > (-mpowerpc-gpopt): Likewise. > (-mpowerpc-gfxopt): Likewise. > (-mmfcrf): Likewise. > (-mpopcntb): Likewise. > (-mfprnd): Likewise. > (-mcmpb): Likewise. > (-mmfpgpr): Likewise. > (-maltivec): Likewise. > (-mhard-dfp): Likewise. > (-mmulhw): Likewise. > (-mdlmzb): Likewise. > (-mmultiple): Likewise. > (-mstring): Likewise. > (-msoft-float): Likewise. > (-mhard-float): Likewise. > (-mpopcntd): Likewise. > (-mvsx): Likewise. > (-mno-update): Likewise. > (-mupdate): Likewise. > (-mrecip-precision): Likewise. > (-mminimal-toc): Likewise. > (-misel): Likewise. > * config/rs6000/aix64.opt (-maix64): Likewise. > (-maix32): Likewise. > * config/rs6000/sysv4.opt (-mstrict-align): Likewise. > (-mrelocatable): Likewise. > (-mlittle-endian): Likewise. > (-mlittle): Likewise. > (-mbig-endian): LIkewise. > (-mbig): Likewise. > (-meabi): Likewise. > (-m64): Likewise. > (-m32): Likewise. > * config/rs6000/darwin.opt (-m64): Likewise. > (-m32): Likewise. > > * config/rs6000/rs6000-cpus.def (ISA_2_1_MASKS): Move the various > masks used in rs6000.c here, since they are more logically in this > file. Convert from being enums to just #defines, since the types > of these masks is now HOST_WIDE_INT instead of int. For > POWERPC_MASKS, add MASK_SOFT_FLOAT, since the only use case or'ed > in the mask. Change the use in rs6000.c not to do the OR of > MASK_SOFT_FLOAT. > (ISA_2_1_MASKS): Likewise. > (ISA_2_2_MASKS): Likewise. > (ISA_2_4_MASKS): Likewise. > (ISA_2_5_MASKS_EMBEDDED): Likewise. > (ISA_2_5_MASKS_SERVER): Likewise. > (POWERPC_7400_MASK): Likewise. > (POWERPC_MASKS): Likewise. > * config/rs6000/rs6000.c (ISA_2_1_MASKS): Likewise. > (ISA_2_1_MASKS): Likewise. > (ISA_2_2_MASKS): Likewise. > (ISA_2_4_MASKS): Likewise. > (ISA_2_5_MASKS_EMBEDDED): Likewise. > (ISA_2_5_MASKS_SERVER): Likewise. > (POWERPC_7400_MASK): Likewise. > (POWERPC_MASKS): Likewise. > (rs6000_option_override_internal): Likewise. > > * config/rs6000/rs6000.c (darwin_rs6000_override_options): Change > all uses of target_flags to rs6000_isa_flags. Change all uses of > target_flags_explicit to rs6000_isa_flags_explicit. Change the > use of MASK_<xxx> to OPTION_MASK_<xxx> that options.h defines when > we use a secondary flags word. Save/restore/print the new flags > word when switching contexts with different target attributes. > (rs6000_option_override_internal): Likewise. > (rs6000_darwin_file_start): Likewise. > (rs6000_opt_masks): Likewise. > (rs6000_inner_target_options): Likewise. > (rs6000_pragma_target_parse): Likewise. > (rs6000_set_current_function): Likewise. > (rs6000_function_specific_save): Likewise. > (rs6000_function_specific_restore): Likewise. > (rs6000_function_specific_print): Likewise. > (rs6000_can_inline_p): Likewise. > * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): > Likewise. > (rs6000_cpu_cpp_builtins): Likewise. > * common/config/rs6000/rs6000-driver.c (rs6000_handle_option): > Likewise. > > * config/rs6000/rs6000.h (MASK_ALTIVEC): In moving to using > Var(...) for all of the isa switches, the options machinery now > uses OPTION_MASK_<xxx> instead of MASK_<xxx> for the mask name. > Use #define to map the old name into the new name. For switches > that are defined in aix64.opt, sysv4.opt, and darwin.opt, only do > the definition if those switches were defined. > (MASK_ALTIVEC): Likewise. > (MASK_CMPB): Likewise. > (MASK_DFP): Likewise. > (MASK_DLMZB): Likewise. > (MASK_EABI): Likewise. > (MASK_FPRND): Likewise. > (MASK_HARD_FLOAT): Likewise. > (MASK_ISEL): Likewise. > (MASK_MFCRF): Likewise. > (MASK_MFPGPR): Likewise. > (MASK_MULHW): Likewise. > (MASK_MULTIPLE): Likewise. > (MASK_NO_UPDATE): Likewise. > (MASK_POPCNTB): Likewise. > (MASK_POPCNTD): Likewise. > (MASK_PPC_GFXOPT): Likewise. > (MASK_PPC_GPOPT): Likewise. > (MASK_RECIP_PRECISION): Likewise. > (MASK_SOFT_FLOAT): Likewise. > (MASK_STRICT_ALIGN): Likewise. > (MASK_STRING): Likewise. > (MASK_UPDATE): Likewise. > (MASK_VSX): Likewise. > (MASK_POWERPC64): Likewise. > (MASK_64BIT): Likewise. > (MASK_RELOCATABLE): Likewise. > (MASK_LITTLE_ENDIAN): Likewise. > (MASK_MINIMAL_TOC): Likewise. > (MASK_REGNAMES): Likewise. > (MASK_PROTOTYPE): Likewise. > (rs6000_isa_flags_explicit): Define in terms of the > global_options_set structure. > > * gcc/config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): > Change use of target_flags to rs6000_isa_flags, > target_flags_explicit to rs6000_isa_flags_explicit, and MASK_<xxx> > to OPTION_MASK_<xxx>. > * gcc/config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): > Likewise. > * gcc/config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): > Likewise. > * gcc/config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): > Likewise. > * gcc/config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): > Likewise. > * gcc/config/rs6000/freebsd64.h (RELOCATABLE_NEEDS_FIXUP): > Likewise. > (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. > * gcc/config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP): > Likewise. > * gcc/config/rs6000/linux64.h (RELOCATABLE_NEEDS_FIXUP): > Likewise. > (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. > (OPTION_LITTLE_ENDIAN): Likewise. > (OPTION_RELOCATABLE): Likewise. > (OPTION_EABI): Likewise. > (OPTION_PROTOTYPE): Likewise. > * gcc/config/rs6000/linux.h (RELOCATABLE_NEEDS_FIXUP): Likewise. > * gcc/config/rs6000/option-defaults.h (OPTION_MASK_64BIT): > Likewise. > (OPT_ARCH32): Likewise. > (OPT_ARCH64): Likewise. > * gcc/config/rs6000/sysv4.h (TARGET_TOC): Likewise. > (SUBTARGET_OVERRIDE_OPTIONS): Likewise. > (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. > (TARGET_OS_SYSV_CPP_BUILTINS): Likewise. > > * config/rs6000/t-rs6000 (rs6000.o): Add rs6000-cpus.def as a > dependency. This apparently breaks bootstrap on PowerPC/Linux: libtool: compile: /nile.build/botcazou/gcc-head/powerpc-linux-gnu/./gcc/xgcc -B/nile.build/botcazou/gcc-head/powerpc-linux-gnu/./gcc/ - B/nile.build/botcazou/gcc-head/install_ppc/powerpc-linux-gnu/bin/ - B/nile.build/botcazou/gcc-head/install_ppc/powerpc-linux-gnu/lib/ -isystem /nile.build/botcazou/gcc-head/install_ppc/powerpc-linux-gnu/include -isystem /nile.build/botcazou/gcc-head/install_ppc/powerpc-linux-gnu/sys-include /nile.build/botcazou/gcc-head/src/libobjc/encoding.c -c -I. - I/nile.build/botcazou/gcc-head/src/libobjc -g -O2 -W -Wall -Wwrite-strings - Wstrict-prototypes -DIN_GCC -DIN_TARGET_LIBS -fno-strict-aliasing -fexceptions -I/nile.build/botcazou/gcc-head/src/libobjc/../gcc -I/nile.build/botcazou/gcc- head/src/libobjc/../gcc/config -I../.././gcc -I/nile.build/botcazou/gcc- head/src/libobjc/../libgcc -I../libgcc -I/nile.build/botcazou/gcc- head/src/libobjc/../include -fPIC -DPIC -o .libs/encoding.o In file included from ../.././gcc/tm.h:19:0, from /nile.build/botcazou/gcc-head/src/libobjc/encoding.c:37: /nile.build/botcazou/gcc-head/src/libobjc/encoding.c: In function 'objc_layout_structure_next_member': ../.././gcc/options.h:4286:26: error: 'rs6000_isa_flags' undeclared (first use in this function) #define TARGET_ALTIVEC ((rs6000_isa_flags & OPTION_MASK_ALTIVEC) != 0) ^ /nile.build/botcazou/gcc-head/src/libobjc/../gcc/config/rs6000/sysv4.h:301:4: note: in expansion of macro 'TARGET_ALTIVEC' ((TARGET_ALTIVEC && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \ ^ /nile.build/botcazou/gcc-head/src/libobjc/encoding.c:1138:19: note: in expansion of macro 'ADJUST_FIELD_ALIGN' desired_align = ADJUST_FIELD_ALIGN (type, desired_align); ^ ../.././gcc/options.h:4286:26: note: each undeclared identifier is reported only once for each function it appears in #define TARGET_ALTIVEC ((rs6000_isa_flags & OPTION_MASK_ALTIVEC) != 0) ^ /nile.build/botcazou/gcc-head/src/libobjc/../gcc/config/rs6000/sysv4.h:301:4: note: in expansion of macro 'TARGET_ALTIVEC' ((TARGET_ALTIVEC && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \ ^ /nile.build/botcazou/gcc-head/src/libobjc/encoding.c:1138:19: note: in expansion of macro 'ADJUST_FIELD_ALIGN' desired_align = ADJUST_FIELD_ALIGN (type, desired_align); ^ ../.././gcc/options.h:4255:30: error: 'HOST_WIDE_INT_1' undeclared (first use in this function) #define OPTION_MASK_ALTIVEC (HOST_WIDE_INT_1 << 1) ^ ../.././gcc/options.h:4286:45: note: in expansion of macro 'OPTION_MASK_ALTIVEC' #define TARGET_ALTIVEC ((rs6000_isa_flags & OPTION_MASK_ALTIVEC) != 0) ^ /nile.build/botcazou/gcc-head/src/libobjc/../gcc/config/rs6000/sysv4.h:301:4: note: in expansion of macro 'TARGET_ALTIVEC' ((TARGET_ALTIVEC && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \ ^ /nile.build/botcazou/gcc-head/src/libobjc/encoding.c:1138:19: note: in expansion of macro 'ADJUST_FIELD_ALIGN' desired_align = ADJUST_FIELD_ALIGN (type, desired_align); ^ make[1]: *** [encoding.lo] Error 1 make[1]: Leaving directory `/nfs/nile/nile.build/botcazou/gcc-head/powerpc- linux-gnu/powerpc-linux-gnu/libobjc' make: *** [all-target-libobjc] Error 2 -- Eric Botcazou ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2012-10-20 4:10 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2012-10-18 19:28 [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f Dominique Dhumieres 2012-10-18 20:32 ` Mike Stump 2012-10-18 22:31 ` Michael Meissner 2012-10-19 0:40 ` Michael Meissner 2012-10-19 3:40 ` David Edelsohn 2012-10-19 9:45 ` Eric Botcazou 2012-10-19 14:30 ` Dominique Dhumieres 2012-10-19 19:52 ` Michael Meissner 2012-10-20 6:42 ` Mike Stump -- strict thread matches above, loose matches on Subject: below -- 2012-09-12 22:44 [PATCH] Rs6000 infrastructure cleanup (switches) Michael Meissner 2012-09-17 19:52 ` [PATCH] Rs6000 infrastructure cleanup (switches), revised patch Michael Meissner 2012-09-19 0:04 ` David Edelsohn 2012-09-20 20:12 ` Michael Meissner 2012-09-27 22:57 ` [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2b Michael Meissner 2012-10-04 1:42 ` David Edelsohn 2012-10-05 19:49 ` Michael Meissner 2012-10-16 16:13 ` [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f Michael Meissner 2012-10-17 19:42 ` David Edelsohn 2012-10-17 20:48 ` Michael Meissner 2012-10-18 15:46 ` Eric Botcazou
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