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From: Xi Ruoyao To: chenglulu , gcc-patches@gcc.gnu.org Cc: i@xen0n.name, xuchenghua@loongson.cn Date: Wed, 15 Nov 2023 04:42:03 +0800 In-Reply-To: <086495273b4f2a721c3b6e15859781cdc8134966.camel@xry111.site> References: <20231114094500.8160-1-chenglulu@loongson.cn> <4030bb00a356a8e8bb801f92951d444117d4dba0.camel@xry111.site> <4969dd47-01d9-0b79-e7ac-6683ed166eac@loongson.cn> <086495273b4f2a721c3b6e15859781cdc8134966.camel@xry111.site> Autocrypt: addr=xry111@xry111.site; prefer-encrypt=mutual; keydata=mDMEYnkdPhYJKwYBBAHaRw8BAQdAsY+HvJs3EVKpwIu2gN89cQT/pnrbQtlvd6Yfq7egugi0HlhpIFJ1b3lhbyA8eHJ5MTExQHhyeTExMS5zaXRlPoiTBBMWCgA7FiEEkdD1djAfkk197dzorKrSDhnnEOMFAmJ5HT4CGwMFCwkIBwICIgIGFQoJCAsCBBYCAwECHgcCF4AACgkQrKrSDhnnEOPHFgD8D9vUToTd1MF5bng9uPJq5y3DfpcxDp+LD3joA3U2TmwA/jZtN9xLH7CGDHeClKZK/ZYELotWfJsqRcthOIGjsdAPuDgEYnkdPhIKKwYBBAGXVQEFAQEHQG+HnNiPZseiBkzYBHwq/nN638o0NPwgYwH70wlKMZhRAwEIB4h4BBgWCgAgFiEEkdD1djAfkk197dzorKrSDhnnEOMFAmJ5HT4CGwwACgkQrKrSDhnnEOPjXgD/euD64cxwqDIqckUaisT3VCst11RcnO5iRHm6meNIwj0BALLmWplyi7beKrOlqKfuZtCLbiAPywGfCNg8LOTt4iMD Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.1 MIME-Version: 1.0 X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, 2023-11-15 at 04:26 +0800, Xi Ruoyao wrote: > On Tue, 2023-11-14 at 20:46 +0800, chenglulu wrote: > >=20 > > =E5=9C=A8 2023/11/14 =E4=B8=8B=E5=8D=885:55, Xi Ruoyao =E5=86=99=E9=81= =93: > > > On Tue, 2023-11-14 at 17:45 +0800, Lulu Cheng wrote: > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* When function calls are made thr= ough call36, t0 register > > > > will be > > > > + implicitly modified, so '-fno-ipa-ra' needs to be set > > > > here.=C2=A0 */ > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case CMODEL_MEDIUM: > > > > + if (HAVE_AS_SUPPORT_CALL36) > > > > + =C2=A0 opts->x_flag_ipa_ra =3D 0; > > > > + break; > > > Maybe we can add a (clobber (reg:P 12)) to the related insns > > > instead? > > >=20 > > Sorry, this was modified in accordance with the call36 macro > > instruction=20 > > during the test. > > I will use clobber, and add test cases. >=20 > There seems a better solution as suggested by the GCC internal doc.=20 > Section 18.9.16 mentions -fipa-ra: >=20 > =C2=A0-- Target Hook: bool TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBER= S > =C2=A0=C2=A0=C2=A0=C2=A0 Set to true if each call that binds to a local d= efinition > =C2=A0=C2=A0=C2=A0=C2=A0 explicitly clobbers or sets all non-fixed regist= ers modified by > =C2=A0=C2=A0=C2=A0=C2=A0 performing the call.=C2=A0 That is, by the call = pattern itself, or by > =C2=A0=C2=A0=C2=A0=C2=A0 code that might be inserted by the linker (e.g. = stubs, veneers, > =C2=A0=C2=A0=C2=A0=C2=A0 branch islands), but not including those modifia= ble by the callee. > =C2=A0=C2=A0=C2=A0=C2=A0 The affected registers may be mentioned explicit= ly in the call > =C2=A0=C2=A0=C2=A0=C2=A0 pattern, or included as clobbers in CALL_INSN_FU= NCTION_USAGE. The > =C2=A0=C2=A0=C2=A0=C2=A0 default version of this hook is set to false.=C2= =A0 The purpose of this > =C2=A0=C2=A0=C2=A0=C2=A0 hook is to enable the fipa-ra optimization. >=20 > So we can add t0 into CALL_INSN_FUNCTION_USAGE of the call insn, like: >=20 > diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loo= ngarch.md > index ea36542b1c3..96e7e98e6b3 100644 > --- a/gcc/config/loongarch/loongarch.md > +++ b/gcc/config/loongarch/loongarch.md > @@ -3274,7 +3274,14 @@ (define_expand "sibcall" > =C2=A0 =C2=A0=C2=A0=C2=A0 XEXP (target, 1), > =C2=A0 =C2=A0=C2=A0=C2=A0 operands[1])); > =C2=A0=C2=A0 else > -=C2=A0=C2=A0=C2=A0 emit_call_insn (gen_sibcall_internal (target, operand= s[1])); > +=C2=A0=C2=A0=C2=A0 { > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rtx call =3D gen_sibcall_internal (target= , operands[1]); > + > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (TARGET_CMODEL_MEDIUM && !REG_P (targe= t)) > + clobber_reg (&CALL_INSN_FUNCTION_USAGE (call), > + =C2=A0=C2=A0=C2=A0=C2=A0 gen_rtx_REG (Pmode, T0_REGNUM)); > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 emit_call_insn (call); > +=C2=A0=C2=A0=C2=A0 } > =C2=A0=C2=A0 DONE; > =C2=A0}) >=20 > Likewise for sibcall_value. Nope. This does not work for __attribute__((noinline)) void q() { asm ("":::"memory"); } __attribute__((noinline)) static void t() { q(); } int main () { int x0 =3D 114514; asm("":"+r"(x0)); t(); if (x0 !=3D 114514) __builtin_trap (); } Not sure why... >=20 > By the way we'd better have a command line switch to override the build- > time check for assembler call36 support, because it makes writing test > cases and inter-operating with different versions of assembler easier. >=20 --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University