From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 85362385741A for ; Wed, 5 May 2021 15:18:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 85362385741A Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 145F4IZF184406 for ; Wed, 5 May 2021 11:18:40 -0400 Received: from ppma03fra.de.ibm.com (6b.4a.5195.ip4.static.sl-reverse.com [149.81.74.107]) by mx0b-001b2d01.pphosted.com with ESMTP id 38bumvn1b1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 05 May 2021 11:18:39 -0400 Received: from pps.filterd (ppma03fra.de.ibm.com [127.0.0.1]) by ppma03fra.de.ibm.com (8.16.0.43/8.16.0.43) with SMTP id 145Ex0Mi030216 for ; Wed, 5 May 2021 15:18:38 GMT Received: from b06cxnps3074.portsmouth.uk.ibm.com (d06relay09.portsmouth.uk.ibm.com [9.149.109.194]) by ppma03fra.de.ibm.com with ESMTP id 38beebg6wr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 05 May 2021 15:18:37 +0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 145FIYt426542356 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 5 May 2021 15:18:35 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D0E2F4C04A; Wed, 5 May 2021 15:18:34 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A87D04C040; Wed, 5 May 2021 15:18:34 +0000 (GMT) Received: from li-926bd7cc-2dd1-11b2-a85c-f6adc0f5efec.ibm.com (unknown [9.171.18.239]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTPS; Wed, 5 May 2021 15:18:34 +0000 (GMT) To: Andreas Krebbel , GCC Patches From: Robin Dapp Subject: [PATCH] s390: Add more vcond_mask patterns. Message-ID: <49d520d8-c771-66bd-e657-d02d2990cb0a@linux.ibm.com> Date: Wed, 5 May 2021 17:18:34 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.9.1 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------407F3FD3C967D1EE685A6CA1" Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: uqSXMLChpaBuv9tYjDQA80wtkMU1-TE8 X-Proofpoint-GUID: uqSXMLChpaBuv9tYjDQA80wtkMU1-TE8 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-05_09:2021-05-05, 2021-05-05 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104060000 definitions=main-2105050110 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 May 2021 15:18:42 -0000 This is a multi-part message in MIME format. --------------407F3FD3C967D1EE685A6CA1 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Hi, this patch adds vcond_mask patterns with mixed mode for the condition/mask and source, target so e.g. boolean conditions become possible: vtarget = bool_cond ? vsource1 : vsource2. Is it OK for trunk? Regards Robin gcc/ChangeLog: * config/s390/vector.md (vcond_mask_): Add vcond_mask with mixed mode. (vcond_mask_): Dito. gcc/testsuite/ChangeLog: * gcc.target/s390/vector/vcond-mixed-double.c: New test. * gcc.target/s390/vector/vcond-mixed-float.c: New test. --------------407F3FD3C967D1EE685A6CA1 Content-Type: text/x-patch; charset=UTF-8; name="0003-s390-Add-more-vcond_mask-patterns.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0003-s390-Add-more-vcond_mask-patterns.patch" >From 4ce2d9a3f43c44d35142a726921258540adfca51 Mon Sep 17 00:00:00 2001 From: Robin Dapp Date: Thu, 18 Mar 2021 11:31:02 +0100 Subject: [PATCH 3/7] s390: Add more vcond_mask patterns. Add vcond_mask patterns that allow another mode for the condition/mask than the source and target so e.g. boolean conditions become possible: vtarget = bool_cond ? vsource1 : vsource2. Also, add test cases for vcond_mask with mixed modes. --- gcc/config/s390/vector.md | 21 ++++++++++ .../s390/vector/vcond-mixed-double.c | 41 +++++++++++++++++++ .../s390/vector/vcond-mixed-float.c | 41 +++++++++++++++++++ 3 files changed, 103 insertions(+) create mode 100644 gcc/testsuite/gcc.target/s390/vector/vcond-mixed-double.c create mode 100644 gcc/testsuite/gcc.target/s390/vector/vcond-mixed-float.c diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index c80d582a300..7c730432d80 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -36,6 +36,7 @@ (define_mode_iterator V_HW2 [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE") (V1TF "TARGET_VXE") (TF "TARGET_VXE")]) + (define_mode_iterator V_HW_64 [V2DI V2DF]) (define_mode_iterator VT_HW_HSDT [V8HI V4SI V4SF V2DI V2DF V1TI V1TF TI TF]) (define_mode_iterator V_HW_HSD [V8HI V4SI (V4SF "TARGET_VXE") V2DI V2DF]) @@ -725,6 +726,26 @@ "TARGET_VX" "operands[4] = CONST0_RTX (mode);") +(define_expand "vcond_mask_" + [(set (match_operand:VX_VEC_CONV_BFP 0 "register_operand" "") + (if_then_else:VX_VEC_CONV_BFP + (eq (match_operand:VX_VEC_CONV_INT 3 "register_operand" "") + (match_dup 4)) + (match_operand:VX_VEC_CONV_BFP 2 "register_operand" "") + (match_operand:VX_VEC_CONV_BFP 1 "register_operand" "")))] + "TARGET_VX" + "operands[4] = CONST0_RTX (mode);") + +(define_expand "vcond_mask_" + [(set (match_operand:VX_VEC_CONV_INT 0 "register_operand" "") + (if_then_else:VX_VEC_CONV_INT + (eq (match_operand:VX_VEC_CONV_BFP 3 "register_operand" "") + (match_dup 4)) + (match_operand:VX_VEC_CONV_INT 2 "register_operand" "") + (match_operand:VX_VEC_CONV_INT 1 "register_operand" "")))] + "TARGET_VX" + "operands[4] = CONST0_RTX (mode);") + ; We only have HW support for byte vectors. The middle-end is ; supposed to lower the mode if required. diff --git a/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-double.c b/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-double.c new file mode 100644 index 00000000000..8795d08a732 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-double.c @@ -0,0 +1,41 @@ +/* Check for vectorization of mixed conditionals. */ +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -march=z14 -mzarch" } */ + +double xd[1024]; +double zd[1024]; +double wd[1024]; + +long xl[1024]; +long zl[1024]; +long wl[1024]; + +void foold () +{ + int i; + for (i = 0; i < 1024; ++i) + zd[i] = xl[i] ? zd[i] : wd[i]; +} + +void foodl () +{ + int i; + for (i = 0; i < 1024; ++i) + zl[i] = xd[i] ? zl[i] : wl[i]; +} + +void foold2 () +{ + int i; + for (i = 0; i < 1024; ++i) + zd[i] = (xd[i] > 0) ? zd[i] : wd[i]; +} + +void foold3 () +{ + int i; + for (i = 0; i < 1024; ++i) + zd[i] = (xd[i] > 0. & wd[i] < 0.) ? zd[i] : wd[i]; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-float.c b/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-float.c new file mode 100644 index 00000000000..1153cace420 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vcond-mixed-float.c @@ -0,0 +1,41 @@ +/* Check for vectorization of mixed conditionals. */ +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O3 -march=z15 -mzarch" } */ + +float xf[1024]; +float zf[1024]; +float wf[1024]; + +int xi[1024]; +int zi[1024]; +int wi[1024]; + +void fooif () +{ + int i; + for (i = 0; i < 1024; ++i) + zf[i] = xi[i] ? zf[i] : wf[i]; +} + +void foofi () +{ + int i; + for (i = 0; i < 1024; ++i) + zi[i] = xf[i] ? zi[i] : wi[i]; +} + +void fooif2 () +{ + int i; + for (i = 0; i < 1024; ++i) + zf[i] = (xf[i] > 0) ? zf[i] : wf[i]; +} + +void fooif3 () +{ + int i; + for (i = 0; i < 1024; ++i) + zf[i] = (xf[i] > 0.f & wf[i] < 0.f) ? zf[i] : wf[i]; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ -- 2.23.0 --------------407F3FD3C967D1EE685A6CA1--