* [PATCH, i386]: Macroize cmove patterns
@ 2009-10-11 21:46 Uros Bizjak
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From: Uros Bizjak @ 2009-10-11 21:46 UTC (permalink / raw)
To: GCC Patches; +Cc: H.J. Lu
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Hello!
This patch macroizes cmove patterns. Oh, and it fixes
gcc.target/pr33555.c failure by introducing missing sbb insn pattern [1].
2009-10-11 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (SWIM): New mode iterator.
(mov<mode>cc): Macroize expander from mov{qi,hi,si,di}cc patterns
using SWIM mode iterator.
(x86_mov<mode>cc_0_m1): Macroize insn from x86_mov{si,di}cc_0_m1
patterns using SWI48 mode iterator.
(*x86_mov<mode>cc_0_m1_se): Macroize insn from
*x86_mov{si,di}cc_0_m1_se patterns using SWI48 mode iterator.
(*x86_mov<mode>cc_0_m1_neg): New insn pattern.
(*mov<mode>cc_noc): Macroize insn from *mov{hi,si,di}cc_noc
patterns using SWI248 mode iterator.
* config/i386/i386.c (ix86_expand_int_movcc): Update the call to
gen_x86_movdicc_0_m1_rex64 for renamed function
Patch was tested on x86_64-pc-linux-gnu {,-m32}. Patch was committed to
mainline SVN.
[1] http://gcc.gnu.org/ml/gcc-patches/2009-10/msg00716.html
Uros.
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Index: i386.md
===================================================================
--- i386.md (revision 152647)
+++ i386.md (working copy)
@@ -731,6 +731,11 @@
(HI "TARGET_HIMODE_MATH")
SI DI (TI "TARGET_64BIT")])
+;; Math-dependant single word integer modes.
+(define_mode_iterator SWIM [(QI "TARGET_QIMODE_MATH")
+ (HI "TARGET_HIMODE_MATH")
+ SI (DI "TARGET_64BIT")])
+
;; Math-dependant single word integer modes without QImode.
(define_mode_iterator SWIM248 [(HI "TARGET_HIMODE_MATH")
SI (DI "TARGET_64BIT")])
@@ -19468,22 +19473,26 @@
\f
;; Conditional move instructions.
-(define_expand "movdicc"
- [(set (match_operand:DI 0 "register_operand" "")
- (if_then_else:DI (match_operand 1 "comparison_operator" "")
- (match_operand:DI 2 "general_operand" "")
- (match_operand:DI 3 "general_operand" "")))]
- "TARGET_64BIT"
+(define_expand "mov<mode>cc"
+ [(set (match_operand:SWIM 0 "register_operand" "")
+ (if_then_else:SWIM (match_operand 1 "comparison_operator" "")
+ (match_operand:SWIM 2 "general_operand" "")
+ (match_operand:SWIM 3 "general_operand" "")))]
+ ""
"if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
-(define_insn "x86_movdicc_0_m1_rex64"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
+;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
+;; the register first winds up with `sbbl $0,reg', which is also weird.
+;; So just document what we're doing explicitly.
+
+(define_insn "x86_mov<mode>cc_0_m1"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (if_then_else:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")
(const_int -1)
(const_int 0)))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "sbb{q}\t%0, %0"
+ ""
+ "sbb{<imodesuffix>}\t%0, %0"
; Since we don't have the proper number of operands for an alu insn,
; fill in all the blanks.
[(set_attr "type" "alu")
@@ -19491,134 +19500,56 @@
(set_attr "pent_pair" "pu")
(set_attr "memory" "none")
(set_attr "imm_disp" "false")
- (set_attr "mode" "DI")
- (set_attr "length_immediate" "0")])
-
-(define_insn "*x86_movdicc_0_m1_se"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extract:DI (match_operand 1 "ix86_carry_flag_operator" "")
- (const_int 1)
- (const_int 0)))
- (clobber (reg:CC FLAGS_REG))]
- ""
- "sbb{q}\t%0, %0"
- [(set_attr "type" "alu")
- (set_attr "use_carry" "1")
- (set_attr "pent_pair" "pu")
- (set_attr "memory" "none")
- (set_attr "imm_disp" "false")
- (set_attr "mode" "DI")
+ (set_attr "mode" "<MODE>")
(set_attr "length_immediate" "0")])
-(define_insn "*movdicc_c_rex64"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
- [(reg FLAGS_REG) (const_int 0)])
- (match_operand:DI 2 "nonimmediate_operand" "rm,0")
- (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
- "TARGET_64BIT && TARGET_CMOVE
- && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
- "@
- cmov%O2%C1\t{%2, %0|%0, %2}
- cmov%O2%c1\t{%3, %0|%0, %3}"
- [(set_attr "type" "icmov")
- (set_attr "mode" "DI")])
-
-(define_expand "movsicc"
- [(set (match_operand:SI 0 "register_operand" "")
- (if_then_else:SI (match_operand 1 "comparison_operator" "")
- (match_operand:SI 2 "general_operand" "")
- (match_operand:SI 3 "general_operand" "")))]
- ""
- "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
-
-;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
-;; the register first winds up with `sbbl $0,reg', which is also weird.
-;; So just document what we're doing explicitly.
-
-(define_insn "x86_movsicc_0_m1"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
- (const_int -1)
- (const_int 0)))
+(define_insn "*x86_mov<mode>cc_0_m1_se"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (sign_extract:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")
+ (const_int 1)
+ (const_int 0)))
(clobber (reg:CC FLAGS_REG))]
""
- "sbb{l}\t%0, %0"
- ; Since we don't have the proper number of operands for an alu insn,
- ; fill in all the blanks.
+ "sbb{<imodesuffix>}\t%0, %0"
[(set_attr "type" "alu")
(set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "memory" "none")
(set_attr "imm_disp" "false")
- (set_attr "mode" "SI")
+ (set_attr "mode" "<MODE>")
(set_attr "length_immediate" "0")])
-(define_insn "*x86_movsicc_0_m1_se"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extract:SI (match_operand 1 "ix86_carry_flag_operator" "")
- (const_int 1)
- (const_int 0)))
- (clobber (reg:CC FLAGS_REG))]
+(define_insn "*x86_mov<mode>cc_0_m1_neg"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (neg:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")))]
""
- "sbb{l}\t%0, %0"
+ "sbb{<imodesuffix>}\t%0, %0"
[(set_attr "type" "alu")
(set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "memory" "none")
(set_attr "imm_disp" "false")
- (set_attr "mode" "SI")
+ (set_attr "mode" "<MODE>")
(set_attr "length_immediate" "0")])
-(define_insn "*movsicc_noc"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
- [(reg FLAGS_REG) (const_int 0)])
- (match_operand:SI 2 "nonimmediate_operand" "rm,0")
- (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
- "TARGET_CMOVE
- && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
- "@
- cmov%O2%C1\t{%2, %0|%0, %2}
- cmov%O2%c1\t{%3, %0|%0, %3}"
- [(set_attr "type" "icmov")
- (set_attr "mode" "SI")])
-
-(define_expand "movhicc"
- [(set (match_operand:HI 0 "register_operand" "")
- (if_then_else:HI (match_operand 1 "comparison_operator" "")
- (match_operand:HI 2 "general_operand" "")
- (match_operand:HI 3 "general_operand" "")))]
- "TARGET_HIMODE_MATH"
- "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
-
-(define_insn "*movhicc_noc"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
- [(reg FLAGS_REG) (const_int 0)])
- (match_operand:HI 2 "nonimmediate_operand" "rm,0")
- (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
- "TARGET_CMOVE
- && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+(define_insn "*mov<mode>cc_noc"
+ [(set (match_operand:SWI248 0 "register_operand" "=r,r")
+ (if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator"
+ [(reg FLAGS_REG) (const_int 0)])
+ (match_operand:SWI248 2 "nonimmediate_operand" "rm,0")
+ (match_operand:SWI248 3 "nonimmediate_operand" "0,rm")))]
+ "TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
"@
cmov%O2%C1\t{%2, %0|%0, %2}
cmov%O2%c1\t{%3, %0|%0, %3}"
[(set_attr "type" "icmov")
- (set_attr "mode" "HI")])
-
-(define_expand "movqicc"
- [(set (match_operand:QI 0 "register_operand" "")
- (if_then_else:QI (match_operand 1 "comparison_operator" "")
- (match_operand:QI 2 "general_operand" "")
- (match_operand:QI 3 "general_operand" "")))]
- "TARGET_QIMODE_MATH"
- "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
+ (set_attr "mode" "<MODE>")])
(define_insn_and_split "*movqicc_noc"
[(set (match_operand:QI 0 "register_operand" "=r,r")
(if_then_else:QI (match_operator 1 "ix86_comparison_operator"
- [(match_operand 4 "flags_reg_operand" "")
- (const_int 0)])
+ [(match_operand 4 "flags_reg_operand" "")
+ (const_int 0)])
(match_operand:QI 2 "register_operand" "r,0")
(match_operand:QI 3 "register_operand" "0,r")))]
"TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
Index: i386.c
===================================================================
--- i386.c (revision 152647)
+++ i386.c (working copy)
@@ -15247,9 +15247,10 @@ ix86_expand_int_movcc (rtx operands[])
tmp = gen_reg_rtx (mode);
if (mode == DImode)
- emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
+ emit_insn (gen_x86_movdicc_0_m1 (tmp, compare_op));
else
- emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
+ emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp),
+ compare_op));
}
else
{
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