From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16681 invoked by alias); 20 Oct 2009 02:54:06 -0000 Received: (qmail 16673 invoked by uid 22791); 20 Oct 2009 02:54:05 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS,SPF_PASS X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 20 Oct 2009 02:54:01 +0000 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n9K2rjHQ012961; Mon, 19 Oct 2009 22:53:45 -0400 Received: from [10.11.12.171] (vpn-12-171.rdu.redhat.com [10.11.12.171]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id n9K2riGC005148; Mon, 19 Oct 2009 22:53:44 -0400 Message-ID: <4ADD2542.1040401@redhat.com> Date: Tue, 20 Oct 2009 03:39:00 -0000 From: Vladimir Makarov User-Agent: Thunderbird 2.0.0.23 (X11/20090825) MIME-Version: 1.0 To: David Edelsohn CC: Richard Guenther , Steve Ellcey , gcc-patches Subject: Re: Ping: IRA-based register pressure calculation for RTL loop invariant motion References: <4AC41EE0.8010000@redhat.com> <20091001084947.GA5640@kam.mff.cuni.cz> <4AC4BD0D.2010400@redhat.com> <20091014152122.GA30067@kam.mff.cuni.cz> <4AD5FBF7.6040301@redhat.com> <84fc9c000910161434ue66ab0cve4ac0f08850c0e10@mail.gmail.com> <4AD93B5D.40902@redhat.com> <84fc9c000910170409r876afe9nf86986ffb1e698d3@mail.gmail.com> <4ADC9132.2030000@redhat.com> <303e1d290910191853v600cdd05v4078c97774226a21@mail.gmail.com> In-Reply-To: <303e1d290910191853v600cdd05v4078c97774226a21@mail.gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2009-10/txt/msg01255.txt.bz2 David Edelsohn wrote: > On Mon, Oct 19, 2009 at 12:17 PM, Vladimir Makarov wrote: > > >>> I think we could switch it on by default at -O3 for a selected group of >>> targets. Itanium overall also improves with the new heuristics. That >>> would >>> make it power and Itanium. >>> >> The patch is below. Ok to commit? >> >>> Did you try restricting the heuristics to certain >>> register classes, like SSE registers on x86_64? >>> >>> >>> >> No, I did not try. I am not sure it is worth to do it. >> >> >> 2009-10-19 Vladimir Makarov >> >> * doc/invoke.texi (fira-loop-pressure): Update default value. >> * opts.c (decode_options): Remove default value setting for >> flag_ira_loop_pressure. >> * config/ia64/ia64.c (ia64_override_options): Set >> flag_ira_loop_pressure up for -O3. >> * config/rs6000/rs6000.c (rs6000_override_options): Ditto. >> > > Tests inside IBM do not show this IRA feature as an overall win for > POWER. If we figure out and fix why artificially limiting > rs6000_issue_rate to 1 for the first scheduler pass still helps (and > it does), then this would make sense. Until then, please do not apply > this patch to rs6000. > > David, I think there is some misunderstanding. It is a different patch. You are probably talking about register pressure sensitive insn scheduling (by the way I am still working on its tuning). This patch is about more accurate register pressure calculation to decide profitability to do RTL loop invariant motion. SPEC2000 and polyhedron benchmarks for power6 shows that this patch is a clear win. You could test and benchmark this patch internally in IBM to confirm or deny my observation if you wish.