Hello Everyone, The patch appended below brings some fixes concerning the declaration for z10 bypasses in the machine description. Test is ok and performance of the generated code is slightly improved. Regards, Wolfgang --- Dr. Wolfgang Gellerich IBM Deutschland Entwicklung GmbH Schoenaicher Strasse 220 71032 Boeblingen, Germany Tel. +49 / 7031 / 162598 gellerich@de.ibm.com ======================= IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter Geschäftsführung: Erich Baier Sitz der Gesellschaft: Boeblingen Registergericht: Amtsgericht Stuttgart, HRB 243294 2009-10-20 Wolfgang Gellerich * config/s390/s390.md: Added agen condition to operand forwarding bypasses. Added bypass for early address generation use of int results. Updated comments. Index: gcc-SVN-un/gcc/config/s390/2097.md =================================================================== --- gcc-SVN-un.orig/gcc/config/s390/2097.md 2009-10-15 15:35:34.000000000 +0200 +++ gcc-SVN-un/gcc/config/s390/2097.md 2009-10-15 16:59:08.000000000 +0200 @@ -57,7 +57,8 @@ z10_int_fr_A3" "z10_other_super, z10_other_super_c_E1, z10_other_super_E1, \ z10_int_super, z10_int_super_E1, \ - z10_lr, z10_store_super") + z10_lr, z10_store_super" + " ! s390_agen_dep_p") ; Forwarding from z10_super to frz10_ and z10_rec. @@ -68,7 +69,8 @@ z10_store_super" "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \ z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \ - z10_other_fr_E1, z10_store_rec") + z10_other_fr_E1, z10_store_rec" + " ! s390_agen_dep_p") ; Forwarding from z10_fwd and z10_fr to z10_rec and z10_fr. @@ -84,7 +86,8 @@ z10_int_fr_A3" "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \ z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \ - z10_other_fr_E1, z10_store_rec") + z10_other_fr_E1, z10_store_rec" + " ! s390_agen_dep_p") ; @@ -205,15 +208,12 @@ (and (eq_attr "type" "lr") (eq_attr "z10prop" "z10_fr"))) "z10_e1_ANY, z10_Gate_ANY") -; "z10_e1_ANY") (define_insn_reservation "z10_lr_fr_E1" 6 (and (eq_attr "cpu" "z10") (and (eq_attr "type" "lr") (eq_attr "z10prop" "z10_fr_E1"))) "z10_e1_ANY, z10_Gate_ANY") -; "z10_e1_ANY") - (define_insn_reservation "z10_la" 6 (and (eq_attr "cpu" "z10") @@ -227,14 +227,12 @@ (and (eq_attr "type" "la") (eq_attr "z10prop" "z10_fwd"))) "z10_e1_ANY, z10_Gate_ANY") -; "z10_e1_ANY") (define_insn_reservation "z10_la_fwd_A1" 6 (and (eq_attr "cpu" "z10") (and (eq_attr "type" "la") (eq_attr "z10prop" "z10_fwd_A1"))) "z10_e1_ANY, z10_Gate_ANY") -; "z10_e1_ANY") ; larl-type instructions @@ -666,13 +664,14 @@ ; Address-related bypasses ; -; Here is the cycle diagram for Address-related bypasses: +; Here is the cycle diagram for address-related bypasses: ; ... G1 G2 G3 A0 A1 A2 A3 E1 P1 P2 P3 R0 ... -; ^ ^ ^ ^ ^ -; | | | | E1-type bypasses provide the new addr AFTER this cycle -; | | | A3-type bypasses provide the new addr AFTER this cycle -; | | A1-type bypasses provide the new addr AFTER this cycle -; | AGI resolution, actual USE of address is DURING this cycle +; ^ ^ ^ ^ ^ ^ +; | | | | | without bypass, its available AFTER this cycle +; | | | | E1-type bypasses provide the new value AFTER this cycle +; | | | A3-type bypasses provide the new value AFTER this cycle +; | | A1-type bypasses provide the new value AFTER this cycle +; | AGI resolution, actual USE of new value is DURING this cycle ; AGI detection (define_bypass 3 "z10_larl_A1, z10_la_fwd_A1, z10_other_fwd_A1, \ @@ -682,7 +681,6 @@ z10_cs, z10_stm, z10_other" "s390_agen_dep_p") - (define_bypass 5 "z10_larl_fwd_A3, z10_load_fwd_A3, z10_other_fwd_A3, \ z10_other_fr_A3, z10_int_fwd_A3, z10_int_fr_A3" "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ @@ -699,6 +697,12 @@ z10_cs, z10_stm, z10_other" "s390_agen_dep_p") +(define_bypass 9 "z10_int_super, z10_int_fwd, z10_int_fr" + "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ + z10_store, \ + z10_cs, z10_stm, z10_other" + "s390_agen_dep_p") + ;