From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by sourceware.org (Postfix) with ESMTPS id A9633385700A for ; Wed, 26 Apr 2023 21:45:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A9633385700A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-505035e3368so13335327a12.0 for ; Wed, 26 Apr 2023 14:45:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682545545; x=1685137545; h=content-transfer-encoding:mime-version:message-id:references :in-reply-to:subject:cc:to:from:date:from:to:cc:subject:date :message-id:reply-to; bh=abTIfV0NUvslYN+JJ8qM/z6ULA29G9L1w4hh44+bAjc=; b=I00/RDgLhULTVVawa3snvBWDhy5lzYQKA0Uwmrr5uyaTkdkMJGZXJYS4ffM7bM57DP KstaQARl2cmMDKGJfd5j+30WdYKUWuEt0HDlI/EzbS89EHe4qdW0sGh+YYowidTyU164 6T2qYETiQswvP0AmLolW+BDeNRiRdy23fCvuleKN2Z3Ot1DyC97JLqYhzid4/Of3ol0q na6iso/b+WtX30ihM+FcS5L3WEZu9tHWw1aOLsTw9ToNHpIgCty5xlBpp/BC0Byt951W PTRoJz+JK7QLTnBTHo0YaQLET3bRRVotuwKfhnLXOOOJyUOeROdje6/Y7DhFRvsPJ/nn 1VPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682545545; x=1685137545; h=content-transfer-encoding:mime-version:message-id:references :in-reply-to:subject:cc:to:from:date:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=abTIfV0NUvslYN+JJ8qM/z6ULA29G9L1w4hh44+bAjc=; b=c1jch4B+d24TWOFCQthchwdbBBOgDs+49ljxAqBQ6VGOL1R28nYRJbvoBaYo+fS0hN ZML4i1TVnE5CKpGKHNdZfMMiDVC+g5KNlIQHQWo0IQcOkXSu42PZ9uhyzO0RevIGAq19 M+eu4GqJDWFkEJZLCcHmmL+OFmQADSUyjS5tUOPU339u1uIXNQ4r/KcVBk/Gi/fCKBOn klpMoDCZ9EtfWLlg7KP7Sb2Fx0PRr0xNm3Sw2k/FW1emIoNAwcUnM08puFDl719pW3FS 5K5YaZ2wllLaxRCm22lIn7gABXu/comDY6iyQQ4ofbqYaaQZR+AqByF/7SMv0AYeFYG5 98gg== X-Gm-Message-State: AAQBX9eJk2K+XRyF70pNs31CSVE8RjDZhsMRvhPhhqm9gFav00CenGen ynTemHE+l6YfEgHh4t5JkPg= X-Google-Smtp-Source: AKy350ZJhmTZUY0a4Y5NGjL23ov9WqUj0Qs6cbvr828y/B8Xt0ZWIjvdC690sS0yeyhnt2pciqoLiQ== X-Received: by 2002:a17:906:631a:b0:957:1782:f80 with SMTP id sk26-20020a170906631a00b0095717820f80mr18268905ejc.7.1682545545037; Wed, 26 Apr 2023 14:45:45 -0700 (PDT) Received: from [127.0.0.1] (80-110-214-113.static.upcbusiness.at. [80.110.214.113]) by smtp.gmail.com with ESMTPSA id g23-20020a170906395700b0094f16a3ea9csm8675838eje.117.2023.04.26.14.45.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Apr 2023 14:45:44 -0700 (PDT) Date: Wed, 26 Apr 2023 23:45:41 +0200 From: Bernhard Reutner-Fischer To: Patrick O'Neill , gcc-patches@gcc.gnu.org CC: jeffreyalaw@gmail.com, schwab@linux-m68k.org Subject: Re: [PATCH v2] RISC-V: Fix sync.md and riscv.cc whitespace errors In-Reply-To: <20230426212106.1134636-1-patrick@rivosinc.com> References: <20230426205349.1131469-1-patrick@rivosinc.com> <20230426212106.1134636-1-patrick@rivosinc.com> Message-ID: <4BB13BEC-424F-43D2-AA55-41FA6E7E9D28@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-6.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,MEDICAL_SUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 26 April 2023 23:21:06 CEST, Patrick O'Neill wr= ote: >This patch fixes whitespace errors introduced with >https://gcc=2Egnu=2Eorg/pipermail/gcc-patches/2023-April/616807=2Ehtml > >2023-04-26 Patrick O'Neill > >gcc/ChangeLog: > > * config/riscv/riscv=2Ecc: Fix whitespace=2E > * config/riscv/sync=2Emd: Fix whitespace=2E The =2Emd change above is gone by now=2E No reason to resend the patch, just fixing it before you push it is fine, = once ACKed (although such patches usually counts as obvious)=2E Many thanks for the quick tweak! cheers, > >Signed-off-by: Patrick O'Neill >--- >Patch was checked with contrib/check_GNU_style=2Epy > >Whitespace changes in this patch are 2 flavors: > * Add space between function name and () > * 2 spaces between end of comment and */ >--- >v2 Changelog: > * Ignored checker warning for space before [] in rtl >--- > gcc/config/riscv/riscv=2Ecc | 6 +++--- > gcc/config/riscv/sync=2Emd | 16 ++++++++-------- > 2 files changed, 11 insertions(+), 11 deletions(-) > >diff --git a/gcc/config/riscv/riscv=2Ecc b/gcc/config/riscv/riscv=2Ecc >index 0f890469d7a=2E=2E1529855a2b4 100644 >--- a/gcc/config/riscv/riscv=2Ecc >+++ b/gcc/config/riscv/riscv=2Ecc >@@ -7193,7 +7193,7 @@ riscv_subword_address (rtx mem, rtx *aligned_mem, r= tx *shift, rtx *mask, > emit_move_insn (*mask, gen_rtx_ASHIFT (SImode, *mask, > gen_lowpart (QImode, *shift))); > >- emit_move_insn (*not_mask, gen_rtx_NOT(SImode, *mask)); >+ emit_move_insn (*not_mask, gen_rtx_NOT (SImode, *mask)); > } > > /* Leftshift a subword within an SImode register=2E */ >@@ -7206,8 +7206,8 @@ riscv_lshift_subword (machine_mode mode, rtx value,= rtx shift, > emit_move_insn (value_reg, simplify_gen_subreg (SImode, value, > mode, 0)); > >- emit_move_insn(*shifted_value, gen_rtx_ASHIFT (SImode, value_reg, >- gen_lowpart (QImode, shift))); >+ emit_move_insn (*shifted_value, gen_rtx_ASHIFT (SImode, value_reg, >+ gen_lowpart (QImode, shift))); > } > > /* Initialize the GCC target structure=2E */ >diff --git a/gcc/config/riscv/sync=2Emd b/gcc/config/riscv/sync=2Emd >index 83be6431cb6=2E=2E19274528262 100644 >--- a/gcc/config/riscv/sync=2Emd >+++ b/gcc/config/riscv/sync=2Emd >@@ -128,10 +128,10 @@ > { > /* We have no QImode/HImode atomics, so form a mask, then use > subword_atomic_fetch_strong_nand to implement a LR/SC version of th= e >- operation=2E */ >+ operation=2E */ > > /* Logic duplicated in gcc/libgcc/config/riscv/atomic=2Ec for use when= inlining >- is disabled */ >+ is disabled=2E */ > > rtx old =3D gen_reg_rtx (SImode); > rtx mem =3D operands[1]; >@@ -193,10 +193,10 @@ > { > /* We have no QImode/HImode atomics, so form a mask, then use > subword_atomic_fetch_strong_ to implement a LR/SC version of = the >- operation=2E */ >+ operation=2E */ > > /* Logic duplicated in gcc/libgcc/config/riscv/atomic=2Ec for use when= inlining >- is disabled */ >+ is disabled=2E */ > > rtx old =3D gen_reg_rtx (SImode); > rtx mem =3D operands[1]; >@@ -367,7 +367,7 @@ > { > rtx difference =3D gen_rtx_MINUS (SImode, val, exp); > compare =3D gen_reg_rtx (SImode); >- emit_move_insn (compare, difference); >+ emit_move_insn (compare, difference); > } > > if (word_mode !=3D SImode) >@@ -393,10 +393,10 @@ > { > /* We have no QImode/HImode atomics, so form a mask, then use > subword_atomic_cas_strong to implement a LR/SC version of the >- operation=2E */ >+ operation=2E */ > > /* Logic duplicated in gcc/libgcc/config/riscv/atomic=2Ec for use when= inlining >- is disabled */ >+ is disabled=2E */ > > rtx old =3D gen_reg_rtx (SImode); > rtx mem =3D operands[1]; >@@ -461,7 +461,7 @@ > "TARGET_ATOMIC" > { > /* We have no QImode atomics, so use the address LSBs to form a mask, >- then use an aligned SImode atomic=2E */ >+ then use an aligned SImode atomic=2E */ > rtx result =3D operands[0]; > rtx mem =3D operands[1]; > rtx model =3D operands[2]; >-- >2=2E34=2E1 >