From: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>
To: 丁乐华 <lehua.ding@rivai.ai>, gcc-patches <gcc-patches@gcc.gnu.org>
Cc: "kito.cheng" <kito.cheng@gmail.com>,
"Robin Dapp" <rdapp.gcc@gmail.com>, palmer <palmer@rivosinc.com>,
jeffreyalaw <jeffreyalaw@gmail.com>, 丁乐华 <lehua.ding@rivai.ai>
Subject: Re: [PATCH V2 11/14] RISC-V: P11: Adjust vector_block_info to vsetvl_block_info class
Date: Wed, 18 Oct 2023 12:06:13 +0800 [thread overview]
Message-ID: <4BF296D3A33427F5+2023101812061334398760@rivai.ai> (raw)
In-Reply-To: <20231017113500.1160997-12-lehua.ding@rivai.ai>
[-- Attachment #1: Type: text/plain, Size: 3858 bytes --]
+ const vsetvl_info &get_header_info () const
+ {
+ gcc_assert (!empty_p ());
+ return infos.is_empty () ? m_info : infos[0];
+ }
Change it into get_entry_info (be consistent with mode-switching naming which also uses LCM).
+ const vsetvl_info &get_footer_info () const
+ {
+ gcc_assert (!empty_p ());
+ return infos.is_empty () ? m_info : infos[infos.length () - 1];
+ }
Change it into get_exit_info (be consistent with mode-switching naming which also uses LCM).
juzhe.zhong@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 11/14] RISC-V: P11: Adjust vector_block_info to vsetvl_block_info class
This sub-patch adjust vector_block_info codes and rename to
vsetvl_block_info.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (class vsetvl_block_info): New.
* config/riscv/riscv-vsetvl.h (struct vector_block_info): Removed.
---
gcc/config/riscv/riscv-vsetvl.cc | 55 +++++++++++++++++++++++++++++++-
gcc/config/riscv/riscv-vsetvl.h | 14 --------
2 files changed, 54 insertions(+), 15 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index b5ed1ea774a..d91b0272d9f 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -85,7 +85,6 @@ along with GCC; see the file COPYING3. If not see
#include "predict.h"
#include "profile-count.h"
#include "gcse.h"
-#include "riscv-vsetvl.h"
using namespace rtl_ssa;
using namespace riscv_vector;
@@ -1218,6 +1217,60 @@ public:
}
};
+class vsetvl_block_info
+{
+public:
+ /* The static execute probability of the demand info. */
+ profile_probability probability;
+
+ auto_vec<vsetvl_info> infos;
+ vsetvl_info m_info;
+ bb_info *m_bb;
+
+ bool full_available;
+
+ vsetvl_block_info () : m_bb (nullptr), full_available (false)
+ {
+ infos.safe_grow_cleared (0);
+ m_info.set_empty ();
+ }
+ vsetvl_block_info (const vsetvl_block_info &other)
+ : probability (other.probability), infos (other.infos.copy ()),
+ m_info (other.m_info), m_bb (other.m_bb)
+ {}
+
+ vsetvl_info &get_header_info ()
+ {
+ gcc_assert (!empty_p ());
+ return infos.is_empty () ? m_info : infos[0];
+ }
+ vsetvl_info &get_footer_info ()
+ {
+ gcc_assert (!empty_p ());
+ return infos.is_empty () ? m_info : infos[infos.length () - 1];
+ }
+ const vsetvl_info &get_header_info () const
+ {
+ gcc_assert (!empty_p ());
+ return infos.is_empty () ? m_info : infos[0];
+ }
+ const vsetvl_info &get_footer_info () const
+ {
+ gcc_assert (!empty_p ());
+ return infos.is_empty () ? m_info : infos[infos.length () - 1];
+ }
+
+ bool empty_p () const { return infos.is_empty () && !has_info (); }
+ bool has_info () const { return !m_info.empty_p (); }
+ void set_info (const vsetvl_info &info)
+ {
+ gcc_assert (infos.is_empty ());
+ m_info = info;
+ m_info.set_bb (m_bb);
+ }
+ void set_empty_info () { m_info.set_empty (); }
+};
+
class demand_system
{
private:
diff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vsetvl.h
index 96e36403af7..16c84e0684b 100644
--- a/gcc/config/riscv/riscv-vsetvl.h
+++ b/gcc/config/riscv/riscv-vsetvl.h
@@ -55,19 +55,5 @@ enum def_type
CLOBBER_DEF = 1 << 4
};
-struct vector_block_info
-{
- /* The local_dem vector insn_info of the block. */
- vector_insn_info local_dem;
-
- /* The reaching_out vector insn_info of the block. */
- vector_insn_info reaching_out;
-
- /* The static execute probability of the demand info. */
- profile_probability probability;
-
- vector_block_info () = default;
-};
-
} // namespace riscv_vector
#endif
--
2.36.3
next prev parent reply other threads:[~2023-10-18 4:06 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-17 11:34 [PATCH V2 00/14] Refactor and cleanup vsetvl pass Lehua Ding
2023-10-17 11:34 ` [PATCH V2 01/14] RISC-V: P1: Refactor avl_info/vl_vtype_info/vector_insn_info Lehua Ding
2023-10-17 12:32 ` juzhe.zhong
2023-10-17 15:23 ` 钟居哲
2023-10-18 2:30 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 02/14] RISC-V: P2: Refactor and cleanup demand system Lehua Ding
2023-10-18 3:43 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 03/14] RISC-V: P3: Refactor vector_infos_manager Lehua Ding
2023-10-18 3:58 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 04/14] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl Lehua Ding
2023-10-18 4:02 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 05/14] RISC-V: P5: combine phase 1 and 2 Lehua Ding
2023-10-18 4:07 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 06/14] RISC-V: P6: Add computing reaching definition data flow Lehua Ding
2023-10-18 4:12 ` juzhe.zhong
2023-10-18 4:13 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 07/14] RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class Lehua Ding
2023-10-18 4:14 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 08/14] RISC-V: P8: Unified insert and delete of vsetvl insn into Phase 4 Lehua Ding
2023-10-18 4:15 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 09/14] RISC-V: P9: Cleanup post optimize phase Lehua Ding
2023-10-18 4:15 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 10/14] RISC-V: P10: Cleanup helper functions Lehua Ding
2023-10-18 4:16 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 11/14] RISC-V: P11: Adjust vector_block_info to vsetvl_block_info class Lehua Ding
2023-10-18 4:06 ` juzhe.zhong [this message]
2023-10-17 11:34 ` [PATCH V2 12/14] RISC-V: P12: Delete riscv-vsetvl.h Lehua Ding
2023-10-18 4:16 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 13/14] RISC-V: P13: Reorganize functions used to modify RTL Lehua Ding
2023-10-18 4:17 ` juzhe.zhong
2023-10-17 11:35 ` [PATCH V2 14/14] RISC-V: P14: Adjust and add testcases Lehua Ding
2023-10-18 4:17 ` juzhe.zhong
2023-10-17 20:25 ` [PATCH V2 00/14] Refactor and cleanup vsetvl pass Patrick O'Neill
2023-10-18 2:20 ` Lehua Ding
2023-10-18 9:14 ` Lehua Ding
2023-10-18 17:17 ` Patrick O'Neill
2023-10-19 8:41 ` Lehua Ding
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=4BF296D3A33427F5+2023101812061334398760@rivai.ai \
--to=juzhe.zhong@rivai.ai \
--cc=gcc-patches@gcc.gnu.org \
--cc=jeffreyalaw@gmail.com \
--cc=kito.cheng@gmail.com \
--cc=lehua.ding@rivai.ai \
--cc=palmer@rivosinc.com \
--cc=rdapp.gcc@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).