From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3002 invoked by alias); 5 Jul 2010 12:47:13 -0000 Received: (qmail 2991 invoked by uid 22791); 5 Jul 2010 12:47:12 -0000 X-SWARE-Spam-Status: No, hits=-2.0 required=5.0 tests=AWL,BAYES_00,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 05 Jul 2010 12:47:07 +0000 Received: (qmail 17763 invoked from network); 5 Jul 2010 12:47:06 -0000 Received: from unknown (HELO ?192.168.0.124?) (jie@127.0.0.2) by mail.codesourcery.com with ESMTPA; 5 Jul 2010 12:47:06 -0000 Message-ID: <4C31D447.4040304@codesourcery.com> Date: Mon, 05 Jul 2010 12:47:00 -0000 From: Jie Zhang User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.4) Gecko/20100608 Lightning/1.0b2 Thunderbird/3.1 MIME-Version: 1.0 To: Richard Earnshaw CC: gcc-patches@gcc.gnu.org, Richard Henderson Subject: Re: [ARM] Remove register constraints from push multiple patterns (was Re: [PATCH] Provide a hook for target to disable register renaming for some instructions) References: <4C2B84B7.2000506@codesourcery.com> <4C2B86EF.6020900@redhat.com> <4C2C95F5.9000000@codesourcery.com> <1277991469.22174.30.camel@e102346-lin.cambridge.arm.com> <4C2F68D8.1060801@codesourcery.com> <1278319909.22174.119.camel@e102346-lin.cambridge.arm.com> In-Reply-To: <1278319909.22174.119.camel@e102346-lin.cambridge.arm.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2010-07/txt/msg00371.txt.bz2 On 07/05/2010 04:51 PM, Richard Earnshaw wrote: > > On Sun, 2010-07-04 at 00:44 +0800, Jie Zhang wrote: >> On 07/01/2010 09:37 PM, Richard Earnshaw wrote: >>> >>> On Thu, 2010-07-01 at 21:19 +0800, Jie Zhang wrote: >>>> On 07/01/2010 02:03 AM, Richard Henderson wrote: >>>>> On 06/30/2010 10:53 AM, Jie Zhang wrote: >>>>>> When compiler an application for ARM, the GAS issued a warning: >>>>>> >>>>>> Warning: register range not in ascending order >>>>>> >>>>>> for the instruction >>>>>> >>>>>> push {ip, r3, r4, lr} >>>>>> >>>>>> Before regrename pass, this instruction looked like >>>>>> >>>>>> push {r0, r3, r4, lr} >>>>> >>>>> Doesn't it work just as well to simply remove the register >>>>> constraint from the push_multi instruction? Without that >>>>> the regrename pass won't get a register class for the >>>>> operand and will leave it alone. >>>>> >>>> According to Richard's comment, a new patch is attached. It removes >>>> register constraints from all three push multiple patterns. Since there >>>> are no constraints for operand 1 of *push_multi_vfp, I use a new >>>> predicate to make it more stricter. >>>> >>>> Tested on arm-none-eabi for NEON and non-NEON. No regressions found. >>>> >>>> Is it OK? >>>> >>>> Regards, >>> >>> OK >>> >> Thanks. Committed on trunk. OK for 4.5 branch, too? >> > > Yes. > Thanks. Committed on 4.5 branch now. -- Jie Zhang CodeSourcery