* ARM: More reorganization of extend patterns (PR43137)
@ 2010-07-13 9:56 Bernd Schmidt
2010-08-04 14:56 ` Ping: " Bernd Schmidt
2010-09-01 16:02 ` Richard Earnshaw
0 siblings, 2 replies; 10+ messages in thread
From: Bernd Schmidt @ 2010-07-13 9:56 UTC (permalink / raw)
To: GCC Patches, Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 836 bytes --]
This patch merges a number of different extend:DI patterns by using a
QHSI mode_iterator. It also removes separate patterns from thumb2.md as
we can just set attr ce_count for ARM patterns as well. I've completed
what I'd partially done in my previous patch, which is to remove
unnecessary constant pool handling from these patterns - none of them
accept constants.
To fix PR43137, I've added splitters that run before the subreg2 pass.
In general, the ARM backend makes practically no use of lower-subreg; I
have given up on fixing that for the moment as it was more effort than I
can spare right now. Just doing it for these patterns is enough to be a
win in certain cases.
Regression tested (together with other patches) on
qemu-system-armv7/arch=armv7-a/thumb
qemu-system-armv7/thumb
qemu-system-armv7
Ok?
Bernd
[-- Attachment #2: extenddi.diff --]
[-- Type: text/plain, Size: 14129 bytes --]
PR target/43137
* config/arm/arm.md (zero_extendsidi2, arm_zero_extendsidi2,
arm_exxtendsidi2, arm_extendsidi2): Delete patterns.
(qhs_zextenddi_cond, qhs_sextenddi_cond): New define_mode_attrs.
(zero_extend<mode>di2, extend<mode>di2 and related splits): New.
(thumb1_zero_extendhisi2): Remove code to handle LABEL_REFs.
Remove pool_range attribute.
(arm_zero_extendhisi2, arm_zero_extendhisi2_v6, arm_zero_extendqisi2,
arm_zero_extendqisi2_v6, thumb1_zero_extendqisi2_v6): Remove
pool_range and neg_pool_range attributes.
* config/arm/thumb2.md (thumb2_zero_extendsidi2,
thumb2_zero_extendhidi2, thumb2_zero_extendqidi2, thumb2_extendsidi2,
thumb2_extendhidi2, thumb2_extendqidi2): Delete.
PR target/43137
* gcc.target/arm/pr43137.c: New test.
Index: gcc/config/arm/arm.md
===================================================================
--- gcc.orig/config/arm/arm.md
+++ gcc/config/arm/arm.md
@@ -3990,69 +3990,82 @@
\f
;; Zero and sign extension instructions.
-(define_expand "zero_extendsidi2"
- [(set (match_operand:DI 0 "s_register_operand" "")
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")))]
- "TARGET_32BIT"
- ""
-)
+(define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
+(define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
+ (QI "&& arm_arch6")])
-(define_insn "*arm_zero_extendsidi2"
+(define_insn "zero_extend<mode>di2"
[(set (match_operand:DI 0 "s_register_operand" "=r")
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_ARM"
- "*
- if (REGNO (operands[1])
- != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0))
- output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
- return \"mov%?\\t%R0, #0\";
- "
+ (zero_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))]
+ "TARGET_32BIT <qhs_zextenddi_cond>"
+ "#"
[(set_attr "length" "8")
- (set_attr "predicable" "yes")]
-)
+ (set_attr "ce_count" "2")
+ (set_attr "predicable" "yes")])
-(define_expand "zero_extendqidi2"
- [(set (match_operand:DI 0 "s_register_operand" "")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
- "TARGET_32BIT"
- ""
-)
-
-(define_insn "*arm_zero_extendqidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,r")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_ARM"
- "@
- and%?\\t%Q0, %1, #255\;mov%?\\t%R0, #0
- ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
+(define_insn "extend<mode>di2"
+ [(set (match_operand:DI 0 "s_register_operand" "=r")
+ (sign_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))]
+ "TARGET_32BIT <qhs_sextenddi_cond>"
+ "#"
[(set_attr "length" "8")
- (set_attr "predicable" "yes")
- (set_attr "type" "*,load_byte")
- (set_attr "pool_range" "*,4092")
- (set_attr "neg_pool_range" "*,4084")]
-)
+ (set_attr "ce_count" "2")
+ (set_attr "shift" "1")
+ (set_attr "predicable" "yes")])
-(define_expand "extendsidi2"
+;; Splits for all extensions to DImode
+(define_split
[(set (match_operand:DI 0 "s_register_operand" "")
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")))]
+ (zero_extend:DI (match_operand 1 "nonimmediate_operand" "")))]
"TARGET_32BIT"
- ""
-)
+ [(set (match_dup 0) (match_dup 1))]
+{
+ rtx insn;
+ rtx lo_part = gen_lowpart (SImode, operands[0]);
+ enum machine_mode src_mode = GET_MODE (operands[1]);
+
+ if (REG_P (operands[0])
+ && !reg_overlap_mentioned_p (operands[0], operands[1]))
+ emit_clobber (operands[0]);
+ if (!REG_P (lo_part) || src_mode != SImode
+ || !rtx_equal_p (lo_part, operands[1]))
+ {
+ if (src_mode == SImode)
+ emit_move_insn (lo_part, operands[1]);
+ else
+ emit_insn (gen_rtx_SET (VOIDmode, lo_part,
+ gen_rtx_ZERO_EXTEND (SImode, operands[1])));
+ operands[1] = lo_part;
+ }
+ operands[0] = gen_highpart (SImode, operands[0]);
+ operands[1] = const0_rtx;
+})
-(define_insn "*arm_extendsidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r")
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_ARM"
- "*
- if (REGNO (operands[1])
- != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0))
- output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
- return \"mov%?\\t%R0, %Q0, asr #31\";
- "
- [(set_attr "length" "8")
- (set_attr "shift" "1")
- (set_attr "predicable" "yes")]
-)
+(define_split
+ [(set (match_operand:DI 0 "s_register_operand" "")
+ (sign_extend:DI (match_operand 1 "nonimmediate_operand" "")))]
+ "TARGET_32BIT"
+ [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
+{
+ rtx lo_part = gen_lowpart (SImode, operands[0]);
+ enum machine_mode src_mode = GET_MODE (operands[1]);
+
+ if (REG_P (operands[0])
+ && !reg_overlap_mentioned_p (operands[0], operands[1]))
+ emit_clobber (operands[0]);
+
+ if (!REG_P (lo_part) || src_mode != SImode
+ || !rtx_equal_p (lo_part, operands[1]))
+ {
+ if (src_mode == SImode)
+ emit_move_insn (lo_part, operands[1]);
+ else
+ emit_insn (gen_rtx_SET (VOIDmode, lo_part,
+ gen_rtx_SIGN_EXTEND (SImode, operands[1])));
+ operands[1] = lo_part;
+ }
+ operands[0] = gen_highpart (SImode, operands[0]);
+})
(define_expand "zero_extendhisi2"
[(set (match_operand:SI 0 "s_register_operand" "")
@@ -4088,26 +4101,22 @@
[(set (match_operand:SI 0 "register_operand" "=l,l")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m")))]
"TARGET_THUMB1"
- "*
+{
rtx mem;
if (which_alternative == 0 && arm_arch6)
- return \"uxth\\t%0, %1\";
+ return "uxth\t%0, %1";
if (which_alternative == 0)
- return \"#\";
+ return "#";
mem = XEXP (operands[1], 0);
if (GET_CODE (mem) == CONST)
mem = XEXP (mem, 0);
- if (GET_CODE (mem) == LABEL_REF)
- return \"ldr\\t%0, %1\";
-
if (GET_CODE (mem) == PLUS)
{
rtx a = XEXP (mem, 0);
- rtx b = XEXP (mem, 1);
/* This can happen due to bugs in reload. */
if (GET_CODE (a) == REG && REGNO (a) == SP_REGNUM)
@@ -4116,25 +4125,19 @@
ops[0] = operands[0];
ops[1] = a;
- output_asm_insn (\"mov %0, %1\", ops);
+ output_asm_insn ("mov\t%0, %1", ops);
XEXP (mem, 0) = operands[0];
}
-
- else if ( GET_CODE (a) == LABEL_REF
- && GET_CODE (b) == CONST_INT)
- return \"ldr\\t%0, %1\";
}
- return \"ldrh\\t%0, %1\";
- "
+ return "ldrh\t%0, %1";
+}
[(set_attr_alternative "length"
[(if_then_else (eq_attr "is_arch6" "yes")
(const_int 2) (const_int 4))
(const_int 4)])
- (set_attr "type" "alu_shift,load_byte")
- (set_attr "pool_range" "*,60")]
-)
+ (set_attr "type" "alu_shift,load_byte")])
(define_insn "*arm_zero_extendhisi2"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
@@ -4144,10 +4147,7 @@
#
ldr%(h%)\\t%0, %1"
[(set_attr "type" "alu_shift,load_byte")
- (set_attr "predicable" "yes")
- (set_attr "pool_range" "*,256")
- (set_attr "neg_pool_range" "*,244")]
-)
+ (set_attr "predicable" "yes")])
(define_insn "*arm_zero_extendhisi2_v6"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
@@ -4157,10 +4157,7 @@
uxth%?\\t%0, %1
ldr%(h%)\\t%0, %1"
[(set_attr "type" "alu_shift,load_byte")
- (set_attr "predicable" "yes")
- (set_attr "pool_range" "*,256")
- (set_attr "neg_pool_range" "*,244")]
-)
+ (set_attr "predicable" "yes")])
(define_insn "*arm_zero_extendhisi2addsi"
[(set (match_operand:SI 0 "s_register_operand" "=r")
@@ -4228,10 +4225,8 @@
"@
uxtb\\t%0, %1
ldrb\\t%0, %1"
- [(set_attr "length" "2,2")
- (set_attr "type" "alu_shift,load_byte")
- (set_attr "pool_range" "*,32")]
-)
+ [(set_attr "length" "2")
+ (set_attr "type" "alu_shift,load_byte")])
(define_insn "*arm_zero_extendqisi2"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
@@ -4242,10 +4237,7 @@
ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "length" "8,4")
(set_attr "type" "alu_shift,load_byte")
- (set_attr "predicable" "yes")
- (set_attr "pool_range" "*,4096")
- (set_attr "neg_pool_range" "*,4084")]
-)
+ (set_attr "predicable" "yes")])
(define_insn "*arm_zero_extendqisi2_v6"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
@@ -4255,10 +4247,7 @@
uxtb%(%)\\t%0, %1
ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "type" "alu_shift,load_byte")
- (set_attr "predicable" "yes")
- (set_attr "pool_range" "*,4096")
- (set_attr "neg_pool_range" "*,4084")]
-)
+ (set_attr "predicable" "yes")])
(define_insn "*arm_zero_extendqisi2addsi"
[(set (match_operand:SI 0 "s_register_operand" "=r")
Index: gcc/config/arm/thumb2.md
===================================================================
--- gcc.orig/config/arm/thumb2.md
+++ gcc/config/arm/thumb2.md
@@ -792,145 +792,6 @@
;; Zero and sign extension instructions.
-(define_insn_and_split "*thumb2_zero_extendsidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r")
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_THUMB2"
- "mov%?\\t%Q0, %1\;mov%?\\t%R0, #0"
- "&& reload_completed"
- [(set (match_dup 0) (match_dup 1))]
- "
- {
- rtx lo_part = gen_lowpart (SImode, operands[0]);
- if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
- emit_move_insn (lo_part, operands[1]);
- operands[0] = gen_highpart (SImode, operands[0]);
- operands[1] = const0_rtx;
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn_and_split "*thumb2_zero_extendhidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,r")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_THUMB2"
- "@
- uxth%?\\t%Q0, %1\;mov%?\\t%R0, #0
- ldr%(h%)\\t%Q0, %1\;mov%?\\t%R0, #0"
- "&& reload_completed"
- [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
- (set (match_dup 2) (match_dup 3))]
- "
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[3] = const0_rtx;
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")
- (set_attr "type" "*,load_byte")
- (set_attr "pool_range" "*,4092")
- (set_attr "neg_pool_range" "*,250")]
-)
-
-(define_insn_and_split "*thumb2_zero_extendqidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,r")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_THUMB2"
- "@
- uxtb%?\\t%Q0, %1\;mov%?\\t%R0, #0
- ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
- "&& reload_completed"
- [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
- (set (match_dup 2) (match_dup 3))]
- "
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[3] = const0_rtx;
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")
- (set_attr "type" "*,load_byte")
- (set_attr "pool_range" "*,4092")
- (set_attr "neg_pool_range" "*,250")]
-)
-
-(define_insn_and_split "*thumb2_extendsidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r")
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_THUMB2"
- "mov%?\\t%Q0, %1\;asr?\\t%R0, %1, #31"
- "&& reload_completed"
- [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
- {
- rtx lo_part = gen_lowpart (SImode, operands[0]);
-
- if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
- emit_move_insn (lo_part, operands[1]);
- operands[0] = gen_highpart (SImode, operands[0]);
- }
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "shift" "1")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn_and_split "*thumb2_extendhidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,r")
- (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_THUMB2"
- "@
- sxth%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31
- ldrsh%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31"
- "&& reload_completed"
- [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
- (set (match_dup 2) (ashiftrt:SI (match_dup 0) (const_int 31)))]
- "
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")
- (set_attr "type" "*,load_byte")
- (set_attr "pool_range" "*,4092")
- (set_attr "neg_pool_range" "*,250")]
-)
-
-(define_insn_and_split "*thumb2_extendqidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,r")
- (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_THUMB2"
- "@
- sxtb%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31
- ldrsb%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31"
- "&& reload_completed"
- [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
- (set (match_dup 2) (ashiftrt:SI (match_dup 0) (const_int 31)))]
- "
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")
- (set_attr "type" "*,load_byte")
- (set_attr "pool_range" "*,4092")
- (set_attr "neg_pool_range" "*,250")]
-)
-
;; All supported Thumb2 implementations are armv6, so only that case is
;; provided.
(define_insn "*thumb2_extendqisi_v6"
Index: testsuite/gcc.target/arm/pr43137.c
===================================================================
--- testsuite/gcc.target/arm/pr43137.c (revision 0)
+++ testsuite/gcc.target/arm/pr43137.c (revision 0)
@@ -0,0 +1,9 @@
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "mov\tr1, r\[1-9\]" } } */
+
+int foo();
+long long bar22()
+{
+ int result = foo();
+ return result;
+}
^ permalink raw reply [flat|nested] 10+ messages in thread
* Ping: ARM: More reorganization of extend patterns (PR43137)
2010-07-13 9:56 ARM: More reorganization of extend patterns (PR43137) Bernd Schmidt
@ 2010-08-04 14:56 ` Bernd Schmidt
2010-08-24 13:09 ` Ping^2: " Bernd Schmidt
2010-09-01 16:02 ` Richard Earnshaw
1 sibling, 1 reply; 10+ messages in thread
From: Bernd Schmidt @ 2010-08-04 14:56 UTC (permalink / raw)
To: GCC Patches, Richard Earnshaw
On 07/13/2010 11:56 AM, Bernd Schmidt wrote:
> This patch merges a number of different extend:DI patterns by using a
> QHSI mode_iterator. It also removes separate patterns from thumb2.md as
> we can just set attr ce_count for ARM patterns as well. I've completed
> what I'd partially done in my previous patch, which is to remove
> unnecessary constant pool handling from these patterns - none of them
> accept constants.
>
> To fix PR43137, I've added splitters that run before the subreg2 pass.
> In general, the ARM backend makes practically no use of lower-subreg; I
> have given up on fixing that for the moment as it was more effort than I
> can spare right now. Just doing it for these patterns is enough to be a
> win in certain cases.
http://gcc.gnu.org/ml/gcc-patches/2010-07/msg01036.html
Bernd
^ permalink raw reply [flat|nested] 10+ messages in thread
* Ping^2: ARM: More reorganization of extend patterns (PR43137)
2010-08-04 14:56 ` Ping: " Bernd Schmidt
@ 2010-08-24 13:09 ` Bernd Schmidt
0 siblings, 0 replies; 10+ messages in thread
From: Bernd Schmidt @ 2010-08-24 13:09 UTC (permalink / raw)
To: GCC Patches, Richard Earnshaw, Paul Brook
On 08/04/2010 04:56 PM, Bernd Schmidt wrote:
> On 07/13/2010 11:56 AM, Bernd Schmidt wrote:
>> This patch merges a number of different extend:DI patterns by using a
>> QHSI mode_iterator. It also removes separate patterns from thumb2.md as
>> we can just set attr ce_count for ARM patterns as well. I've completed
>> what I'd partially done in my previous patch, which is to remove
>> unnecessary constant pool handling from these patterns - none of them
>> accept constants.
>>
>> To fix PR43137, I've added splitters that run before the subreg2 pass.
>> In general, the ARM backend makes practically no use of lower-subreg; I
>> have given up on fixing that for the moment as it was more effort than I
>> can spare right now. Just doing it for these patterns is enough to be a
>> win in certain cases.
http://gcc.gnu.org/ml/gcc-patches/2010-07/msg01036.html
Bernd
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ARM: More reorganization of extend patterns (PR43137)
2010-07-13 9:56 ARM: More reorganization of extend patterns (PR43137) Bernd Schmidt
2010-08-04 14:56 ` Ping: " Bernd Schmidt
@ 2010-09-01 16:02 ` Richard Earnshaw
2010-09-06 23:13 ` Bernd Schmidt
2010-09-15 22:47 ` Bernd Schmidt
1 sibling, 2 replies; 10+ messages in thread
From: Richard Earnshaw @ 2010-09-01 16:02 UTC (permalink / raw)
To: Bernd Schmidt; +Cc: GCC Patches
On Tue, 2010-07-13 at 10:56 +0100, Bernd Schmidt wrote:
> This patch merges a number of different extend:DI patterns by using a
> QHSI mode_iterator. It also removes separate patterns from thumb2.md
> as
> we can just set attr ce_count for ARM patterns as well. I've
> completed
> what I'd partially done in my previous patch, which is to remove
> unnecessary constant pool handling from these patterns - none of them
> accept constants.
>
> To fix PR43137, I've added splitters that run before the subreg2 pass.
> In general, the ARM backend makes practically no use of lower-subreg;
> I
> have given up on fixing that for the moment as it was more effort than
> I
> can spare right now. Just doing it for these patterns is enough to be
> a
> win in certain cases.
>
> Regression tested (together with other patches) on
> qemu-system-armv7/arch=armv7-a/thumb
> qemu-system-armv7/thumb
> qemu-system-armv7
>
> Ok?
>
The define_mode_attrs need to be moved to iterators.md. Also, a number
of patterns have been changed (inconsistently with the rest of arm.md)
to not have the terminating ')' in column 1.
Otherwise, OK.
R.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ARM: More reorganization of extend patterns (PR43137)
2010-09-01 16:02 ` Richard Earnshaw
@ 2010-09-06 23:13 ` Bernd Schmidt
2010-09-07 21:29 ` Ramana Radhakrishnan
2010-09-15 22:47 ` Bernd Schmidt
1 sibling, 1 reply; 10+ messages in thread
From: Bernd Schmidt @ 2010-09-06 23:13 UTC (permalink / raw)
To: Richard Earnshaw; +Cc: GCC Patches
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On 09/01/2010 05:52 PM, Richard Earnshaw wrote:
>
> On Tue, 2010-07-13 at 10:56 +0100, Bernd Schmidt wrote:
>> This patch merges a number of different extend:DI patterns by using a
>> QHSI mode_iterator. It also removes separate patterns from thumb2.md
>> as
>> we can just set attr ce_count for ARM patterns as well. I've
>> completed
>> what I'd partially done in my previous patch, which is to remove
>> unnecessary constant pool handling from these patterns - none of them
>> accept constants.
> The define_mode_attrs need to be moved to iterators.md. Also, a number
> of patterns have been changed (inconsistently with the rest of arm.md)
> to not have the terminating ')' in column 1.
>
> Otherwise, OK.
Thanks. Here's what I committed.
Bernd
[-- Attachment #2: extenddi2.diff --]
[-- Type: text/plain, Size: 15506 bytes --]
Index: ChangeLog
===================================================================
--- ChangeLog (revision 163934)
+++ ChangeLog (working copy)
@@ -1,3 +1,20 @@
+2010-09-07 Bernd Schmidt <bernds@codesourcery.com>
+
+ PR target/43137
+ * config/arm/iterators.md (qhs_zextenddi_cond, qhs_sextenddi_cond):
+ New define_mode_attrs.
+ * config/arm/arm.md (zero_extendsidi2, arm_zero_extendsidi2,
+ arm_exxtendsidi2, arm_extendsidi2): Delete patterns.
+ (zero_extend<mode>di2, extend<mode>di2 and related splits): New.
+ (thumb1_zero_extendhisi2): Remove code to handle LABEL_REFs.
+ Remove pool_range attribute.
+ (arm_zero_extendhisi2, arm_zero_extendhisi2_v6, arm_zero_extendqisi2,
+ arm_zero_extendqisi2_v6, thumb1_zero_extendqisi2_v6): Remove
+ pool_range and neg_pool_range attributes.
+ * config/arm/thumb2.md (thumb2_zero_extendsidi2,
+ thumb2_zero_extendhidi2, thumb2_zero_extendqidi2, thumb2_extendsidi2,
+ thumb2_extendhidi2, thumb2_extendqidi2): Delete.
+
2010-09-06 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/linux-unwind.h (x86_fallback_frame_state): Properly
Index: config/arm/thumb2.md
===================================================================
--- config/arm/thumb2.md (revision 163792)
+++ config/arm/thumb2.md (working copy)
@@ -557,145 +557,6 @@ (define_insn "*thumb2_movcond"
;; Zero and sign extension instructions.
-(define_insn_and_split "*thumb2_zero_extendsidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r")
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_THUMB2"
- "mov%?\\t%Q0, %1\;mov%?\\t%R0, #0"
- "&& reload_completed"
- [(set (match_dup 0) (match_dup 1))]
- "
- {
- rtx lo_part = gen_lowpart (SImode, operands[0]);
- if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
- emit_move_insn (lo_part, operands[1]);
- operands[0] = gen_highpart (SImode, operands[0]);
- operands[1] = const0_rtx;
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn_and_split "*thumb2_zero_extendhidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,r")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_THUMB2"
- "@
- uxth%?\\t%Q0, %1\;mov%?\\t%R0, #0
- ldr%(h%)\\t%Q0, %1\;mov%?\\t%R0, #0"
- "&& reload_completed"
- [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
- (set (match_dup 2) (match_dup 3))]
- "
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[3] = const0_rtx;
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")
- (set_attr "type" "*,load_byte")
- (set_attr "pool_range" "*,4092")
- (set_attr "neg_pool_range" "*,250")]
-)
-
-(define_insn_and_split "*thumb2_zero_extendqidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,r")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_THUMB2"
- "@
- uxtb%?\\t%Q0, %1\;mov%?\\t%R0, #0
- ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
- "&& reload_completed"
- [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
- (set (match_dup 2) (match_dup 3))]
- "
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[3] = const0_rtx;
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")
- (set_attr "type" "*,load_byte")
- (set_attr "pool_range" "*,4092")
- (set_attr "neg_pool_range" "*,250")]
-)
-
-(define_insn_and_split "*thumb2_extendsidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r")
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_THUMB2"
- "mov%?\\t%Q0, %1\;asr?\\t%R0, %1, #31"
- "&& reload_completed"
- [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
- {
- rtx lo_part = gen_lowpart (SImode, operands[0]);
-
- if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
- emit_move_insn (lo_part, operands[1]);
- operands[0] = gen_highpart (SImode, operands[0]);
- }
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "shift" "1")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn_and_split "*thumb2_extendhidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,r")
- (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_THUMB2"
- "@
- sxth%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31
- ldrsh%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31"
- "&& reload_completed"
- [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
- (set (match_dup 2) (ashiftrt:SI (match_dup 0) (const_int 31)))]
- "
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")
- (set_attr "type" "*,load_byte")
- (set_attr "pool_range" "*,4092")
- (set_attr "neg_pool_range" "*,250")]
-)
-
-(define_insn_and_split "*thumb2_extendqidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,r")
- (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_THUMB2"
- "@
- sxtb%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31
- ldrsb%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31"
- "&& reload_completed"
- [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
- (set (match_dup 2) (ashiftrt:SI (match_dup 0) (const_int 31)))]
- "
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")
- (set_attr "type" "*,load_byte")
- (set_attr "pool_range" "*,4092")
- (set_attr "neg_pool_range" "*,250")]
-)
-
;; All supported Thumb2 implementations are armv6, so only that case is
;; provided.
(define_insn "*thumb2_extendqisi_v6"
Index: config/arm/iterators.md
===================================================================
--- config/arm/iterators.md (revision 163792)
+++ config/arm/iterators.md (working copy)
@@ -370,6 +370,11 @@ (define_mode_attr V_widen_l [(V8QI "v8hi
;; Widen. Result is half the number of elements, but widened to double-width.
(define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])
+;; Conditions to be used in extend<mode>di patterns.
+(define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
+(define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
+ (QI "&& arm_arch6")])
+
;;----------------------------------------------------------------------------
;; Code attributes
;;----------------------------------------------------------------------------
Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md (revision 163792)
+++ config/arm/arm.md (working copy)
@@ -4037,71 +4037,80 @@ (define_expand "truncdfhf2"
\f
;; Zero and sign extension instructions.
-(define_expand "zero_extendsidi2"
- [(set (match_operand:DI 0 "s_register_operand" "")
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")))]
- "TARGET_32BIT"
- ""
+(define_insn "zero_extend<mode>di2"
+ [(set (match_operand:DI 0 "s_register_operand" "=r")
+ (zero_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))]
+ "TARGET_32BIT <qhs_zextenddi_cond>"
+ "#"
+ [(set_attr "length" "8")
+ (set_attr "ce_count" "2")
+ (set_attr "predicable" "yes")]
)
-(define_insn "*arm_zero_extendsidi2"
+(define_insn "extend<mode>di2"
[(set (match_operand:DI 0 "s_register_operand" "=r")
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_ARM"
- "*
- if (REGNO (operands[1])
- != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0))
- output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
- return \"mov%?\\t%R0, #0\";
- "
+ (sign_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))]
+ "TARGET_32BIT <qhs_sextenddi_cond>"
+ "#"
[(set_attr "length" "8")
- (set_attr "insn" "mov")
+ (set_attr "ce_count" "2")
+ (set_attr "shift" "1")
(set_attr "predicable" "yes")]
)
-(define_expand "zero_extendqidi2"
- [(set (match_operand:DI 0 "s_register_operand" "")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
+;; Splits for all extensions to DImode
+(define_split
+ [(set (match_operand:DI 0 "s_register_operand" "")
+ (zero_extend:DI (match_operand 1 "nonimmediate_operand" "")))]
"TARGET_32BIT"
- ""
-)
+ [(set (match_dup 0) (match_dup 1))]
+{
+ rtx insn;
+ rtx lo_part = gen_lowpart (SImode, operands[0]);
+ enum machine_mode src_mode = GET_MODE (operands[1]);
-(define_insn "*arm_zero_extendqidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,r")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_ARM"
- "@
- and%?\\t%Q0, %1, #255\;mov%?\\t%R0, #0
- ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
- [(set_attr "length" "8")
- (set_attr "predicable" "yes")
- (set_attr "type" "*,load_byte")
- (set_attr "pool_range" "*,4092")
- (set_attr "neg_pool_range" "*,4084")]
-)
+ if (REG_P (operands[0])
+ && !reg_overlap_mentioned_p (operands[0], operands[1]))
+ emit_clobber (operands[0]);
+ if (!REG_P (lo_part) || src_mode != SImode
+ || !rtx_equal_p (lo_part, operands[1]))
+ {
+ if (src_mode == SImode)
+ emit_move_insn (lo_part, operands[1]);
+ else
+ emit_insn (gen_rtx_SET (VOIDmode, lo_part,
+ gen_rtx_ZERO_EXTEND (SImode, operands[1])));
+ operands[1] = lo_part;
+ }
+ operands[0] = gen_highpart (SImode, operands[0]);
+ operands[1] = const0_rtx;
+})
-(define_expand "extendsidi2"
+(define_split
[(set (match_operand:DI 0 "s_register_operand" "")
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")))]
+ (sign_extend:DI (match_operand 1 "nonimmediate_operand" "")))]
"TARGET_32BIT"
- ""
-)
+ [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
+{
+ rtx lo_part = gen_lowpart (SImode, operands[0]);
+ enum machine_mode src_mode = GET_MODE (operands[1]);
-(define_insn "*arm_extendsidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r")
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_ARM"
- "*
- if (REGNO (operands[1])
- != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0))
- output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
- return \"mov%?\\t%R0, %Q0, asr #31\";
- "
- [(set_attr "length" "8")
- (set_attr "shift" "1")
- (set_attr "insn" "mov")
- (set_attr "predicable" "yes")]
-)
+ if (REG_P (operands[0])
+ && !reg_overlap_mentioned_p (operands[0], operands[1]))
+ emit_clobber (operands[0]);
+
+ if (!REG_P (lo_part) || src_mode != SImode
+ || !rtx_equal_p (lo_part, operands[1]))
+ {
+ if (src_mode == SImode)
+ emit_move_insn (lo_part, operands[1]);
+ else
+ emit_insn (gen_rtx_SET (VOIDmode, lo_part,
+ gen_rtx_SIGN_EXTEND (SImode, operands[1])));
+ operands[1] = lo_part;
+ }
+ operands[0] = gen_highpart (SImode, operands[0]);
+})
(define_expand "zero_extendhisi2"
[(set (match_operand:SI 0 "s_register_operand" "")
@@ -4137,26 +4146,22 @@ (define_insn "*thumb1_zero_extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=l,l")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m")))]
"TARGET_THUMB1"
- "*
+{
rtx mem;
if (which_alternative == 0 && arm_arch6)
- return \"uxth\\t%0, %1\";
+ return "uxth\t%0, %1";
if (which_alternative == 0)
- return \"#\";
+ return "#";
mem = XEXP (operands[1], 0);
if (GET_CODE (mem) == CONST)
mem = XEXP (mem, 0);
- if (GET_CODE (mem) == LABEL_REF)
- return \"ldr\\t%0, %1\";
-
if (GET_CODE (mem) == PLUS)
{
rtx a = XEXP (mem, 0);
- rtx b = XEXP (mem, 1);
/* This can happen due to bugs in reload. */
if (GET_CODE (a) == REG && REGNO (a) == SP_REGNUM)
@@ -4165,24 +4170,19 @@ (define_insn "*thumb1_zero_extendhisi2"
ops[0] = operands[0];
ops[1] = a;
- output_asm_insn (\"mov %0, %1\", ops);
+ output_asm_insn ("mov\t%0, %1", ops);
XEXP (mem, 0) = operands[0];
}
-
- else if ( GET_CODE (a) == LABEL_REF
- && GET_CODE (b) == CONST_INT)
- return \"ldr\\t%0, %1\";
}
- return \"ldrh\\t%0, %1\";
- "
+ return "ldrh\t%0, %1";
+}
[(set_attr_alternative "length"
[(if_then_else (eq_attr "is_arch6" "yes")
(const_int 2) (const_int 4))
(const_int 4)])
- (set_attr "type" "alu_shift,load_byte")
- (set_attr "pool_range" "*,60")]
+ (set_attr "type" "alu_shift,load_byte")]
)
(define_insn "*arm_zero_extendhisi2"
@@ -4193,9 +4193,7 @@ (define_insn "*arm_zero_extendhisi2"
#
ldr%(h%)\\t%0, %1"
[(set_attr "type" "alu_shift,load_byte")
- (set_attr "predicable" "yes")
- (set_attr "pool_range" "*,256")
- (set_attr "neg_pool_range" "*,244")]
+ (set_attr "predicable" "yes")]
)
(define_insn "*arm_zero_extendhisi2_v6"
@@ -4206,9 +4204,7 @@ (define_insn "*arm_zero_extendhisi2_v6"
uxth%?\\t%0, %1
ldr%(h%)\\t%0, %1"
[(set_attr "type" "alu_shift,load_byte")
- (set_attr "predicable" "yes")
- (set_attr "pool_range" "*,256")
- (set_attr "neg_pool_range" "*,244")]
+ (set_attr "predicable" "yes")]
)
(define_insn "*arm_zero_extendhisi2addsi"
@@ -4277,9 +4273,8 @@ (define_insn "*thumb1_zero_extendqisi2_v
"@
uxtb\\t%0, %1
ldrb\\t%0, %1"
- [(set_attr "length" "2,2")
- (set_attr "type" "alu_shift,load_byte")
- (set_attr "pool_range" "*,32")]
+ [(set_attr "length" "2")
+ (set_attr "type" "alu_shift,load_byte")]
)
(define_insn "*arm_zero_extendqisi2"
@@ -4291,9 +4286,7 @@ (define_insn "*arm_zero_extendqisi2"
ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "length" "8,4")
(set_attr "type" "alu_shift,load_byte")
- (set_attr "predicable" "yes")
- (set_attr "pool_range" "*,4096")
- (set_attr "neg_pool_range" "*,4084")]
+ (set_attr "predicable" "yes")]
)
(define_insn "*arm_zero_extendqisi2_v6"
@@ -4304,9 +4297,7 @@ (define_insn "*arm_zero_extendqisi2_v6"
uxtb%(%)\\t%0, %1
ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "type" "alu_shift,load_byte")
- (set_attr "predicable" "yes")
- (set_attr "pool_range" "*,4096")
- (set_attr "neg_pool_range" "*,4084")]
+ (set_attr "predicable" "yes")]
)
(define_insn "*arm_zero_extendqisi2addsi"
Index: testsuite/gcc.target/arm/pr43137.c
===================================================================
--- testsuite/gcc.target/arm/pr43137.c (revision 0)
+++ testsuite/gcc.target/arm/pr43137.c (revision 0)
@@ -0,0 +1,9 @@
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "mov\tr1, r\[1-9\]" } } */
+
+int foo();
+long long bar22()
+{
+ int result = foo();
+ return result;
+}
Index: testsuite/ChangeLog
===================================================================
--- testsuite/ChangeLog (revision 163934)
+++ testsuite/ChangeLog (working copy)
@@ -1,3 +1,8 @@
+2010-09-07 Bernd Schmidt <bernds@codesourcery.com>
+
+ PR target/43137
+ * gcc.target/arm/pr43137.c: New test.
+
2010-09-06 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/36931
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ARM: More reorganization of extend patterns (PR43137)
2010-09-06 23:13 ` Bernd Schmidt
@ 2010-09-07 21:29 ` Ramana Radhakrishnan
0 siblings, 0 replies; 10+ messages in thread
From: Ramana Radhakrishnan @ 2010-09-07 21:29 UTC (permalink / raw)
To: Bernd Schmidt; +Cc: Richard Earnshaw, GCC Patches
>> The define_mode_attrs need to be moved to iterators.md. Also, a number
>> of patterns have been changed (inconsistently with the rest of arm.md)
>> to not have the terminating ')' in column 1.
>>
>> Otherwise, OK.
>
> Thanks. Here's what I committed.
This broke bootstrap because of an unused variable "insn" . I've
committed this patch as obvious after making sure trunk builds for
arm-eabi after this patch.
2010-09-07 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm.md: Remove unused variable.
cheers
Ramana
Index: gcc/config/arm/arm.md
===================================================================
--- gcc/config/arm/arm.md (revision 163966)
+++ gcc/config/arm/arm.md (working copy)
@@ -4065,7 +4065,6 @@
"TARGET_32BIT"
[(set (match_dup 0) (match_dup 1))]
{
- rtx insn;
rtx lo_part = gen_lowpart (SImode, operands[0]);
enum machine_mode src_mode = GET_MODE (operands[1]);
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ARM: More reorganization of extend patterns (PR43137)
2010-09-01 16:02 ` Richard Earnshaw
2010-09-06 23:13 ` Bernd Schmidt
@ 2010-09-15 22:47 ` Bernd Schmidt
2010-09-16 12:04 ` Richard Earnshaw
1 sibling, 1 reply; 10+ messages in thread
From: Bernd Schmidt @ 2010-09-15 22:47 UTC (permalink / raw)
To: Richard Earnshaw; +Cc: GCC Patches
[-- Attachment #1: Type: text/plain, Size: 984 bytes --]
On 09/01/2010 05:52 PM, Richard Earnshaw wrote:
> On Tue, 2010-07-13 at 10:56 +0100, Bernd Schmidt wrote:
>> This patch merges a number of different extend:DI patterns by using a
>> QHSI mode_iterator. It also removes separate patterns from thumb2.md
>> as
>> we can just set attr ce_count for ARM patterns as well. I've
>> completed
>> what I'd partially done in my previous patch, which is to remove
>> unnecessary constant pool handling from these patterns - none of them
>> accept constants.
> The define_mode_attrs need to be moved to iterators.md. Also, a number
> of patterns have been changed (inconsistently with the rest of arm.md)
> to not have the terminating ')' in column 1.
>
> Otherwise, OK.
This had one undesirable side effect. The extendsidi patterns now
accept memory arguments, which can make it impossible for the combiner
to generate adddi_[zs]esidi patterns. Fixed with this patch, regression
tested in the same way as the previous one. Ok?
Bernd
[-- Attachment #2: arm-extendfix.diff --]
[-- Type: text/plain, Size: 1765 bytes --]
* config/arm/iterators.md (qhs_extenddi_op): New mode_attr.
* config/arm/arm.md (zero_extend<mode>di2, extend<mode>di2): Use it
for the source operand.
Index: gcc/config/arm/iterators.md
===================================================================
--- gcc/config/arm/iterators.md (revision 163935)
+++ gcc/config/arm/iterators.md (working copy)
@@ -374,6 +374,9 @@ (define_mode_attr V_unpack [(V16QI "V8
(define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
(define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
(QI "&& arm_arch6")])
+(define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
+ (HI "nonimmediate_operand")
+ (QI "nonimmediate_operand")])
;;----------------------------------------------------------------------------
;; Code attributes
Index: gcc/config/arm/arm.md
===================================================================
--- gcc/config/arm/arm.md (revision 163935)
+++ gcc/config/arm/arm.md (working copy)
@@ -4039,7 +4039,7 @@ (define_expand "truncdfhf2"
(define_insn "zero_extend<mode>di2"
[(set (match_operand:DI 0 "s_register_operand" "=r")
- (zero_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))]
+ (zero_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>" "rm")))]
"TARGET_32BIT <qhs_zextenddi_cond>"
"#"
[(set_attr "length" "8")
@@ -4049,7 +4049,7 @@ (define_insn "zero_extend<mode>di2"
(define_insn "extend<mode>di2"
[(set (match_operand:DI 0 "s_register_operand" "=r")
- (sign_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))]
+ (sign_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>" "rm")))]
"TARGET_32BIT <qhs_sextenddi_cond>"
"#"
[(set_attr "length" "8")
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ARM: More reorganization of extend patterns (PR43137)
2010-09-15 22:47 ` Bernd Schmidt
@ 2010-09-16 12:04 ` Richard Earnshaw
2010-09-21 13:59 ` Bernd Schmidt
0 siblings, 1 reply; 10+ messages in thread
From: Richard Earnshaw @ 2010-09-16 12:04 UTC (permalink / raw)
To: Bernd Schmidt; +Cc: GCC Patches
On Thu, 2010-09-16 at 00:31 +0200, Bernd Schmidt wrote:
> On 09/01/2010 05:52 PM, Richard Earnshaw wrote:
> > On Tue, 2010-07-13 at 10:56 +0100, Bernd Schmidt wrote:
> >> This patch merges a number of different extend:DI patterns by using a
> >> QHSI mode_iterator. It also removes separate patterns from thumb2.md
> >> as
> >> we can just set attr ce_count for ARM patterns as well. I've
> >> completed
> >> what I'd partially done in my previous patch, which is to remove
> >> unnecessary constant pool handling from these patterns - none of them
> >> accept constants.
>
> > The define_mode_attrs need to be moved to iterators.md. Also, a number
> > of patterns have been changed (inconsistently with the rest of arm.md)
> > to not have the terminating ')' in column 1.
> >
> > Otherwise, OK.
>
> This had one undesirable side effect. The extendsidi patterns now
> accept memory arguments, which can make it impossible for the combiner
> to generate adddi_[zs]esidi patterns. Fixed with this patch, regression
> tested in the same way as the previous one. Ok?
>
>
> Bernd
So as Uros points out, the constraints also need a macro substitution
(or you'll end up with a potentially invalid insn during reload).
Otherwise, OK.
R.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ARM: More reorganization of extend patterns (PR43137)
2010-09-16 12:04 ` Richard Earnshaw
@ 2010-09-21 13:59 ` Bernd Schmidt
0 siblings, 0 replies; 10+ messages in thread
From: Bernd Schmidt @ 2010-09-21 13:59 UTC (permalink / raw)
To: Richard Earnshaw; +Cc: GCC Patches
[-- Attachment #1: Type: text/plain, Size: 246 bytes --]
On 09/16/2010 12:04 PM, Richard Earnshaw wrote:
> So as Uros points out, the constraints also need a macro substitution
> (or you'll end up with a potentially invalid insn during reload).
>
> Otherwise, OK.
Here's the patch I committed.
Bernd
[-- Attachment #2: arm-extendfix2.diff --]
[-- Type: text/plain, Size: 1709 bytes --]
Index: config/arm/iterators.md
===================================================================
--- config/arm/iterators.md (revision 164476)
+++ config/arm/iterators.md (working copy)
@@ -381,6 +381,10 @@ (define_mode_attr V_unpack [(V16QI "V8
(define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
(define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
(QI "&& arm_arch6")])
+(define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
+ (HI "nonimmediate_operand")
+ (QI "nonimmediate_operand")])
+(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
;;----------------------------------------------------------------------------
;; Code attributes
Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md (revision 164476)
+++ config/arm/arm.md (working copy)
@@ -4042,7 +4042,8 @@ (define_expand "truncdfhf2"
(define_insn "zero_extend<mode>di2"
[(set (match_operand:DI 0 "s_register_operand" "=r")
- (zero_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))]
+ (zero_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
+ "<qhs_extenddi_cstr>")))]
"TARGET_32BIT <qhs_zextenddi_cond>"
"#"
[(set_attr "length" "8")
@@ -4052,7 +4053,8 @@ (define_insn "zero_extend<mode>di2"
(define_insn "extend<mode>di2"
[(set (match_operand:DI 0 "s_register_operand" "=r")
- (sign_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))]
+ (sign_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
+ "<qhs_extenddi_cstr>")))]
"TARGET_32BIT <qhs_sextenddi_cond>"
"#"
[(set_attr "length" "8")
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ARM: More reorganization of extend patterns (PR43137)
@ 2010-09-15 23:01 Uros Bizjak
0 siblings, 0 replies; 10+ messages in thread
From: Uros Bizjak @ 2010-09-15 23:01 UTC (permalink / raw)
To: gcc-patches; +Cc: Bernd Schmidt, Richard Earnshaw
Hello!
> The define_mode_attrs need to be moved to iterators.md. Also, a number
> of patterns have been changed (inconsistently with the rest of arm.md)
> to not have the terminating ')' in column 1.
>
>
> Otherwise, OK.
>
>
> This had one undesirable side effect. The extendsidi patterns now accept memory arguments, which can make it impossible for the combiner to generate adddi_[zs]esidi patterns.
> Fixed with this patch, regression tested in the same way as the previous one. Ok?
You will also need to remove "m" constraint for "s_register_operand"
SImode predicate.
Uros.
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2010-09-21 13:14 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-07-13 9:56 ARM: More reorganization of extend patterns (PR43137) Bernd Schmidt
2010-08-04 14:56 ` Ping: " Bernd Schmidt
2010-08-24 13:09 ` Ping^2: " Bernd Schmidt
2010-09-01 16:02 ` Richard Earnshaw
2010-09-06 23:13 ` Bernd Schmidt
2010-09-07 21:29 ` Ramana Radhakrishnan
2010-09-15 22:47 ` Bernd Schmidt
2010-09-16 12:04 ` Richard Earnshaw
2010-09-21 13:59 ` Bernd Schmidt
2010-09-15 23:01 Uros Bizjak
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