From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 5516 invoked by alias); 9 Dec 2010 16:01:39 -0000 Received: (qmail 5468 invoked by uid 22791); 9 Dec 2010 16:01:38 -0000 X-SWARE-Spam-Status: No, hits=-1.6 required=5.0 tests=AWL,BAYES_00,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 09 Dec 2010 16:01:31 +0000 Received: (qmail 27532 invoked from network); 9 Dec 2010 16:01:29 -0000 Received: from unknown (HELO ?192.168.0.104?) (ams@127.0.0.2) by mail.codesourcery.com with ESMTPA; 9 Dec 2010 16:01:29 -0000 Message-ID: <4D00FD55.8050205@codesourcery.com> Date: Thu, 09 Dec 2010 16:19:00 -0000 From: Andrew Stubbs User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.12) Gecko/20101027 Lightning/1.0b2 Thunderbird/3.1.6 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org Subject: [patch][ARM] Don't generate redundant zero_extend before smlabb Content-Type: multipart/mixed; boundary="------------000309070603090600050508" Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2010-12/txt/msg00775.txt.bz2 This is a multi-part message in MIME format. --------------000309070603090600050508 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-length: 1047 The attached patch adjusts the ARM machine description to prevent GCC emitting redundant zero-extends before 16-bit->32-bit multiply and accumulate operations. The problem is that maddhisi4 pattern has the operands of plus swapped, with respect to the (de facto?) canonical form always returned by combine_simplify_rtx. This means that recog does not match the pattern, and the zero-extends are not optimized away. The patch simply swaps the order of the operands. maddhidi4 appears to have a similar problem, so I've corrected it there also. Test case: int footrunc (int x, int a, int b) { return x + (short) a * (short) b; } Before, compiled with "-O2": mov ip, r1, asl #16 mov r3, r2, asl #16 mov r1, ip, lsr #16 mov r2, r3, lsr #16 smlabb r0, r2, r1, r0 bx lr (On armv7a/thumb2 the code uses uxth, but the problem is the same.) After: smlabb r0, r1, r2, r0 bx lr OK for commit, after stage 1 opens again? Andrew --------------000309070603090600050508 Content-Type: text/x-patch; name="arm-madd-combine.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="arm-madd-combine.patch" Content-length: 1565 2010-12-09 Andrew Stubbs gcc/ * config/arm/arm.md (maddhisi4, *maddhidi4): Use the canonical operand order for plus. --- src/gcc-mainline/gcc/config/arm/arm.md | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/gcc-mainline/gcc/config/arm/arm.md b/src/gcc-mainline/gcc/config/arm/arm.md index 8bc9926..c816126 100644 --- a/src/gcc-mainline/gcc/config/arm/arm.md +++ b/src/gcc-mainline/gcc/config/arm/arm.md @@ -1800,11 +1800,11 @@ (define_insn "maddhisi4" [(set (match_operand:SI 0 "s_register_operand" "=r") - (plus:SI (match_operand:SI 3 "s_register_operand" "r") - (mult:SI (sign_extend:SI + (plus:SI (mult:SI (sign_extend:SI (match_operand:HI 1 "s_register_operand" "%r")) (sign_extend:SI - (match_operand:HI 2 "s_register_operand" "r")))))] + (match_operand:HI 2 "s_register_operand" "r"))) + (match_operand:SI 3 "s_register_operand" "r")))] "TARGET_DSP_MULTIPLY" "smlabb%?\\t%0, %1, %2, %3" [(set_attr "insn" "smlaxy") @@ -1814,11 +1814,11 @@ (define_insn "*maddhidi4" [(set (match_operand:DI 0 "s_register_operand" "=r") (plus:DI - (match_operand:DI 3 "s_register_operand" "0") (mult:DI (sign_extend:DI (match_operand:HI 1 "s_register_operand" "%r")) (sign_extend:DI - (match_operand:HI 2 "s_register_operand" "r")))))] + (match_operand:HI 2 "s_register_operand" "r"))) + (match_operand:DI 3 "s_register_operand" "0")))] "TARGET_DSP_MULTIPLY" "smlalbb%?\\t%Q0, %R0, %1, %2" [(set_attr "insn" "smlalxy") --------------000309070603090600050508--