Ok. After floating-point binary. I will do floating-point ternary.
I think you do conversion next (widen floating point, float to int, int to float).

It seems that we almost done  most of the part autovec patterns in RISC-V port.
What else we can do? My second middle-end patch (LEN_MASK _* load/store) is blocked which is prerequisite for reduction
if you understand how reduction works.
 
Maybe next you could find the way to optimize vv->vx ?

Thanks.


juzhe.zhong@rivai.ai
 
From: Robin Dapp
Date: 2023-06-13 20:00
To: juzhe.zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: [PATCH V3] RISC-V: Add more SLP tests
Hi Juzhe,
 
thanks, works for me as is.  I just hope somebody is going to take on the task
of making different LMUL SLP variants "scannable" at some point because
it would definitely increase our test coverage with these tests. (Or split
the tests manually and not iterate over LMUL)
 
Regards
Robin