* [PATCH][ARM] Tweak arm_class_likely_spilled_p, MODE_BASE_REG_CLASS for Thumb-2
@ 2011-02-14 15:01 Andrew Stubbs
2011-03-30 15:28 ` Richard Earnshaw
0 siblings, 1 reply; 3+ messages in thread
From: Andrew Stubbs @ 2011-02-14 15:01 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 446 bytes --]
This patch is a rework of an old one:
http://gcc.gnu.org/ml/gcc-patches/2010-06/msg01080.html
The ARM parts of that patch were approved, but the target independent
parts were never reviewed (AFAICT), and the patch no longer applies.
I've updated the target-specific parts. As far as I can tell, the target
independent parts are no longer required, so I've dropped them.
Tested with no regressions for ARM mode and Thumb2 mode.
OK?
Andrew
[-- Attachment #2: thumb2_likely_spill.patch --]
[-- Type: text/x-patch, Size: 1870 bytes --]
2011-02-14 Andrew Stubbs <ams@codesourcery.com>
Julian Brown <julian@codesourcery.com>
Mark Shinwell <shinwell@codesourcery.com>
gcc/
* config/arm/arm.h (arm_class_likely_spilled_p): Check against
LO_REGS only for Thumb-1.
(MODE_BASE_REG_CLASS): Restrict base registers to those which can
be used in short instructions when optimising for size on Thumb-2.
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -22304,14 +22304,16 @@ arm_preferred_simd_mode (enum machine_mode mode)
/* Implement TARGET_CLASS_LIKELY_SPILLED_P.
- We need to define this for LO_REGS on thumb. Otherwise we can end up
- using r0-r4 for function arguments, r7 for the stack frame and don't
- have enough left over to do doubleword arithmetic. */
-
+ We need to define this for LO_REGS on Thumb-1. Otherwise we can end up
+ using r0-r4 for function arguments, r7 for the stack frame and don't have
+ enough left over to do doubleword arithmetic. For Thumb-2 all the
+ potentially problematic instructions accept high registers so this is not
+ necessary. Care needs to be taken to avoid adding new Thumb-2 patterns
+ that require many low registers. */
static bool
arm_class_likely_spilled_p (reg_class_t rclass)
{
- if ((TARGET_THUMB && rclass == LO_REGS)
+ if ((TARGET_THUMB1 && rclass == LO_REGS)
|| rclass == CC_REG)
return true;
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1185,7 +1185,7 @@ enum reg_class
when addressing quantities in QI or HI mode; if we don't know the
mode, then we must be conservative. */
#define MODE_BASE_REG_CLASS(MODE) \
- (TARGET_32BIT ? CORE_REGS : \
+ (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \
(((MODE) == SImode) ? BASE_REGS : LO_REGS))
/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH][ARM] Tweak arm_class_likely_spilled_p, MODE_BASE_REG_CLASS for Thumb-2
2011-02-14 15:01 [PATCH][ARM] Tweak arm_class_likely_spilled_p, MODE_BASE_REG_CLASS for Thumb-2 Andrew Stubbs
@ 2011-03-30 15:28 ` Richard Earnshaw
2011-04-06 9:54 ` Andrew Stubbs
0 siblings, 1 reply; 3+ messages in thread
From: Richard Earnshaw @ 2011-03-30 15:28 UTC (permalink / raw)
To: Andrew Stubbs; +Cc: gcc-patches
On Mon, 2011-02-14 at 14:20 +0000, Andrew Stubbs wrote:
> This patch is a rework of an old one:
>
> http://gcc.gnu.org/ml/gcc-patches/2010-06/msg01080.html
>
> The ARM parts of that patch were approved, but the target independent
> parts were never reviewed (AFAICT), and the patch no longer applies.
>
> I've updated the target-specific parts. As far as I can tell, the target
> independent parts are no longer required, so I've dropped them.
>
> Tested with no regressions for ARM mode and Thumb2 mode.
>
> OK?
>
> Andrew
2011-02-14 Andrew Stubbs <ams@codesourcery.com>
Julian Brown <julian@codesourcery.com>
Mark Shinwell <shinwell@codesourcery.com>
gcc/
* config/arm/arm.h (arm_class_likely_spilled_p): Check against
LO_REGS only for Thumb-1.
(MODE_BASE_REG_CLASS): Restrict base registers to those which can
be used in short instructions when optimising for size on Thumb-2.
OK.
R.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH][ARM] Tweak arm_class_likely_spilled_p, MODE_BASE_REG_CLASS for Thumb-2
2011-03-30 15:28 ` Richard Earnshaw
@ 2011-04-06 9:54 ` Andrew Stubbs
0 siblings, 0 replies; 3+ messages in thread
From: Andrew Stubbs @ 2011-04-06 9:54 UTC (permalink / raw)
To: Richard Earnshaw; +Cc: gcc-patches, patches
On 30/03/11 16:13, Richard Earnshaw wrote:
> 2011-02-14 Andrew Stubbs<ams@codesourcery.com>
> Julian Brown<julian@codesourcery.com>
> Mark Shinwell<shinwell@codesourcery.com>
>
> gcc/
> * config/arm/arm.h (arm_class_likely_spilled_p): Check against
> LO_REGS only for Thumb-1.
> (MODE_BASE_REG_CLASS): Restrict base registers to those which can
> be used in short instructions when optimising for size on Thumb-2.
>
> OK.
Committed.
Andrew
^ permalink raw reply [flat|nested] 3+ messages in thread
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2011-02-14 15:01 [PATCH][ARM] Tweak arm_class_likely_spilled_p, MODE_BASE_REG_CLASS for Thumb-2 Andrew Stubbs
2011-03-30 15:28 ` Richard Earnshaw
2011-04-06 9:54 ` Andrew Stubbs
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