From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13390 invoked by alias); 7 Apr 2011 19:41:38 -0000 Received: (qmail 13379 invoked by uid 22791); 7 Apr 2011 19:41:37 -0000 X-SWARE-Spam-Status: No, hits=-6.3 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_HI,SPF_HELO_PASS,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 07 Apr 2011 19:41:30 +0000 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p37JfTtn028946 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Thu, 7 Apr 2011 15:41:29 -0400 Received: from toll.yyz.redhat.com (toll.yyz.redhat.com [10.15.16.165]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id p37JfTu0031091; Thu, 7 Apr 2011 15:41:29 -0400 Message-ID: <4D9E1369.5090205@redhat.com> Date: Thu, 07 Apr 2011 19:41:00 -0000 From: Vladimir Makarov User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.15) Gecko/20110307 Fedora/3.1.9-0.39.b3pre.fc14 Thunderbird/3.1.9 MIME-Version: 1.0 To: gcc-patches CC: Jeffrey Law Subject: patch to fix PR 48435 Content-Type: multipart/mixed; boundary="------------080005010403030203080006" X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-04/txt/msg00573.txt.bz2 This is a multi-part message in MIME format. --------------080005010403030203080006 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-length: 1428 The following patch should solve problem http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48435. It might solve other latest IRA problems too including performance related ones. The patch is for targets which require some values to be placed in hard registers starting with an even (odd) hard registers. I already addressed an analogous problem recently and the patch I sent that time although solved some problems it created even more new problems. I should acknowledge this. The problem was in that profitable hard regs were used for colorability criterion and finding hard registers where allocno values can be resided but *also* as starting allocno hard registers. It resulted in spilling allocnos which should be placed in multi-registers starting on a specific border because profitable hard registers were only starting registers and when we calculated number of available hard registers multi-register allocnos can not fit only in their starting hard registers. The following patch was successfully bootstrapped on x86/x86-64 and on i686 with H.J.'s autotester options. OK to commit? 2011-04-07 Vladimir Makarov PR 4435 * ira-color.c (setup_profitable_hard_regs): Add comments. Don't take prohibited hard regs into account. (setup_conflict_profitable_regs): Rename to get_conflict_profitable_regs. (check_hard_reg_p): Check prohibited hard regs. --------------080005010403030203080006 Content-Type: text/plain; name="p48435.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="p48435.patch" Content-length: 3801 Index: ira-color.c =================================================================== --- ira-color.c (revision 172107) +++ ira-color.c (working copy) @@ -1057,6 +1057,8 @@ setup_profitable_hard_regs (void) enum reg_class aclass; enum machine_mode mode; + /* Initial set up from allocno classes and explicitly conflicting + hard regs. */ EXECUTE_IF_SET_IN_BITMAP (coloring_allocno_bitmap, 0, i, bi) { a = ira_allocnos[i]; @@ -1076,9 +1078,6 @@ setup_profitable_hard_regs (void) { COPY_HARD_REG_SET (obj_data->profitable_hard_regs, reg_class_contents[aclass]); - AND_COMPL_HARD_REG_SET - (obj_data->profitable_hard_regs, - ira_prohibited_class_mode_regs[aclass][mode]); AND_COMPL_HARD_REG_SET (obj_data->profitable_hard_regs, ira_no_alloc_regs); AND_COMPL_HARD_REG_SET (obj_data->profitable_hard_regs, @@ -1086,6 +1085,7 @@ setup_profitable_hard_regs (void) } } } + /* Exclude hard regs already assigned for conflicting objects. */ EXECUTE_IF_SET_IN_BITMAP (consideration_allocno_bitmap, 0, i, bi) { a = ira_allocnos[i]; @@ -1124,6 +1124,7 @@ setup_profitable_hard_regs (void) } } } + /* Exclude too costly hard regs. */ EXECUTE_IF_SET_IN_BITMAP (coloring_allocno_bitmap, 0, i, bi) { int min_cost = INT_MAX; @@ -1451,9 +1452,9 @@ update_conflict_hard_regno_costs (int *c profitable regs exclude hard regs which can not hold value of mode of allocno A. */ static inline void -setup_conflict_profitable_regs (ira_allocno_t a, bool retry_p, - HARD_REG_SET *conflict_regs, - HARD_REG_SET *profitable_regs) +get_conflict_profitable_regs (ira_allocno_t a, bool retry_p, + HARD_REG_SET *conflict_regs, + HARD_REG_SET *profitable_regs) { int i, nwords; ira_object_t obj; @@ -1485,8 +1486,15 @@ check_hard_reg_p (ira_allocno_t a, int h HARD_REG_SET *conflict_regs, HARD_REG_SET *profitable_regs) { int j, nwords, nregs; + enum reg_class aclass; + enum machine_mode mode; - nregs = hard_regno_nregs[hard_regno][ALLOCNO_MODE (a)]; + aclass = ALLOCNO_CLASS (a); + mode = ALLOCNO_MODE (a); + if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[aclass][mode], + hard_regno)) + return false; + nregs = hard_regno_nregs[hard_regno][mode]; nwords = ALLOCNO_NUM_OBJECTS (a); for (j = 0; j < nregs; j++) { @@ -1554,8 +1562,8 @@ assign_hard_reg (ira_allocno_t a, bool r #endif ira_assert (! ALLOCNO_ASSIGNED_P (a)); - setup_conflict_profitable_regs (a, retry_p, - conflicting_regs, profitable_hard_regs); + get_conflict_profitable_regs (a, retry_p, + conflicting_regs, profitable_hard_regs); aclass = ALLOCNO_CLASS (a); class_size = ira_class_hard_regs_num[aclass]; best_hard_regno = -1; @@ -2233,7 +2241,8 @@ setup_allocno_available_regs_num (ira_al ira_object_t obj = ALLOCNO_OBJECT (a, k); object_color_data_t obj_data = OBJECT_COLOR_DATA (obj); - /* Checking only profitable hard regs. */ + /* Checking only profitable hard regs which exclude + object's conflict hard regs. */ if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), hard_regno + j) || ! TEST_HARD_REG_BIT (obj_data->profitable_hard_regs, @@ -2403,8 +2412,8 @@ improve_allocation (void) else base_cost = allocno_costs[ira_class_hard_reg_index[aclass][hregno]]; try_p = false; - setup_conflict_profitable_regs (a, false, - conflicting_regs, profitable_hard_regs); + get_conflict_profitable_regs (a, false, + conflicting_regs, profitable_hard_regs); class_size = ira_class_hard_regs_num[aclass]; /* Set up cost improvement for usage of each profitable hard register for allocno A. */ --------------080005010403030203080006--