Index: config/arm/arm.c =================================================================== --- config/arm/arm.c (revision 176385) +++ config/arm/arm.c (working copy) @@ -3172,6 +3172,19 @@ return code; } + /* If *op0 is (zero_extend:SI (subreg:QI (reg:SI) 0)) and comparing + with const0_rtx, change it to (and:SI (reg:SI) (const_int 255)), + to facilitate possible combining with a cmp into 'ands'. */ + if (mode == SImode + && GET_CODE (*op0) == ZERO_EXTEND + && GET_CODE (XEXP (*op0, 0)) == SUBREG + && GET_MODE (XEXP (*op0, 0)) == QImode + && GET_MODE (SUBREG_REG (XEXP (*op0, 0))) == SImode + && subreg_lowpart_p (XEXP (*op0, 0)) + && *op1 == const0_rtx) + *op0 = gen_rtx_AND (SImode, SUBREG_REG (XEXP (*op0, 0)), + GEN_INT (255)); + /* Comparisons smaller than DImode. Only adjust comparisons against an out-of-range constant. */ if (GET_CODE (*op1) != CONST_INT Index: testsuite/gcc.target/arm/combine-movs.c =================================================================== --- testsuite/gcc.target/arm/combine-movs.c (revision 0) +++ testsuite/gcc.target/arm/combine-movs.c (revision 0) @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +void foo (unsigned long r[], unsigned int d) +{ + int i, n = d / 32; + for (i = 0; i < n; ++i) + r[i] = 0; +} + +/* { dg-final { scan-assembler "movs\tr\[0-9\]" } } */ Index: testsuite/gcc.target/arm/unsigned-extend-2.c =================================================================== --- testsuite/gcc.target/arm/unsigned-extend-2.c (revision 0) +++ testsuite/gcc.target/arm/unsigned-extend-2.c (revision 0) @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O -march=armv6t2" } */ + +unsigned short foo (unsigned short x) +{ + unsigned char i = 0; + for (i = 0; i < 8; i++) + { + x >>= 1; + x &= 0x7fff; + } + return x; +} + +/* { dg-final { scan-assembler "ands" } } */ +/* { dg-final { scan-assembler-not "uxtb" } } */ +/* { dg-final { scan-assembler-not "cmp" } } */