* [patch][i386, AVX] GFNI enabling [3/4]
@ 2017-10-17 13:15 Koval, Julia
2017-10-17 13:15 ` Jakub Jelinek
0 siblings, 1 reply; 5+ messages in thread
From: Koval, Julia @ 2017-10-17 13:15 UTC (permalink / raw)
To: GCC Patches; +Cc: Kirill Yukhin
[-- Attachment #1: Type: text/plain, Size: 1307 bytes --]
Hi, this the third patch of GFNI ISASET enabling. It enables GF2P8AFFINE instruction, described here: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gcc/
* config/i386/gfniintrin.h (_mm_gf2p8affine_epi64_epi8, _mm256_gf2p8affine_epi64_epi8,
(_mm_mask_gf2p8affine_epi64_epi8, _mm_maskz_gf2p8affine_epi64_epi8,
_mm256_mask_gf2p8affine_epi64_epi8, _mm256_maskz_gf2p8affine_epi64_epi8,
_mm512_mask_gf2p8affine_epi64_epi8, _mm512_maskz_gf2p8affine_epi64_epi8,
_mm512_gf2p8affine_epi64_epi8): New intrinsics.
* config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineqb_v64qi,
__builtin_ia32_vgf2p8affineqb_v32qi, __builtin_ia32_vgf2p8affineqb_v16qi): New builtins.
* config/i386/sse.md (vgf2p8affineqb_*): New pattern.
gcc/testsuite/
* gcc.target/i386/avx-1.c: Handle new intrinsics.
* gcc.target/i386/avx512f-gf2p8affineqb-2.c: New runtime tests.
* gcc.target/i386/avx512vl-gf2p8affineqb-2.c: Ditto.
* gcc.target/i386/gfni-1.c: Add tests for GF2P8AFFINE.
* gcc.target/i386/gfni-2.c: Ditto.
* gcc.target/i386/gfni-3.c: Ditto.
* gcc.target/i386/gfni-4.c: Ditto.
* gcc.target/i386/sse-13.c: Handle new tests.
* gcc.target/i386/sse-23.c: Handle new tests.
Ok for trunk?
Thanks,
Julia
[-- Attachment #2: 0003-GF2P8AFFINE-instruction.patch --]
[-- Type: application/octet-stream, Size: 25628 bytes --]
From ddc86c68a318493c45068a809162e9e275fe0075 Mon Sep 17 00:00:00 2001
From: "julia.koval" <jkoval@gkticlel801.igk.intel.com>
Date: Mon, 20 Feb 2017 14:25:53 +0300
Subject: [PATCH 3/4] GF2P8AFFINE instruction
---
gcc/config/i386/gfniintrin.h | 110 +++++++++++++++++++++
gcc/config/i386/i386-builtin.def | 6 ++
gcc/config/i386/sse.md | 18 ++++
gcc/testsuite/gcc.target/i386/avx-1.c | 6 ++
.../gcc.target/i386/avx512f-gf2p8affineqb-2.c | 74 ++++++++++++++
.../gcc.target/i386/avx512vl-gf2p8affineqb-2.c | 17 ++++
gcc/testsuite/gcc.target/i386/gfni-1.c | 6 ++
gcc/testsuite/gcc.target/i386/gfni-2.c | 12 +++
gcc/testsuite/gcc.target/i386/gfni-3.c | 4 +
gcc/testsuite/gcc.target/i386/gfni-4.c | 2 +
gcc/testsuite/gcc.target/i386/sse-13.c | 7 ++
gcc/testsuite/gcc.target/i386/sse-23.c | 7 ++
12 files changed, 269 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-gf2p8affineqb-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-gf2p8affineqb-2.c
diff --git a/gcc/config/i386/gfniintrin.h b/gcc/config/i386/gfniintrin.h
index a42c205..9ddd2e0 100644
--- a/gcc/config/i386/gfniintrin.h
+++ b/gcc/config/i386/gfniintrin.h
@@ -43,10 +43,21 @@ _mm_gf2p8affineinv_epi64_epi8 (__m128i __A, __m128i __B, const int __C)
(__v16qi) __B,
__C);
}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_gf2p8affine_epi64_epi8 (__m128i __A, __m128i __B, const int __C)
+{
+ return (__m128i) __builtin_ia32_vgf2p8affineqb_v16qi ((__v16qi) __A,
+ (__v16qi) __B, __C);
+}
#else
#define _mm_gf2p8affineinv_epi64_epi8(A, B, C) \
((__m128i) __builtin_ia32_vgf2p8affineinvqb_v16qi((__v16qi)(__m128i)(A), \
(__v16qi)(__m128i)(B), (int)(C)))
+#define _mm_gf2p8affine_epi64_epi8(A, B, C) \
+ ((__m128i) __builtin_ia32_vgf2p8affineqb_v16qi ((__v16qi)(__m128i)(A), \
+ (__v16qi)(__m128i)(B), (int)(C)))
#endif
#ifdef __DISABLE_GFNI__
@@ -69,11 +80,22 @@ _mm256_gf2p8affineinv_epi64_epi8 (__m256i __A, __m256i __B, const int __C)
(__v32qi) __B,
__C);
}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_gf2p8affine_epi64_epi8 (__m256i __A, __m256i __B, const int __C)
+{
+ return (__m256i) __builtin_ia32_vgf2p8affineqb_v32qi ((__v32qi) __A,
+ (__v32qi) __B, __C);
+}
#else
#define _mm256_gf2p8affineinv_epi64_epi8(A, B, C) \
((__m256i) __builtin_ia32_vgf2p8affineinvqb_v32qi((__v32qi)(__m256i)(A), \
(__v32qi)(__m256i)(B), \
(int)(C)))
+#define _mm256_gf2p8affine_epi64_epi8(A, B, C) \
+ ((__m256i) __builtin_ia32_vgf2p8affineqb_v32qi ((__v32qi)(__m256i)(A), \
+ ( __v32qi)(__m256i)(B), (int)(C)))
#endif
#ifdef __DISABLE_GFNIAVX__
@@ -110,6 +132,24 @@ _mm_maskz_gf2p8affineinv_epi64_epi8 (__mmask16 __A, __m128i __B, __m128i __C,
(__v16qi) _mm_setzero_si128 (),
__A);
}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_gf2p8affine_epi64_epi8 (__m128i __A, __mmask16 __B, __m128i __C,
+ __m128i __D, const int __E)
+{
+ return (__m128i) __builtin_ia32_vgf2p8affineqb_v16qi_mask ((__v16qi) __C,
+ (__v16qi) __D, __E, (__v16qi)__A, __B);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_gf2p8affine_epi64_epi8 (__mmask16 __A, __m128i __B, __m128i __C,
+ const int __D)
+{
+ return (__m128i) __builtin_ia32_vgf2p8affineqb_v16qi_mask ((__v16qi) __B,
+ (__v16qi) __C, __D, (__v16qi) _mm_setzero_si128 (), __A);
+}
#else
#define _mm_mask_gf2p8affineinv_epi64_epi8(A, B, C, D, E) \
((__m128i) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask( \
@@ -120,6 +160,13 @@ _mm_maskz_gf2p8affineinv_epi64_epi8 (__mmask16 __A, __m128i __B, __m128i __C,
(__v16qi)(__m128i)(B), (__v16qi)(__m128i)(C), \
(int)(D), (__v16qi)(__m128i) _mm_setzero_si128 (), \
(__mmask16)(A)))
+#define _mm_mask_gf2p8affine_epi64_epi8(A, B, C, D, E) \
+ ((__m128i) __builtin_ia32_vgf2p8affineqb_v16qi_mask((__v16qi)(__m128i)(C),\
+ (__v16qi)(__m128i)(D), (int)(E), (__v16qi)(__m128i)(A), (__mmask16)(B)))
+#define _mm_maskz_gf2p8affine_epi64_epi8(A, B, C, D) \
+ ((__m128i) __builtin_ia32_vgf2p8affineqb_v16qi_mask((__v16qi)(__m128i)(B),\
+ (__v16qi)(__m128i)(C), (int)(D), \
+ (__v16qi)(__m128i) _mm_setzero_si128 (), (__mmask16)(A)))
#endif
#ifdef __DISABLE_GFNIAVX512VL__
@@ -155,6 +202,27 @@ _mm256_maskz_gf2p8affineinv_epi64_epi8 (__mmask32 __A, __m256i __B,
(__v32qi) __C, __D,
(__v32qi) _mm256_setzero_si256 (), __A);
}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_gf2p8affine_epi64_epi8 (__m256i __A, __mmask32 __B, __m256i __C,
+ __m256i __D, const int __E)
+{
+ return (__m256i) __builtin_ia32_vgf2p8affineqb_v32qi_mask ((__v32qi) __C,
+ (__v32qi) __D,
+ __E,
+ (__v32qi)__A,
+ __B);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_gf2p8affine_epi64_epi8 (__mmask32 __A, __m256i __B,
+ __m256i __C, const int __D)
+{
+ return (__m256i) __builtin_ia32_vgf2p8affineqb_v32qi_mask ((__v32qi) __B,
+ (__v32qi) __C, __D, (__v32qi)_mm256_setzero_si256 (), __A);
+}
#else
#define _mm256_mask_gf2p8affineinv_epi64_epi8(A, B, C, D, E) \
((__m256i) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask( \
@@ -164,6 +232,13 @@ _mm256_maskz_gf2p8affineinv_epi64_epi8 (__mmask32 __A, __m256i __B,
((__m256i) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask( \
(__v32qi)(__m256i)(B), (__v32qi)(__m256i)(C), (int)(D), \
(__v32qi)(__m256i) _mm256_setzero_si256 (), (__mmask32)(A)))
+#define _mm256_mask_gf2p8affine_epi64_epi8(A, B, C, D, E) \
+ ((__m256i) __builtin_ia32_vgf2p8affineqb_v32qi_mask((__v32qi)(__m256i)(C),\
+ (__v32qi)(__m256i)(D), (int)(E), (__v32qi)(__m256i)(A), (__mmask32)(B)))
+#define _mm256_maskz_gf2p8affine_epi64_epi8(A, B, C, D) \
+ ((__m256i) __builtin_ia32_vgf2p8affineqb_v32qi_mask((__v32qi)(__m256i)(B),\
+ (__v32qi)(__m256i)(C), (int)(D), \
+ (__v32qi)(__m256i) _mm256_setzero_si256 (), (__mmask32)(A)))
#endif
#ifdef __DISABLE_GFNIAVX512VLBW__
@@ -207,6 +282,31 @@ _mm512_gf2p8affineinv_epi64_epi8 (__m512i __A, __m512i __B, const int __C)
return (__m512i) __builtin_ia32_vgf2p8affineinvqb_v64qi ((__v64qi) __A,
(__v64qi) __B, __C);
}
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_gf2p8affine_epi64_epi8 (__m512i __A, __mmask64 __B, __m512i __C,
+ __m512i __D, const int __E)
+{
+ return (__m512i) __builtin_ia32_vgf2p8affineqb_v64qi_mask ((__v64qi) __C,
+ (__v64qi) __D, __E, (__v64qi)__A, __B);
+}
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_gf2p8affine_epi64_epi8 (__mmask64 __A, __m512i __B, __m512i __C,
+ const int __D)
+{
+ return (__m512i) __builtin_ia32_vgf2p8affineqb_v64qi_mask ((__v64qi) __B,
+ (__v64qi) __C, __D, (__v64qi) _mm512_setzero_si512 (), __A);
+}
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_gf2p8affine_epi64_epi8 (__m512i __A, __m512i __B, const int __C)
+{
+ return (__m512i) __builtin_ia32_vgf2p8affineqb_v64qi ((__v64qi) __A,
+ (__v64qi) __B, __C);
+}
#else
#define _mm512_mask_gf2p8affineinv_epi64_epi8(A, B, C, D, E) \
((__m512i) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask( \
@@ -219,6 +319,16 @@ _mm512_gf2p8affineinv_epi64_epi8 (__m512i __A, __m512i __B, const int __C)
#define _mm512_gf2p8affineinv_epi64_epi8(A, B, C) \
((__m512i) __builtin_ia32_vgf2p8affineinvqb_v64qi ( \
(__v64qi)(__m512i)(A), (__v64qi)(__m512i)(B), (int)(C)))
+#define _mm512_mask_gf2p8affine_epi64_epi8(A, B, C, D, E) \
+ ((__m512i) __builtin_ia32_vgf2p8affineqb_v64qi_mask((__v64qi)(__m512i)(C),\
+ (__v64qi)(__m512i)(D), (int)(E), (__v64qi)(__m512i)(A), (__mmask64)(B)))
+#define _mm512_maskz_gf2p8affine_epi64_epi8(A, B, C, D) \
+ ((__m512i) __builtin_ia32_vgf2p8affineqb_v64qi_mask((__v64qi)(__m512i)(B),\
+ (__v64qi)(__m512i)(C), (int)(D), \
+ (__v64qi)(__m512i) _mm512_setzero_si512 (), (__mmask64)(A)))
+#define _mm512_gf2p8affine_epi64_epi8(A, B, C) \
+ ((__m512i) __builtin_ia32_vgf2p8affineqb_v64qi ((__v64qi)(__m512i)(A), \
+ (__v64qi)(__m512i)(B), (int)(C)))
#endif
#ifdef __DISABLE_GFNIAVX512FBW__
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 24d057d..eee9d64 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -2596,6 +2596,12 @@ BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v32qi, "__builtin_ia32_v
BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v32qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI)
BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v16qi, "__builtin_ia32_vgf2p8affineinvqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEINVQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT)
BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v16qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI)
+BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineqb_v64qi, "__builtin_ia32_vgf2p8affineqb_v64qi", IX86_BUILTIN_VGF2P8AFFINEQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineqb_v64qi_mask, "__builtin_ia32_vgf2p8affineqb_v64qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB512MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT_V64QI_UDI)
+BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineqb_v32qi, "__builtin_ia32_vgf2p8affineqb_v32qi", IX86_BUILTIN_VGF2P8AFFINEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineqb_v32qi_mask, "__builtin_ia32_vgf2p8affineqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI)
+BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineqb_v16qi, "__builtin_ia32_vgf2p8affineqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineqb_v16qi_mask, "__builtin_ia32_vgf2p8affineqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI)
BDESC_END (ARGS2, MPX)
/* Builtins for MPX. */
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 3199f19..fe583ed 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -160,6 +160,7 @@
;; For GFNI support
UNSPEC_GF2P8AFFINEINV
+ UNSPEC_GF2P8AFFINE
])
(define_c_enum "unspecv" [
@@ -20188,3 +20189,20 @@
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
(set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "vgf2p8affineqb_<mode><mask_name>"
+ [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
+ (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
+ (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
+ (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
+ UNSPEC_GF2P8AFFINE))]
+ "TARGET_GFNI"
+ "@
+ gf2p8affineqb\t{%3, %2, %0| %0, %2, %3}
+ vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}
+ vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
+ [(set_attr "isa" "noavx,avx,avx512bw")
+ (set_attr "prefix_data16" "1,*,*")
+ (set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,maybe_evex,evex")
+ (set_attr "mode" "<sseinsnmode>")])
diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c
index 67dea5b..1d68317 100644
--- a/gcc/testsuite/gcc.target/i386/avx-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx-1.c
@@ -610,6 +610,12 @@
#define __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, 1, D, E)
#define __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, 1, D, E)
#define __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v16qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v16qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v32qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v32qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v64qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v64qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v16qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v32qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v64qi_mask(A, B, 1, D, E)
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-gf2p8affineqb-2.c b/gcc/testsuite/gcc.target/i386/avx512f-gf2p8affineqb-2.c
new file mode 100644
index 0000000..807da2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-gf2p8affineqb-2.c
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -mgfni -mavx512bw" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target gfni } */
+
+#define AVX512F
+
+#define GFNI
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 8)
+
+#include "avx512f-mask-type.h"
+#include <x86intrin.h>
+
+static void
+CALC (unsigned char *r, unsigned char *s1, unsigned char *s2, unsigned char imm)
+{
+ for (int a = 0; a < SIZE/8; a++)
+ {
+ for (int val = 0; val < 8; val++)
+ {
+ unsigned char result = 0;
+ for (int bit = 0; bit < 8; bit++)
+ {
+ unsigned char temp = s1[a*8 + val] & s2[a*8 + bit];
+ unsigned char parity = __popcntd(temp);
+ if (parity % 2)
+ result |= (1 << (8 - bit - 1));
+ }
+ r[a*8 + val] = result ^ imm;
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i;
+ UNION_TYPE (AVX512F_LEN, i_b) res1, res2, res3, src1, src2;
+ MASK_TYPE mask = MASK_VALUE;
+ char res_ref[SIZE];
+ unsigned char imm = 0;
+
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = 1 + i;
+ src2.a[i] = 1;
+ }
+
+ for (i = 0; i < SIZE; i++)
+ {
+ res1.a[i] = DEFAULT_VALUE;
+ res2.a[i] = DEFAULT_VALUE;
+ res3.a[i] = DEFAULT_VALUE;
+ }
+
+ CALC (res_ref, src1.a, src2.a, imm);
+
+ res1.x = INTRINSIC (_gf2p8affine_epi64_epi8) (src1.x, src2.x, imm);
+ res2.x = INTRINSIC (_mask_gf2p8affine_epi64_epi8) (res2.x, mask, src1.x, src2.x, imm);
+ res3.x = INTRINSIC (_maskz_gf2p8affine_epi64_epi8) (mask, src1.x, src2.x, imm);
+ if (UNION_CHECK (AVX512F_LEN, i_b) (res1, res_ref))
+ abort ();
+
+ MASK_MERGE (i_b) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_b) (res2, res_ref))
+ abort ();
+
+ MASK_ZERO (i_b) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_b) (res3, res_ref))
+ abort ();
+
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-gf2p8affineqb-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-gf2p8affineqb-2.c
new file mode 100644
index 0000000..1b650d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-gf2p8affineqb-2.c
@@ -0,0 +1,17 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512bw -mavx512vl -mgfni" } */
+/* { dg-require-effective-target avx512vl } */
+/* { dg-require-effective-target avx512bw } */
+/* { dg-require-effective-target gfni } */
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512f-gf2p8affineqb-2.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512f-gf2p8affineqb-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/gfni-1.c b/gcc/testsuite/gcc.target/i386/gfni-1.c
index 5e22c9e..71e6db2 100644
--- a/gcc/testsuite/gcc.target/i386/gfni-1.c
+++ b/gcc/testsuite/gcc.target/i386/gfni-1.c
@@ -3,6 +3,9 @@
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
#include <x86intrin.h>
@@ -15,4 +18,7 @@ avx512vl_test (void)
x1 = _mm512_gf2p8affineinv_epi64_epi8(x1, x2, 3);
x1 = _mm512_mask_gf2p8affineinv_epi64_epi8(x1, m64, x2, x1, 3);
x1 = _mm512_maskz_gf2p8affineinv_epi64_epi8(m64, x1, x2, 3);
+ x1 = _mm512_gf2p8affine_epi64_epi8(x1, x2, 3);
+ x1 = _mm512_mask_gf2p8affine_epi64_epi8(x1, m64, x2, x1, 3);
+ x1 = _mm512_maskz_gf2p8affine_epi64_epi8(m64, x1, x2, 3);
}
diff --git a/gcc/testsuite/gcc.target/i386/gfni-2.c b/gcc/testsuite/gcc.target/i386/gfni-2.c
index 4d1f151..14764b5 100644
--- a/gcc/testsuite/gcc.target/i386/gfni-2.c
+++ b/gcc/testsuite/gcc.target/i386/gfni-2.c
@@ -6,6 +6,12 @@
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
#include <x86intrin.h>
@@ -24,4 +30,10 @@ avx512vl_test (void)
x5 = _mm_gf2p8affineinv_epi64_epi8(x5, x6, 3);
x5 = _mm_mask_gf2p8affineinv_epi64_epi8(x5, m16, x6, x5, 3);
x5 = _mm_maskz_gf2p8affineinv_epi64_epi8(m16, x5, x6, 3);
+ x3 = _mm256_gf2p8affine_epi64_epi8(x3, x4, 3);
+ x3 = _mm256_mask_gf2p8affine_epi64_epi8(x3, m32, x4, x3, 3);
+ x3 = _mm256_maskz_gf2p8affine_epi64_epi8(m32, x3, x4, 3);
+ x5 = _mm_gf2p8affine_epi64_epi8(x5, x6, 3);
+ x5 = _mm_mask_gf2p8affine_epi64_epi8(x5, m16, x6, x5, 3);
+ x5 = _mm_maskz_gf2p8affine_epi64_epi8(m16, x5, x6, 3);
}
diff --git a/gcc/testsuite/gcc.target/i386/gfni-3.c b/gcc/testsuite/gcc.target/i386/gfni-3.c
index de5f80b..3e39f4e 100644
--- a/gcc/testsuite/gcc.target/i386/gfni-3.c
+++ b/gcc/testsuite/gcc.target/i386/gfni-3.c
@@ -2,6 +2,8 @@
/* { dg-options "-mgfni -mavx -O2" } */
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
#include <x86intrin.h>
@@ -14,4 +16,6 @@ avx512vl_test (void)
{
x3 = _mm256_gf2p8affineinv_epi64_epi8(x3, x4, 3);
x5 = _mm_gf2p8affineinv_epi64_epi8(x5, x6, 3);
+ x3 = _mm256_gf2p8affine_epi64_epi8(x3, x4, 3);
+ x5 = _mm_gf2p8affine_epi64_epi8(x5, x6, 3);
}
diff --git a/gcc/testsuite/gcc.target/i386/gfni-4.c b/gcc/testsuite/gcc.target/i386/gfni-4.c
index 1532716..6103547 100644
--- a/gcc/testsuite/gcc.target/i386/gfni-4.c
+++ b/gcc/testsuite/gcc.target/i386/gfni-4.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-mgfni -O2" } */
/* { dg-final { scan-assembler-times "gf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "gf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
#include <x86intrin.h>
@@ -11,4 +12,5 @@ void extern
avx512vl_test (void)
{
x5 = _mm_gf2p8affineinv_epi64_epi8(x5, x6, 3);
+ x5 = _mm_gf2p8affine_epi64_epi8(x5, x6, 3);
}
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c
index 3378c5d..da04e54 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -627,5 +627,12 @@
#define __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, 1, D, E)
#define __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, 1, D, E)
#define __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v16qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v16qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v32qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v32qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v64qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v64qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v16qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v32qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v64qi_mask(A, B, 1, D, E)
+
#include <x86intrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c
index d2a301c..cb5119f 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -626,6 +626,13 @@
#define __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, 1, D, E)
#define __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, 1, D, E)
#define __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v16qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v16qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v32qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v32qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v64qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v64qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v16qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v32qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v64qi_mask(A, B, 1, D, E)
+
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid")
--
1.8.3.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [patch][i386, AVX] GFNI enabling [3/4]
2017-10-17 13:15 [patch][i386, AVX] GFNI enabling [3/4] Koval, Julia
@ 2017-10-17 13:15 ` Jakub Jelinek
2017-10-17 13:26 ` Koval, Julia
0 siblings, 1 reply; 5+ messages in thread
From: Jakub Jelinek @ 2017-10-17 13:15 UTC (permalink / raw)
To: Koval, Julia; +Cc: GCC Patches, Kirill Yukhin
On Tue, Oct 17, 2017 at 01:09:50PM +0000, Koval, Julia wrote:
> Hi, this the third patch of GFNI ISASET enabling. It enables GF2P8AFFINE instruction, described here: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
>
> gcc/
> * config/i386/gfniintrin.h (_mm_gf2p8affine_epi64_epi8, _mm256_gf2p8affine_epi64_epi8,
Too long line, even ChangeLog entries should be wrapped to 80 columns.
> (_mm_mask_gf2p8affine_epi64_epi8, _mm_maskz_gf2p8affine_epi64_epi8,
> _mm256_mask_gf2p8affine_epi64_epi8, _mm256_maskz_gf2p8affine_epi64_epi8,
> _mm512_mask_gf2p8affine_epi64_epi8, _mm512_maskz_gf2p8affine_epi64_epi8,
The above two are also too long (off by 1 char).
> _mm512_gf2p8affine_epi64_epi8): New intrinsics.
> * config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineqb_v64qi,
> __builtin_ia32_vgf2p8affineqb_v32qi, __builtin_ia32_vgf2p8affineqb_v16qi): New builtins.
And this one too. Please wrap them.
> * config/i386/sse.md (vgf2p8affineqb_*): New pattern.
Use vgf2p8affineqb_<mode><mask_name> instead of the wild-card?
I'll defer actual review to Kirill.
Jakub
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [patch][i386, AVX] GFNI enabling [3/4]
2017-10-17 13:15 ` Jakub Jelinek
@ 2017-10-17 13:26 ` Koval, Julia
2017-11-06 8:26 ` Koval, Julia
0 siblings, 1 reply; 5+ messages in thread
From: Koval, Julia @ 2017-10-17 13:26 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: GCC Patches, Kirill Yukhin
Thanks for your comments, fixed everything.
gcc/
* config/i386/gfniintrin.h (_mm_gf2p8affine_epi64_epi8,
_mm256_gf2p8affine_epi64_epi8, _mm_mask_gf2p8affine_epi64_epi8,
_mm_maskz_gf2p8affine_epi64_epi8, _mm256_mask_gf2p8affine_epi64_epi8,
_mm256_maskz_gf2p8affine_epi64_epi8,
_mm512_mask_gf2p8affine_epi64_epi8, _mm512_gf2p8affine_epi64_epi8
_mm512_maskz_gf2p8affine_epi64_epi8): New intrinsics.
* config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineqb_v64qi,
__builtin_ia32_vgf2p8affineqb_v32qi,
__builtin_ia32_vgf2p8affineqb_v16qi): New builtins.
* config/i386/sse.md (vgf2p8affineqb_<mode><mask_name>): New pattern.
gcc/testsuite/
* gcc.target/i386/avx-1.c: Handle new intrinsics.
* gcc.target/i386/avx512f-gf2p8affineqb-2.c: New runtime tests.
* gcc.target/i386/avx512vl-gf2p8affineqb-2.c: Ditto.
* gcc.target/i386/gfni-1.c: Add tests for GF2P8AFFINE.
* gcc.target/i386/gfni-2.c: Ditto.
* gcc.target/i386/gfni-3.c: Ditto.
* gcc.target/i386/gfni-4.c: Ditto.
* gcc.target/i386/sse-13.c: Handle new tests.
* gcc.target/i386/sse-23.c: Handle new tests.
> -----Original Message-----
> From: Jakub Jelinek [mailto:jakub@redhat.com]
> Sent: Tuesday, October 17, 2017 3:15 PM
> To: Koval, Julia <julia.koval@intel.com>
> Cc: GCC Patches <gcc-patches@gcc.gnu.org>; Kirill Yukhin
> <kirill.yukhin@gmail.com>
> Subject: Re: [patch][i386, AVX] GFNI enabling [3/4]
>
> On Tue, Oct 17, 2017 at 01:09:50PM +0000, Koval, Julia wrote:
> > Hi, this the third patch of GFNI ISASET enabling. It enables GF2P8AFFINE
> instruction, described here:
> https://software.intel.com/sites/default/files/managed/c5/15/architecture-
> instruction-set-extensions-programming-reference.pdf
> >
> > gcc/
> > * config/i386/gfniintrin.h (_mm_gf2p8affine_epi64_epi8,
> _mm256_gf2p8affine_epi64_epi8,
>
> Too long line, even ChangeLog entries should be wrapped to 80 columns.
>
> > (_mm_mask_gf2p8affine_epi64_epi8,
> _mm_maskz_gf2p8affine_epi64_epi8,
> > _mm256_mask_gf2p8affine_epi64_epi8,
> _mm256_maskz_gf2p8affine_epi64_epi8,
> > _mm512_mask_gf2p8affine_epi64_epi8,
> _mm512_maskz_gf2p8affine_epi64_epi8,
>
> The above two are also too long (off by 1 char).
>
> > _mm512_gf2p8affine_epi64_epi8): New intrinsics.
> > * config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineqb_v64qi,
> > __builtin_ia32_vgf2p8affineqb_v32qi,
> __builtin_ia32_vgf2p8affineqb_v16qi): New builtins.
>
> And this one too. Please wrap them.
>
> > * config/i386/sse.md (vgf2p8affineqb_*): New pattern.
>
> Use vgf2p8affineqb_<mode><mask_name> instead of the wild-card?
>
> I'll defer actual review to Kirill.
>
> Jakub
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [patch][i386, AVX] GFNI enabling [3/4]
2017-10-17 13:26 ` Koval, Julia
@ 2017-11-06 8:26 ` Koval, Julia
2017-11-10 20:41 ` Kirill Yukhin
0 siblings, 1 reply; 5+ messages in thread
From: Koval, Julia @ 2017-11-06 8:26 UTC (permalink / raw)
To: Koval, Julia
Cc: 'GCC Patches', 'Kirill Yukhin', 'Jakub Jelinek'
[-- Attachment #1: Type: text/plain, Size: 4398 bytes --]
Rebased after last patch fixes.
gcc/
* config/i386/gfniintrin.h (_mm_gf2p8affine_epi64_epi8,
_mm256_gf2p8affine_epi64_epi8, _mm_mask_gf2p8affine_epi64_epi8,
_mm_maskz_gf2p8affine_epi64_epi8, _mm256_mask_gf2p8affine_epi64_epi8,
_mm256_maskz_gf2p8affine_epi64_epi8,
_mm512_mask_gf2p8affine_epi64_epi8, _mm512_gf2p8affine_epi64_epi8
_mm512_maskz_gf2p8affine_epi64_epi8): New intrinsics.
* config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineqb_v64qi,
__builtin_ia32_vgf2p8affineqb_v32qi,
__builtin_ia32_vgf2p8affineqb_v16qi): New builtins.
* config/i386/sse.md (vgf2p8affineqb_<mode><mask_name>): New pattern.
gcc/testsuite/
* gcc.target/i386/avx-1.c: Handle new intrinsics.
* gcc.target/i386/avx512f-gf2p8affineqb-2.c: New runtime tests.
* gcc.target/i386/avx512vl-gf2p8affineqb-2.c: Ditto.
* gcc.target/i386/gfni-1.c: Add tests for GF2P8AFFINE.
* gcc.target/i386/gfni-2.c: Ditto.
* gcc.target/i386/gfni-3.c: Ditto.
* gcc.target/i386/gfni-4.c: Ditto.
* gcc.target/i386/sse-13.c: Handle new tests.
* gcc.target/i386/sse-14.c: Handle new tests.
* gcc.target/i386/sse-23.c: Handle new tests.
> -----Original Message-----
> From: Koval, Julia
> Sent: Tuesday, October 17, 2017 3:26 PM
> To: Jakub Jelinek <jakub@redhat.com>
> Cc: GCC Patches <gcc-patches@gcc.gnu.org>; Kirill Yukhin
> <kirill.yukhin@gmail.com>
> Subject: RE: [patch][i386, AVX] GFNI enabling [3/4]
>
> Thanks for your comments, fixed everything.
>
> gcc/
> * config/i386/gfniintrin.h (_mm_gf2p8affine_epi64_epi8,
> _mm256_gf2p8affine_epi64_epi8, _mm_mask_gf2p8affine_epi64_epi8,
> _mm_maskz_gf2p8affine_epi64_epi8,
> _mm256_mask_gf2p8affine_epi64_epi8,
> _mm256_maskz_gf2p8affine_epi64_epi8,
> _mm512_mask_gf2p8affine_epi64_epi8, _mm512_gf2p8affine_epi64_epi8
> _mm512_maskz_gf2p8affine_epi64_epi8): New intrinsics.
> * config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineqb_v64qi,
> __builtin_ia32_vgf2p8affineqb_v32qi,
> __builtin_ia32_vgf2p8affineqb_v16qi): New builtins.
> * config/i386/sse.md (vgf2p8affineqb_<mode><mask_name>): New
> pattern.
>
> gcc/testsuite/
> * gcc.target/i386/avx-1.c: Handle new intrinsics.
> * gcc.target/i386/avx512f-gf2p8affineqb-2.c: New runtime tests.
> * gcc.target/i386/avx512vl-gf2p8affineqb-2.c: Ditto.
> * gcc.target/i386/gfni-1.c: Add tests for GF2P8AFFINE.
> * gcc.target/i386/gfni-2.c: Ditto.
> * gcc.target/i386/gfni-3.c: Ditto.
> * gcc.target/i386/gfni-4.c: Ditto.
> * gcc.target/i386/sse-13.c: Handle new tests.
> * gcc.target/i386/sse-23.c: Handle new tests.
>
>
> > -----Original Message-----
> > From: Jakub Jelinek [mailto:jakub@redhat.com]
> > Sent: Tuesday, October 17, 2017 3:15 PM
> > To: Koval, Julia <julia.koval@intel.com>
> > Cc: GCC Patches <gcc-patches@gcc.gnu.org>; Kirill Yukhin
> > <kirill.yukhin@gmail.com>
> > Subject: Re: [patch][i386, AVX] GFNI enabling [3/4]
> >
> > On Tue, Oct 17, 2017 at 01:09:50PM +0000, Koval, Julia wrote:
> > > Hi, this the third patch of GFNI ISASET enabling. It enables GF2P8AFFINE
> > instruction, described here:
> > https://software.intel.com/sites/default/files/managed/c5/15/architecture-
> > instruction-set-extensions-programming-reference.pdf
> > >
> > > gcc/
> > > * config/i386/gfniintrin.h (_mm_gf2p8affine_epi64_epi8,
> > _mm256_gf2p8affine_epi64_epi8,
> >
> > Too long line, even ChangeLog entries should be wrapped to 80 columns.
> >
> > > (_mm_mask_gf2p8affine_epi64_epi8,
> > _mm_maskz_gf2p8affine_epi64_epi8,
> > > _mm256_mask_gf2p8affine_epi64_epi8,
> > _mm256_maskz_gf2p8affine_epi64_epi8,
> > > _mm512_mask_gf2p8affine_epi64_epi8,
> > _mm512_maskz_gf2p8affine_epi64_epi8,
> >
> > The above two are also too long (off by 1 char).
> >
> > > _mm512_gf2p8affine_epi64_epi8): New intrinsics.
> > > * config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineqb_v64qi,
> > > __builtin_ia32_vgf2p8affineqb_v32qi,
> > __builtin_ia32_vgf2p8affineqb_v16qi): New builtins.
> >
> > And this one too. Please wrap them.
> >
> > > * config/i386/sse.md (vgf2p8affineqb_*): New pattern.
> >
> > Use vgf2p8affineqb_<mode><mask_name> instead of the wild-card?
> >
> > I'll defer actual review to Kirill.
> >
> > Jakub
[-- Attachment #2: 0001-gf2p8affine.patch --]
[-- Type: application/octet-stream, Size: 26573 bytes --]
From 488f6c3a0499070caec9572720f1d708549487d5 Mon Sep 17 00:00:00 2001
From: julia <jkoval@gkticlel801.igk.intel.com>
Date: Mon, 6 Nov 2017 09:18:45 +0300
Subject: [PATCH] gf2p8affine
---
gcc/config/i386/gfniintrin.h | 110 +++++++++++++++++++++
gcc/config/i386/i386-builtin.def | 6 ++
gcc/config/i386/sse.md | 18 ++++
gcc/testsuite/gcc.target/i386/avx-1.c | 6 ++
.../gcc.target/i386/avx512f-gf2p8affineqb-2.c | 74 ++++++++++++++
.../gcc.target/i386/avx512vl-gf2p8affineqb-2.c | 17 ++++
gcc/testsuite/gcc.target/i386/gfni-1.c | 6 ++
gcc/testsuite/gcc.target/i386/gfni-2.c | 12 +++
gcc/testsuite/gcc.target/i386/gfni-3.c | 4 +
gcc/testsuite/gcc.target/i386/gfni-4.c | 4 +-
gcc/testsuite/gcc.target/i386/sse-13.c | 7 ++
gcc/testsuite/gcc.target/i386/sse-14.c | 3 +
gcc/testsuite/gcc.target/i386/sse-23.c | 6 ++
13 files changed, 272 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-gf2p8affineqb-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-gf2p8affineqb-2.c
diff --git a/gcc/config/i386/gfniintrin.h b/gcc/config/i386/gfniintrin.h
index f4ca01c..0cf6fe7 100644
--- a/gcc/config/i386/gfniintrin.h
+++ b/gcc/config/i386/gfniintrin.h
@@ -43,10 +43,21 @@ _mm_gf2p8affineinv_epi64_epi8 (__m128i __A, __m128i __B, const int __C)
(__v16qi) __B,
__C);
}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_gf2p8affine_epi64_epi8 (__m128i __A, __m128i __B, const int __C)
+{
+ return (__m128i) __builtin_ia32_vgf2p8affineqb_v16qi ((__v16qi) __A,
+ (__v16qi) __B, __C);
+}
#else
#define _mm_gf2p8affineinv_epi64_epi8(A, B, C) \
((__m128i) __builtin_ia32_vgf2p8affineinvqb_v16qi((__v16qi)(__m128i)(A), \
(__v16qi)(__m128i)(B), (int)(C)))
+#define _mm_gf2p8affine_epi64_epi8(A, B, C) \
+ ((__m128i) __builtin_ia32_vgf2p8affineqb_v16qi ((__v16qi)(__m128i)(A), \
+ (__v16qi)(__m128i)(B), (int)(C)))
#endif
#ifdef __DISABLE_GFNI__
@@ -69,11 +80,22 @@ _mm256_gf2p8affineinv_epi64_epi8 (__m256i __A, __m256i __B, const int __C)
(__v32qi) __B,
__C);
}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_gf2p8affine_epi64_epi8 (__m256i __A, __m256i __B, const int __C)
+{
+ return (__m256i) __builtin_ia32_vgf2p8affineqb_v32qi ((__v32qi) __A,
+ (__v32qi) __B, __C);
+}
#else
#define _mm256_gf2p8affineinv_epi64_epi8(A, B, C) \
((__m256i) __builtin_ia32_vgf2p8affineinvqb_v32qi((__v32qi)(__m256i)(A), \
(__v32qi)(__m256i)(B), \
(int)(C)))
+#define _mm256_gf2p8affine_epi64_epi8(A, B, C) \
+ ((__m256i) __builtin_ia32_vgf2p8affineqb_v32qi ((__v32qi)(__m256i)(A), \
+ ( __v32qi)(__m256i)(B), (int)(C)))
#endif
#ifdef __DISABLE_GFNIAVX__
@@ -110,6 +132,24 @@ _mm_maskz_gf2p8affineinv_epi64_epi8 (__mmask16 __A, __m128i __B, __m128i __C,
(__v16qi) _mm_setzero_si128 (),
__A);
}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_gf2p8affine_epi64_epi8 (__m128i __A, __mmask16 __B, __m128i __C,
+ __m128i __D, const int __E)
+{
+ return (__m128i) __builtin_ia32_vgf2p8affineqb_v16qi_mask ((__v16qi) __C,
+ (__v16qi) __D, __E, (__v16qi)__A, __B);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_gf2p8affine_epi64_epi8 (__mmask16 __A, __m128i __B, __m128i __C,
+ const int __D)
+{
+ return (__m128i) __builtin_ia32_vgf2p8affineqb_v16qi_mask ((__v16qi) __B,
+ (__v16qi) __C, __D, (__v16qi) _mm_setzero_si128 (), __A);
+}
#else
#define _mm_mask_gf2p8affineinv_epi64_epi8(A, B, C, D, E) \
((__m128i) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask( \
@@ -120,6 +160,13 @@ _mm_maskz_gf2p8affineinv_epi64_epi8 (__mmask16 __A, __m128i __B, __m128i __C,
(__v16qi)(__m128i)(B), (__v16qi)(__m128i)(C), \
(int)(D), (__v16qi)(__m128i) _mm_setzero_si128 (), \
(__mmask16)(A)))
+#define _mm_mask_gf2p8affine_epi64_epi8(A, B, C, D, E) \
+ ((__m128i) __builtin_ia32_vgf2p8affineqb_v16qi_mask((__v16qi)(__m128i)(C),\
+ (__v16qi)(__m128i)(D), (int)(E), (__v16qi)(__m128i)(A), (__mmask16)(B)))
+#define _mm_maskz_gf2p8affine_epi64_epi8(A, B, C, D) \
+ ((__m128i) __builtin_ia32_vgf2p8affineqb_v16qi_mask((__v16qi)(__m128i)(B),\
+ (__v16qi)(__m128i)(C), (int)(D), \
+ (__v16qi)(__m128i) _mm_setzero_si128 (), (__mmask16)(A)))
#endif
#ifdef __DISABLE_GFNIAVX512VL__
@@ -155,6 +202,27 @@ _mm256_maskz_gf2p8affineinv_epi64_epi8 (__mmask32 __A, __m256i __B,
(__v32qi) __C, __D,
(__v32qi) _mm256_setzero_si256 (), __A);
}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_gf2p8affine_epi64_epi8 (__m256i __A, __mmask32 __B, __m256i __C,
+ __m256i __D, const int __E)
+{
+ return (__m256i) __builtin_ia32_vgf2p8affineqb_v32qi_mask ((__v32qi) __C,
+ (__v32qi) __D,
+ __E,
+ (__v32qi)__A,
+ __B);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_gf2p8affine_epi64_epi8 (__mmask32 __A, __m256i __B,
+ __m256i __C, const int __D)
+{
+ return (__m256i) __builtin_ia32_vgf2p8affineqb_v32qi_mask ((__v32qi) __B,
+ (__v32qi) __C, __D, (__v32qi)_mm256_setzero_si256 (), __A);
+}
#else
#define _mm256_mask_gf2p8affineinv_epi64_epi8(A, B, C, D, E) \
((__m256i) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask( \
@@ -164,6 +232,13 @@ _mm256_maskz_gf2p8affineinv_epi64_epi8 (__mmask32 __A, __m256i __B,
((__m256i) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask( \
(__v32qi)(__m256i)(B), (__v32qi)(__m256i)(C), (int)(D), \
(__v32qi)(__m256i) _mm256_setzero_si256 (), (__mmask32)(A)))
+#define _mm256_mask_gf2p8affine_epi64_epi8(A, B, C, D, E) \
+ ((__m256i) __builtin_ia32_vgf2p8affineqb_v32qi_mask((__v32qi)(__m256i)(C),\
+ (__v32qi)(__m256i)(D), (int)(E), (__v32qi)(__m256i)(A), (__mmask32)(B)))
+#define _mm256_maskz_gf2p8affine_epi64_epi8(A, B, C, D) \
+ ((__m256i) __builtin_ia32_vgf2p8affineqb_v32qi_mask((__v32qi)(__m256i)(B),\
+ (__v32qi)(__m256i)(C), (int)(D), \
+ (__v32qi)(__m256i) _mm256_setzero_si256 (), (__mmask32)(A)))
#endif
#ifdef __DISABLE_GFNIAVX512VLBW__
@@ -207,6 +282,31 @@ _mm512_gf2p8affineinv_epi64_epi8 (__m512i __A, __m512i __B, const int __C)
return (__m512i) __builtin_ia32_vgf2p8affineinvqb_v64qi ((__v64qi) __A,
(__v64qi) __B, __C);
}
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_gf2p8affine_epi64_epi8 (__m512i __A, __mmask64 __B, __m512i __C,
+ __m512i __D, const int __E)
+{
+ return (__m512i) __builtin_ia32_vgf2p8affineqb_v64qi_mask ((__v64qi) __C,
+ (__v64qi) __D, __E, (__v64qi)__A, __B);
+}
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_gf2p8affine_epi64_epi8 (__mmask64 __A, __m512i __B, __m512i __C,
+ const int __D)
+{
+ return (__m512i) __builtin_ia32_vgf2p8affineqb_v64qi_mask ((__v64qi) __B,
+ (__v64qi) __C, __D, (__v64qi) _mm512_setzero_si512 (), __A);
+}
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_gf2p8affine_epi64_epi8 (__m512i __A, __m512i __B, const int __C)
+{
+ return (__m512i) __builtin_ia32_vgf2p8affineqb_v64qi ((__v64qi) __A,
+ (__v64qi) __B, __C);
+}
#else
#define _mm512_mask_gf2p8affineinv_epi64_epi8(A, B, C, D, E) \
((__m512i) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask( \
@@ -219,6 +319,16 @@ _mm512_gf2p8affineinv_epi64_epi8 (__m512i __A, __m512i __B, const int __C)
#define _mm512_gf2p8affineinv_epi64_epi8(A, B, C) \
((__m512i) __builtin_ia32_vgf2p8affineinvqb_v64qi ( \
(__v64qi)(__m512i)(A), (__v64qi)(__m512i)(B), (int)(C)))
+#define _mm512_mask_gf2p8affine_epi64_epi8(A, B, C, D, E) \
+ ((__m512i) __builtin_ia32_vgf2p8affineqb_v64qi_mask((__v64qi)(__m512i)(C),\
+ (__v64qi)(__m512i)(D), (int)(E), (__v64qi)(__m512i)(A), (__mmask64)(B)))
+#define _mm512_maskz_gf2p8affine_epi64_epi8(A, B, C, D) \
+ ((__m512i) __builtin_ia32_vgf2p8affineqb_v64qi_mask((__v64qi)(__m512i)(B),\
+ (__v64qi)(__m512i)(C), (int)(D), \
+ (__v64qi)(__m512i) _mm512_setzero_si512 (), (__mmask64)(A)))
+#define _mm512_gf2p8affine_epi64_epi8(A, B, C) \
+ ((__m512i) __builtin_ia32_vgf2p8affineqb_v64qi ((__v64qi)(__m512i)(A), \
+ (__v64qi)(__m512i)(B), (int)(C)))
#endif
#ifdef __DISABLE_GFNIAVX512FBW__
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 3cf5eae..e46a6ab 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -2401,6 +2401,12 @@ BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX, CODE_FOR_vgf2p8affineinvqb_v3
BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vgf2p8affineinvqb_v32qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI)
BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8affineinvqb_v16qi, "__builtin_ia32_vgf2p8affineinvqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEINVQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT)
BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8affineinvqb_v16qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI)
+BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineqb_v64qi, "__builtin_ia32_vgf2p8affineqb_v64qi", IX86_BUILTIN_VGF2P8AFFINEQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineqb_v64qi_mask, "__builtin_ia32_vgf2p8affineqb_v64qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB512MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT_V64QI_UDI)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX, CODE_FOR_vgf2p8affineqb_v32qi, "__builtin_ia32_vgf2p8affineqb_v32qi", IX86_BUILTIN_VGF2P8AFFINEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vgf2p8affineqb_v32qi_mask, "__builtin_ia32_vgf2p8affineqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8affineqb_v16qi, "__builtin_ia32_vgf2p8affineqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8affineqb_v16qi_mask, "__builtin_ia32_vgf2p8affineqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI)
/* Builtins with rounding support. */
BDESC_END (ARGS, ROUND_ARGS)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 4dfb2f8..b272e3a 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -158,6 +158,7 @@
;; For GFNI support
UNSPEC_GF2P8AFFINEINV
+ UNSPEC_GF2P8AFFINE
])
(define_c_enum "unspecv" [
@@ -19991,3 +19992,20 @@
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
(set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "vgf2p8affineqb_<mode><mask_name>"
+ [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
+ (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
+ (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
+ (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
+ UNSPEC_GF2P8AFFINE))]
+ "TARGET_GFNI"
+ "@
+ gf2p8affineqb\t{%3, %2, %0| %0, %2, %3}
+ vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}
+ vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
+ [(set_attr "isa" "noavx,avx,avx512bw")
+ (set_attr "prefix_data16" "1,*,*")
+ (set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,maybe_evex,evex")
+ (set_attr "mode" "<sseinsnmode>")])
diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c
index 4623826..1133a83 100644
--- a/gcc/testsuite/gcc.target/i386/avx-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx-1.c
@@ -610,6 +610,12 @@
#define __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, 1, D, E)
#define __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, 1, D, E)
#define __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v16qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v16qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v32qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v32qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v64qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v64qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v16qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v32qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v64qi_mask(A, B, 1, D, E)
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-gf2p8affineqb-2.c b/gcc/testsuite/gcc.target/i386/avx512f-gf2p8affineqb-2.c
new file mode 100644
index 0000000..807da2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-gf2p8affineqb-2.c
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -mgfni -mavx512bw" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target gfni } */
+
+#define AVX512F
+
+#define GFNI
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 8)
+
+#include "avx512f-mask-type.h"
+#include <x86intrin.h>
+
+static void
+CALC (unsigned char *r, unsigned char *s1, unsigned char *s2, unsigned char imm)
+{
+ for (int a = 0; a < SIZE/8; a++)
+ {
+ for (int val = 0; val < 8; val++)
+ {
+ unsigned char result = 0;
+ for (int bit = 0; bit < 8; bit++)
+ {
+ unsigned char temp = s1[a*8 + val] & s2[a*8 + bit];
+ unsigned char parity = __popcntd(temp);
+ if (parity % 2)
+ result |= (1 << (8 - bit - 1));
+ }
+ r[a*8 + val] = result ^ imm;
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i;
+ UNION_TYPE (AVX512F_LEN, i_b) res1, res2, res3, src1, src2;
+ MASK_TYPE mask = MASK_VALUE;
+ char res_ref[SIZE];
+ unsigned char imm = 0;
+
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = 1 + i;
+ src2.a[i] = 1;
+ }
+
+ for (i = 0; i < SIZE; i++)
+ {
+ res1.a[i] = DEFAULT_VALUE;
+ res2.a[i] = DEFAULT_VALUE;
+ res3.a[i] = DEFAULT_VALUE;
+ }
+
+ CALC (res_ref, src1.a, src2.a, imm);
+
+ res1.x = INTRINSIC (_gf2p8affine_epi64_epi8) (src1.x, src2.x, imm);
+ res2.x = INTRINSIC (_mask_gf2p8affine_epi64_epi8) (res2.x, mask, src1.x, src2.x, imm);
+ res3.x = INTRINSIC (_maskz_gf2p8affine_epi64_epi8) (mask, src1.x, src2.x, imm);
+ if (UNION_CHECK (AVX512F_LEN, i_b) (res1, res_ref))
+ abort ();
+
+ MASK_MERGE (i_b) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_b) (res2, res_ref))
+ abort ();
+
+ MASK_ZERO (i_b) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_b) (res3, res_ref))
+ abort ();
+
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-gf2p8affineqb-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-gf2p8affineqb-2.c
new file mode 100644
index 0000000..1b650d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-gf2p8affineqb-2.c
@@ -0,0 +1,17 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512bw -mavx512vl -mgfni" } */
+/* { dg-require-effective-target avx512vl } */
+/* { dg-require-effective-target avx512bw } */
+/* { dg-require-effective-target gfni } */
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512f-gf2p8affineqb-2.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512f-gf2p8affineqb-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/gfni-1.c b/gcc/testsuite/gcc.target/i386/gfni-1.c
index 5e22c9e..71e6db2 100644
--- a/gcc/testsuite/gcc.target/i386/gfni-1.c
+++ b/gcc/testsuite/gcc.target/i386/gfni-1.c
@@ -3,6 +3,9 @@
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
#include <x86intrin.h>
@@ -15,4 +18,7 @@ avx512vl_test (void)
x1 = _mm512_gf2p8affineinv_epi64_epi8(x1, x2, 3);
x1 = _mm512_mask_gf2p8affineinv_epi64_epi8(x1, m64, x2, x1, 3);
x1 = _mm512_maskz_gf2p8affineinv_epi64_epi8(m64, x1, x2, 3);
+ x1 = _mm512_gf2p8affine_epi64_epi8(x1, x2, 3);
+ x1 = _mm512_mask_gf2p8affine_epi64_epi8(x1, m64, x2, x1, 3);
+ x1 = _mm512_maskz_gf2p8affine_epi64_epi8(m64, x1, x2, 3);
}
diff --git a/gcc/testsuite/gcc.target/i386/gfni-2.c b/gcc/testsuite/gcc.target/i386/gfni-2.c
index 4d1f151..14764b5 100644
--- a/gcc/testsuite/gcc.target/i386/gfni-2.c
+++ b/gcc/testsuite/gcc.target/i386/gfni-2.c
@@ -6,6 +6,12 @@
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
#include <x86intrin.h>
@@ -24,4 +30,10 @@ avx512vl_test (void)
x5 = _mm_gf2p8affineinv_epi64_epi8(x5, x6, 3);
x5 = _mm_mask_gf2p8affineinv_epi64_epi8(x5, m16, x6, x5, 3);
x5 = _mm_maskz_gf2p8affineinv_epi64_epi8(m16, x5, x6, 3);
+ x3 = _mm256_gf2p8affine_epi64_epi8(x3, x4, 3);
+ x3 = _mm256_mask_gf2p8affine_epi64_epi8(x3, m32, x4, x3, 3);
+ x3 = _mm256_maskz_gf2p8affine_epi64_epi8(m32, x3, x4, 3);
+ x5 = _mm_gf2p8affine_epi64_epi8(x5, x6, 3);
+ x5 = _mm_mask_gf2p8affine_epi64_epi8(x5, m16, x6, x5, 3);
+ x5 = _mm_maskz_gf2p8affine_epi64_epi8(m16, x5, x6, 3);
}
diff --git a/gcc/testsuite/gcc.target/i386/gfni-3.c b/gcc/testsuite/gcc.target/i386/gfni-3.c
index de5f80b..3e39f4e 100644
--- a/gcc/testsuite/gcc.target/i386/gfni-3.c
+++ b/gcc/testsuite/gcc.target/i386/gfni-3.c
@@ -2,6 +2,8 @@
/* { dg-options "-mgfni -mavx -O2" } */
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vgf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
#include <x86intrin.h>
@@ -14,4 +16,6 @@ avx512vl_test (void)
{
x3 = _mm256_gf2p8affineinv_epi64_epi8(x3, x4, 3);
x5 = _mm_gf2p8affineinv_epi64_epi8(x5, x6, 3);
+ x3 = _mm256_gf2p8affine_epi64_epi8(x3, x4, 3);
+ x5 = _mm_gf2p8affine_epi64_epi8(x5, x6, 3);
}
diff --git a/gcc/testsuite/gcc.target/i386/gfni-4.c b/gcc/testsuite/gcc.target/i386/gfni-4.c
index 1532716..19409d2 100644
--- a/gcc/testsuite/gcc.target/i386/gfni-4.c
+++ b/gcc/testsuite/gcc.target/i386/gfni-4.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-options "-mgfni -O2" } */
+/* { dg-options "-mgfni -O2 -msse" } */
/* { dg-final { scan-assembler-times "gf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "gf2p8affineqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
#include <x86intrin.h>
@@ -11,4 +12,5 @@ void extern
avx512vl_test (void)
{
x5 = _mm_gf2p8affineinv_epi64_epi8(x5, x6, 3);
+ x5 = _mm_gf2p8affine_epi64_epi8(x5, x6, 3);
}
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c
index c35ec9a..9bdc73f 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -627,5 +627,12 @@
#define __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, 1, D, E)
#define __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, 1, D, E)
#define __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v16qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v16qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v32qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v32qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v64qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v64qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v16qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v32qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v64qi_mask(A, B, 1, D, E)
+
#include <x86intrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c
index 388026f..fb2c35a 100644
--- a/gcc/testsuite/gcc.target/i386/sse-14.c
+++ b/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -689,3 +689,6 @@ test_1 ( __bextri_u64, unsigned long long, unsigned long long, 1)
test_2 (_mm_gf2p8affineinv_epi64_epi8, __m128i, __m128i, __m128i, 1)
test_2 (_mm256_gf2p8affineinv_epi64_epi8, __m256i, __m256i, __m256i, 1)
test_2 (_mm512_gf2p8affineinv_epi64_epi8, __m512i, __m512i, __m512i, 1)
+test_2 (_mm_gf2p8affine_epi64_epi8, __m128i, __m128i, __m128i, 1)
+test_2 (_mm256_gf2p8affine_epi64_epi8, __m256i, __m256i, __m256i, 1)
+test_2 (_mm512_gf2p8affine_epi64_epi8, __m512i, __m512i, __m512i, 1)
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c
index 911258f..66c25c7 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -626,6 +626,12 @@
#define __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, 1, D, E)
#define __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, 1, D, E)
#define __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v16qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v16qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v32qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v32qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v64qi(A, B, C) __builtin_ia32_vgf2p8affineqb_v64qi(A, B, 1)
+#define __builtin_ia32_vgf2p8affineqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v16qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v32qi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vgf2p8affineqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineqb_v64qi_mask(A, B, 1, D, E)
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni")
--
2.5.5
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [patch][i386, AVX] GFNI enabling [3/4]
2017-11-06 8:26 ` Koval, Julia
@ 2017-11-10 20:41 ` Kirill Yukhin
0 siblings, 0 replies; 5+ messages in thread
From: Kirill Yukhin @ 2017-11-10 20:41 UTC (permalink / raw)
To: Koval, Julia; +Cc: 'GCC Patches', 'Jakub Jelinek'
Hello Julia!
On 06 Nov 08:26, Koval, Julia wrote:
> Rebased after last patch fixes.
>
> gcc/
> * config/i386/gfniintrin.h (_mm_gf2p8affine_epi64_epi8,
> _mm256_gf2p8affine_epi64_epi8, _mm_mask_gf2p8affine_epi64_epi8,
> _mm_maskz_gf2p8affine_epi64_epi8, _mm256_mask_gf2p8affine_epi64_epi8,
> _mm256_maskz_gf2p8affine_epi64_epi8,
> _mm512_mask_gf2p8affine_epi64_epi8, _mm512_gf2p8affine_epi64_epi8
> _mm512_maskz_gf2p8affine_epi64_epi8): New intrinsics.
> * config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineqb_v64qi,
> __builtin_ia32_vgf2p8affineqb_v32qi,
> __builtin_ia32_vgf2p8affineqb_v16qi): New builtins.
> * config/i386/sse.md (vgf2p8affineqb_<mode><mask_name>): New pattern.
>
> gcc/testsuite/
> * gcc.target/i386/avx-1.c: Handle new intrinsics.
> * gcc.target/i386/avx512f-gf2p8affineqb-2.c: New runtime tests.
> * gcc.target/i386/avx512vl-gf2p8affineqb-2.c: Ditto.
> * gcc.target/i386/gfni-1.c: Add tests for GF2P8AFFINE.
> * gcc.target/i386/gfni-2.c: Ditto.
> * gcc.target/i386/gfni-3.c: Ditto.
> * gcc.target/i386/gfni-4.c: Ditto.
> * gcc.target/i386/sse-13.c: Handle new tests.
> * gcc.target/i386/sse-14.c: Handle new tests.
> * gcc.target/i386/sse-23.c: Handle new tests.
Your patch is OK for trunk. I've check it in.
--
Thanks, K
>
> > -----Original Message-----
> > From: Koval, Julia
> > Sent: Tuesday, October 17, 2017 3:26 PM
> > To: Jakub Jelinek <jakub@redhat.com>
> > Cc: GCC Patches <gcc-patches@gcc.gnu.org>; Kirill Yukhin
> > <kirill.yukhin@gmail.com>
> > Subject: RE: [patch][i386, AVX] GFNI enabling [3/4]
> >
> > Thanks for your comments, fixed everything.
> >
> > gcc/
> > * config/i386/gfniintrin.h (_mm_gf2p8affine_epi64_epi8,
> > _mm256_gf2p8affine_epi64_epi8, _mm_mask_gf2p8affine_epi64_epi8,
> > _mm_maskz_gf2p8affine_epi64_epi8,
> > _mm256_mask_gf2p8affine_epi64_epi8,
> > _mm256_maskz_gf2p8affine_epi64_epi8,
> > _mm512_mask_gf2p8affine_epi64_epi8, _mm512_gf2p8affine_epi64_epi8
> > _mm512_maskz_gf2p8affine_epi64_epi8): New intrinsics.
> > * config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineqb_v64qi,
> > __builtin_ia32_vgf2p8affineqb_v32qi,
> > __builtin_ia32_vgf2p8affineqb_v16qi): New builtins.
> > * config/i386/sse.md (vgf2p8affineqb_<mode><mask_name>): New
> > pattern.
> >
> > gcc/testsuite/
> > * gcc.target/i386/avx-1.c: Handle new intrinsics.
> > * gcc.target/i386/avx512f-gf2p8affineqb-2.c: New runtime tests.
> > * gcc.target/i386/avx512vl-gf2p8affineqb-2.c: Ditto.
> > * gcc.target/i386/gfni-1.c: Add tests for GF2P8AFFINE.
> > * gcc.target/i386/gfni-2.c: Ditto.
> > * gcc.target/i386/gfni-3.c: Ditto.
> > * gcc.target/i386/gfni-4.c: Ditto.
> > * gcc.target/i386/sse-13.c: Handle new tests.
> > * gcc.target/i386/sse-23.c: Handle new tests.
> >
> >
> > > -----Original Message-----
> > > From: Jakub Jelinek [mailto:jakub@redhat.com]
> > > Sent: Tuesday, October 17, 2017 3:15 PM
> > > To: Koval, Julia <julia.koval@intel.com>
> > > Cc: GCC Patches <gcc-patches@gcc.gnu.org>; Kirill Yukhin
> > > <kirill.yukhin@gmail.com>
> > > Subject: Re: [patch][i386, AVX] GFNI enabling [3/4]
> > >
> > > On Tue, Oct 17, 2017 at 01:09:50PM +0000, Koval, Julia wrote:
> > > > Hi, this the third patch of GFNI ISASET enabling. It enables GF2P8AFFINE
> > > instruction, described here:
> > > https://software.intel.com/sites/default/files/managed/c5/15/architecture-
> > > instruction-set-extensions-programming-reference.pdf
> > > >
> > > > gcc/
> > > > * config/i386/gfniintrin.h (_mm_gf2p8affine_epi64_epi8,
> > > _mm256_gf2p8affine_epi64_epi8,
> > >
> > > Too long line, even ChangeLog entries should be wrapped to 80 columns.
> > >
> > > > (_mm_mask_gf2p8affine_epi64_epi8,
> > > _mm_maskz_gf2p8affine_epi64_epi8,
> > > > _mm256_mask_gf2p8affine_epi64_epi8,
> > > _mm256_maskz_gf2p8affine_epi64_epi8,
> > > > _mm512_mask_gf2p8affine_epi64_epi8,
> > > _mm512_maskz_gf2p8affine_epi64_epi8,
> > >
> > > The above two are also too long (off by 1 char).
> > >
> > > > _mm512_gf2p8affine_epi64_epi8): New intrinsics.
> > > > * config/i386/i386-builtin.def (__builtin_ia32_vgf2p8affineqb_v64qi,
> > > > __builtin_ia32_vgf2p8affineqb_v32qi,
> > > __builtin_ia32_vgf2p8affineqb_v16qi): New builtins.
> > >
> > > And this one too. Please wrap them.
> > >
> > > > * config/i386/sse.md (vgf2p8affineqb_*): New pattern.
> > >
> > > Use vgf2p8affineqb_<mode><mask_name> instead of the wild-card?
> > >
> > > I'll defer actual review to Kirill.
> > >
> > > Jakub
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-11-10 20:30 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-10-17 13:15 [patch][i386, AVX] GFNI enabling [3/4] Koval, Julia
2017-10-17 13:15 ` Jakub Jelinek
2017-10-17 13:26 ` Koval, Julia
2017-11-06 8:26 ` Koval, Julia
2017-11-10 20:41 ` Kirill Yukhin
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).