* [PATCH][i386,AVX] Enable VAES support [2/5]
@ 2017-11-08 12:38 Koval, Julia
2017-12-07 6:34 ` Kirill Yukhin
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Koval, Julia @ 2017-11-08 12:38 UTC (permalink / raw)
To: 'GCC Patches'; +Cc: 'Kirill Yukhin'
[-- Attachment #1: Type: text/plain, Size: 1067 bytes --]
Hi, this patch enables VAESDEC instruction from VAES isaset, defined here: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
Thanks,
Julia
gcc/
* config.gcc: Add vaesintrin.h.
* config/i386/i386-builtin-types.def (V64QI_FTYPE_V64QI_V64QI): New type.
* config/i386/i386-builtin.def (__builtin_ia32_vaesdec_v16qi,
__builtin_ia32_vaesdec_v32qi, __builtin_ia32_vaesdec_v64qi): New builtins.
* config/i386/i386.c (ix86_expand_args_builtin): Handle new type.
* config/i386/immintrin.h: Include vaesintrin.h.
* config/i386/sse.md (vaesdec_<mode>): New pattern.
* config/i386/vaesintrin.h (_mm256_aesdec_epi128, _mm512_aesdec_epi128,
_mm_aesdec_epi128): New intrinsics.
gcc/testsuite/
* gcc.target/i386/avx512-check.h: Handle bit_VAES.
* gcc.target/i386/avx512f-aesdec-2.c: New test.
* gcc.target/i386/avx512fvl-vaes-1.c: Ditto.
* gcc.target/i386/avx512vl-aesdec-2.c: Ditto.
* gcc.target/i386/i386.exp (check_effective_target_avx512vaes): New.
[-- Attachment #2: 0002-VAESDEC.PATCH --]
[-- Type: application/octet-stream, Size: 11551 bytes --]
From fbe586831730fff378c1309b264d4d81011c2c4e Mon Sep 17 00:00:00 2001
From: "julia.koval" <jkoval@gkticlel801.igk.intel.com>
Date: Mon, 27 Feb 2017 22:42:13 +0300
Subject: [PATCH 2/5] VAESDEC
---
gcc/config.gcc | 4 +-
gcc/config/i386/i386-builtin-types.def | 3 ++
gcc/config/i386/i386-builtin.def | 6 +++
gcc/config/i386/i386.c | 1 +
gcc/config/i386/immintrin.h | 2 +
gcc/config/i386/sse.md | 16 ++++++
gcc/config/i386/vaesintrin.h | 59 +++++++++++++++++++++++
gcc/testsuite/gcc.target/i386/avx512-check.h | 3 ++
gcc/testsuite/gcc.target/i386/avx512f-aesdec-2.c | 52 ++++++++++++++++++++
gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c | 24 +++++++++
gcc/testsuite/gcc.target/i386/avx512vl-aesdec-2.c | 17 +++++++
gcc/testsuite/gcc.target/i386/i386.exp | 14 ++++++
12 files changed, 199 insertions(+), 2 deletions(-)
create mode 100644 gcc/config/i386/vaesintrin.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-aesdec-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-aesdec-2.c
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 3dace85..c719821 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -379,7 +379,7 @@ i[34567]86-*-*)
avx512vbmivlintrin.h avx5124fmapsintrin.h avx5124vnniwintrin.h
avx512vpopcntdqintrin.h clwbintrin.h mwaitxintrin.h
clzerointrin.h pkuintrin.h sgxintrin.h cetintrin.h
- gfniintrin.h"
+ gfniintrin.h vaesintrin.h"
;;
x86_64-*-*)
cpu_type=i386
@@ -404,7 +404,7 @@ x86_64-*-*)
avx512vbmivlintrin.h avx5124fmapsintrin.h avx5124vnniwintrin.h
avx512vpopcntdqintrin.h clwbintrin.h mwaitxintrin.h
clzerointrin.h pkuintrin.h sgxintrin.h cetintrin.h
- gfniintrin.h"
+ gfniintrin.h vaesintrin.h"
;;
ia64-*-*)
extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def
index 5b3b96e..265a762 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -1218,3 +1218,6 @@ DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI, INT)
DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI, INT, V64QI, UDI)
DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, INT, V32QI, USI)
DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, INT, V16QI, UHI)
+
+#VAES builtins
+DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 3cf5eae..4e76970 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -2596,6 +2596,12 @@ BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ, CODE_FOR_vpopcountv8di_mask, "__builtin_
/* RDPID */
BDESC (OPTION_MASK_ISA_RDPID, CODE_FOR_rdpid, "__builtin_ia32_rdpid", IX86_BUILTIN_RDPID, UNKNOWN, (int) UNSIGNED_FTYPE_VOID)
+
+/* VAES */
+BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdec_v16qi, "__builtin_ia32_vaesdec_v16qi", IX86_BUILTIN_VAESDEC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
+BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdec_v32qi, "__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI)
+BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
+
BDESC_END (ARGS2, MPX)
/* Builtins for MPX. */
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index f8a91bf..7be62b7 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -33453,6 +33453,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V1DI_FTYPE_V2SI_V2SI:
case V32QI_FTYPE_V16HI_V16HI:
case V16HI_FTYPE_V8SI_V8SI:
+ case V64QI_FTYPE_V64QI_V64QI:
case V32QI_FTYPE_V32QI_V32QI:
case V16HI_FTYPE_V32QI_V32QI:
case V16HI_FTYPE_V16HI_V16HI:
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index 365d2db..eaf1d83 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -94,6 +94,8 @@
#include <gfniintrin.h>
+#include <vaesintrin.h>
+
#ifndef __RDRND__
#pragma GCC push_options
#pragma GCC target("rdrnd")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 200aad6..9064075 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -158,6 +158,9 @@
;; For GFNI support
UNSPEC_GF2P8AFFINEINV
+
+ ;; For VAES support
+ UNSPEC_VAESDEC
])
(define_c_enum "unspecv" [
@@ -354,6 +357,9 @@
(define_mode_iterator VI2_AVX512VL
[(V8HI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL") V32HI])
+(define_mode_iterator VI1_AVX512VL_F
+ [V32QI (V16QI "TARGET_AVX512VL") (V64QI "TARGET_AVX512F")])
+
(define_mode_iterator VI8_AVX2_AVX512BW
[(V8DI "TARGET_AVX512BW") (V4DI "TARGET_AVX2") V2DI])
@@ -19990,3 +19996,13 @@
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
(set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "vaesdec_<mode>"
+ [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
+ (unspec:VI1_AVX512VL_F
+ [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
+ (match_operand:VI1_AVX512VL_F 2 "vector_operand" "v")]
+ UNSPEC_VAESDEC))]
+ "TARGET_VAES"
+ "vaesdec\t{%2, %1, %0|%0, %1, %2}"
+)
diff --git a/gcc/config/i386/vaesintrin.h b/gcc/config/i386/vaesintrin.h
new file mode 100644
index 0000000..0208cc7
--- /dev/null
+++ b/gcc/config/i386/vaesintrin.h
@@ -0,0 +1,59 @@
+#ifndef __VAESINTRIN_H_INCLUDED
+#define __VAESINTRIN_H_INCLUDED
+
+#ifndef __VAES__
+#pragma GCC push_options
+#pragma GCC target("vaes")
+#define __DISABLE_VAES__
+#endif /* __VAES__ */
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_aesdec_epi128 (__m256i __A, __m256i __B)
+{
+ return (__m256i)__builtin_ia32_vaesdec_v32qi ((__v32qi) __A, (__v32qi) __B);
+}
+
+#ifdef __DISABLE_VAES__
+#undef __DISABLE_VAES__
+#pragma GCC pop_options
+#endif /* __DISABLE_VAES__ */
+
+
+#if !defined(__VAES__) || !defined(__AVX512F)
+#pragma GCC push_options
+#pragma GCC target("vaes,avx512f")
+#define __DISABLE_VAESF__
+#endif /* __VAES__ */
+
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_aesdec_epi128 (__m512i __A, __m512i __B)
+{
+ return (__m512i)__builtin_ia32_vaesdec_v64qi ((__v64qi) __A, (__v64qi) __B);
+}
+
+#ifdef __DISABLE_VAESF__
+#undef __DISABLE_VAESF__
+#pragma GCC pop_options
+#endif /* __DISABLE_VAES__ */
+
+#if !defined(__VAES__) || !defined(__AVX512VL)
+#pragma GCC push_options
+#pragma GCC target("vaes,avx512vl")
+#define __DISABLE_VAESVL__
+#endif /* __VAES__ */
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_aesdec_epi128 (__m128i __A, __m128i __B)
+{
+ return (__m128i)__builtin_ia32_vaesdec_v16qi ((__v16qi) __A, (__v16qi) __B);
+}
+
+#ifdef __DISABLE_VAESVL__
+#undef __DISABLE_VAESVL__
+#pragma GCC pop_options
+#endif /* __DISABLE_VAES__ */
+#endif /* __VAESINTRIN_H_INCLUDED */
diff --git a/gcc/testsuite/gcc.target/i386/avx512-check.h b/gcc/testsuite/gcc.target/i386/avx512-check.h
index 9390c1a..528d087 100644
--- a/gcc/testsuite/gcc.target/i386/avx512-check.h
+++ b/gcc/testsuite/gcc.target/i386/avx512-check.h
@@ -78,6 +78,9 @@ main ()
#ifdef GFNI
&& (ecx & bit_GFNI)
#endif
+#ifdef VAES
+ && (ecx & bit_VAES)
+#endif
&& avx512f_os_support ())
{
DO_TEST ();
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-aesdec-2.c b/gcc/testsuite/gcc.target/i386/avx512f-aesdec-2.c
new file mode 100644
index 0000000..a343fbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-aesdec-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -mvaes" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target avx512vaes } */
+
+#define AVX512F
+
+#define VAES
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+
+#include "avx512f-mask-type.h"
+
+static void
+CALC (unsigned int *r)
+{
+ for (int i = 0; i < SIZE; i+=4)
+ {
+ r[i] = 0xba0cda94;
+ r[i + 1] = 0x73676a7;
+ r[i + 2] = 0xd3204422;
+ r[i + 3] = 0x5506edd;
+ }
+}
+
+void
+TEST (void)
+{
+ int i;
+ UNION_TYPE (AVX512F_LEN, i_ud) res1, src1, src2;
+ MASK_TYPE mask = MASK_VALUE;
+ unsigned int res_ref[SIZE];
+
+ for (int i = 0; i < SIZE; i+=4)
+ {
+ src1.a[i] = 0x5d53475d;
+ src1.a[i + 1] = 0x63746f72;
+ src1.a[i + 2] = 0x73745665;
+ src1.a[i + 3] = 0x7b5b5465;
+ src2.a[i] = 0x726f6e5d;
+ src2.a[i + 1] = 0x5b477565;
+ src2.a[i + 2] = 0x68617929;
+ src2.a[i + 3] = 0x48692853;
+ }
+
+ CALC (res_ref);
+ res1.x = INTRINSIC (_aesdec_epi128) (src2.x, src1.x);
+
+ if (UNION_CHECK (AVX512F_LEN, i_ud) (res1, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c b/gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c
new file mode 100644
index 0000000..fc4e6bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mvaes -mavx512f -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+
+/* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+
+/* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x,y;
+volatile __m256i x256, y256;
+volatile __m128i x128, y128;
+
+void extern
+avx512f_test (void)
+{
+ x = _mm512_aesdec_epi128 (x, y);
+
+ x256 = _mm256_aesdec_epi128 (x256, y256);
+
+ x128 = _mm_aesdec_epi128 (x128, y128);
+
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-aesdec-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-aesdec-2.c
new file mode 100644
index 0000000..92a6eb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-aesdec-2.c
@@ -0,0 +1,17 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512bw -mavx512vl -mvaes" } */
+/* { dg-require-effective-target avx512vl } */
+/* { dg-require-effective-target avx512bw } */
+/* { dg-require-effective-target avx512vaes } */
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512f-aesdec-2.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512f-aesdec-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/i386.exp b/gcc/testsuite/gcc.target/i386/i386.exp
index b2bdbfd..f66f86e 100644
--- a/gcc/testsuite/gcc.target/i386/i386.exp
+++ b/gcc/testsuite/gcc.target/i386/i386.exp
@@ -436,6 +436,20 @@ proc check_effective_target_gfni { } {
} "-mgfni" ]
}
+# Return 1 if vaes instructions can be compiled.
+proc check_effective_target_avx512vaes { } {
+ return [check_no_compiler_messages avx512vaes object {
+
+ typedef int __v16si __attribute__ ((__vector_size__ (64)));
+
+ __v32qi
+ _mm256_aesdec_epi128 (__v32qi __A, __v32qi __B)
+ {
+ return (__v32qi)__builtin_ia32_vaesdec_v32qi ((__v32qi) __A, (__v32qi) __B);
+ }
+ } "-mvaes" ]
+}
+
# If a testcase doesn't have special options, use these.
global DEFAULT_CFLAGS
if ![info exists DEFAULT_CFLAGS] then {
--
2.5.5
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH][i386,AVX] Enable VAES support [2/5]
2017-11-08 12:38 [PATCH][i386,AVX] Enable VAES support [2/5] Koval, Julia
@ 2017-12-07 6:34 ` Kirill Yukhin
2017-12-08 5:09 ` Kirill Yukhin
2017-12-12 5:56 ` Kirill Yukhin
2 siblings, 0 replies; 4+ messages in thread
From: Kirill Yukhin @ 2017-12-07 6:34 UTC (permalink / raw)
To: Koval, Julia; +Cc: 'GCC Patches'
Hello Julia,
On 08 Nov 12:32, Koval, Julia wrote:
> Hi, this patch enables VAESDEC instruction from VAES isaset, defined here: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
>
> Ok for trunk?
Your patch is OK. I've checked it in.
--
Thanks, K
> Thanks,
> Julia
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH][i386,AVX] Enable VAES support [2/5]
2017-11-08 12:38 [PATCH][i386,AVX] Enable VAES support [2/5] Koval, Julia
2017-12-07 6:34 ` Kirill Yukhin
@ 2017-12-08 5:09 ` Kirill Yukhin
2017-12-12 5:56 ` Kirill Yukhin
2 siblings, 0 replies; 4+ messages in thread
From: Kirill Yukhin @ 2017-12-08 5:09 UTC (permalink / raw)
To: Koval, Julia; +Cc: 'GCC Patches'
Hello Julia,
On 08 Nov 12:32, Koval, Julia wrote:
> Hi, this patch enables VAESDEC instruction from VAES isaset, defined here: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
>
> Ok for trunk?
Patch is OK. I've checked it in.
> Thanks,
> Julia
--
Thanks, K
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH][i386,AVX] Enable VAES support [2/5]
2017-11-08 12:38 [PATCH][i386,AVX] Enable VAES support [2/5] Koval, Julia
2017-12-07 6:34 ` Kirill Yukhin
2017-12-08 5:09 ` Kirill Yukhin
@ 2017-12-12 5:56 ` Kirill Yukhin
2 siblings, 0 replies; 4+ messages in thread
From: Kirill Yukhin @ 2017-12-12 5:56 UTC (permalink / raw)
To: Koval, Julia; +Cc: 'GCC Patches'
Hello Julia,
On 08 Nov 12:32, Koval, Julia wrote:
> Hi, this patch enables VAESDEC instruction from VAES isaset, defined here: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
>
> Ok for trunk?
Patch is OK. Checked into main trunk
--
Thanks, K
> Thanks,
> Julia
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-12-12 5:56 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-08 12:38 [PATCH][i386,AVX] Enable VAES support [2/5] Koval, Julia
2017-12-07 6:34 ` Kirill Yukhin
2017-12-08 5:09 ` Kirill Yukhin
2017-12-12 5:56 ` Kirill Yukhin
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).