* [patch][x86] Split-up march icelake on march=icelake-server and march=icelake-client @ 2018-03-12 20:47 Koval, Julia 2018-03-12 21:20 ` Joseph Myers 0 siblings, 1 reply; 5+ messages in thread From: Koval, Julia @ 2018-03-12 20:47 UTC (permalink / raw) To: 'GCC Patches'; +Cc: Uros Bizjak [-- Attachment #1: Type: text/plain, Size: 919 bytes --] Hi, This patch introduces separate client and server arch options instead of -march=icelake. Ok for trunk? Thanks, Julia gcc/ * config.gcc (icelake-client, icelake-server): New. (icelake): Remove. * config/i386/i386.c (initial_ix86_tune_features): Extend to 64 bit. (initial_ix86_arch_features): Ditto. (ix86_option_override_internal): Split up icelake on icelake client and icelake server. (get_builtin_code_for_version): Ditto. (fold_builtin_cpu): Ditto. * config/i386/driver-i386.c (config/i386/driver-i386.c): Ditto. * config/i386/i386-c.c (ix86_target_macros_internal): Ditto * config/i386/i386.h (processor_type) Ditto. gcc/testsuite/ * g++.dg/ext/mv16.C: Split up icelake on icelake client and icelake-server. * gcc.target/i386/funcspec-56.inc: Ditto. libgcc/ * config/i386/cpuinfo.h (processor_subtypes): Split up icelake on icelake client and icelake-server. [-- Attachment #2: 0001-icelake-client.patch --] [-- Type: application/octet-stream, Size: 16500 bytes --] From 17183eec6cff9f0ba9d983821b5b5b6e87da5134 Mon Sep 17 00:00:00 2001 From: julia <jkoval@gkticlel801.igk.intel.com> Date: Mon, 12 Mar 2018 16:28:54 +0300 Subject: [PATCH] icelake-client --- gcc/config.gcc | 2 +- gcc/config/i386/driver-i386.c | 7 +- gcc/config/i386/i386-c.c | 17 +++-- gcc/config/i386/i386.c | 104 +++++++++++++++----------- gcc/config/i386/i386.h | 6 +- gcc/testsuite/g++.dg/ext/mv16.C | 10 ++- gcc/testsuite/gcc.target/i386/funcspec-56.inc | 3 +- libgcc/config/i386/cpuinfo.h | 3 +- 8 files changed, 96 insertions(+), 56 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 81627d5..f7b2659 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -637,7 +637,7 @@ x86_64_archs="amdfam10 athlon64 athlon64-sse3 barcelona bdver1 bdver2 \ bdver3 bdver4 znver1 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \ core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \ sandybridge ivybridge haswell broadwell bonnell silvermont knl knm \ -skylake-avx512 cannonlake icelake x86-64 native" +skylake-avx512 cannonlake icelake-client icelake-server x86-64 native" # Additional x86 processors supported by --with-cpu=. Each processor # MUST be separated by exactly one space. diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index 8c95c2e..4f59854 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -825,9 +825,12 @@ const char *host_detect_local_cpu (int argc, const char **argv) if (arch) { /* This is unknown family 0x6 CPU. */ + /* Assume Ice Lake Server. */ + if (has_wbnoinvd) + cpu = "icelake-server"; /* Assume Ice Lake. */ - if (has_gfni) - cpu = "icelake"; + else if (has_gfni) + cpu = "icelake-client"; /* Assume Cannon Lake. */ else if (has_avx512vbmi) cpu = "cannonlake"; diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 644958a..6c50e20 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -190,9 +190,13 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__cannonlake"); def_or_undef (parse_in, "__cannonlake__"); break; - case PROCESSOR_ICELAKE: - def_or_undef (parse_in, "__icelake"); - def_or_undef (parse_in, "__icelake__"); + case PROCESSOR_ICELAKE_CLIENT: + def_or_undef (parse_in, "__icelake_client"); + def_or_undef (parse_in, "__icelake_client__"); + break; + case PROCESSOR_ICELAKE_SERVER: + def_or_undef (parse_in, "__icelake_server"); + def_or_undef (parse_in, "__icelake_server__"); break; /* use PROCESSOR_max to not set/unset the arch macro. */ case PROCESSOR_max: @@ -315,8 +319,11 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, case PROCESSOR_CANNONLAKE: def_or_undef (parse_in, "__tune_cannonlake__"); break; - case PROCESSOR_ICELAKE: - def_or_undef (parse_in, "__tune_icelake__"); + case PROCESSOR_ICELAKE_CLIENT: + def_or_undef (parse_in, "__tune_icelake_client__"); + break; + case PROCESSOR_ICELAKE_SERVER: + def_or_undef (parse_in, "__tune_icelake_server__"); break; case PROCESSOR_LAKEMONT: def_or_undef (parse_in, "__tune_lakemont__"); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index af24c6e..d747a0a 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -127,48 +127,49 @@ const struct processor_costs *ix86_tune_cost = NULL; const struct processor_costs *ix86_cost = NULL; /* Processor feature/optimization bitmasks. */ -#define m_386 (1U<<PROCESSOR_I386) -#define m_486 (1U<<PROCESSOR_I486) -#define m_PENT (1U<<PROCESSOR_PENTIUM) -#define m_LAKEMONT (1U<<PROCESSOR_LAKEMONT) -#define m_PPRO (1U<<PROCESSOR_PENTIUMPRO) -#define m_PENT4 (1U<<PROCESSOR_PENTIUM4) -#define m_NOCONA (1U<<PROCESSOR_NOCONA) +#define m_386 (HOST_WIDE_INT_1U<<PROCESSOR_I386) +#define m_486 (HOST_WIDE_INT_1U<<PROCESSOR_I486) +#define m_PENT (HOST_WIDE_INT_1U<<PROCESSOR_PENTIUM) +#define m_LAKEMONT (HOST_WIDE_INT_1U<<PROCESSOR_LAKEMONT) +#define m_PPRO (HOST_WIDE_INT_1U<<PROCESSOR_PENTIUMPRO) +#define m_PENT4 (HOST_WIDE_INT_1U<<PROCESSOR_PENTIUM4) +#define m_NOCONA (HOST_WIDE_INT_1U<<PROCESSOR_NOCONA) #define m_P4_NOCONA (m_PENT4 | m_NOCONA) -#define m_CORE2 (1U<<PROCESSOR_CORE2) -#define m_NEHALEM (1U<<PROCESSOR_NEHALEM) -#define m_SANDYBRIDGE (1U<<PROCESSOR_SANDYBRIDGE) -#define m_HASWELL (1U<<PROCESSOR_HASWELL) +#define m_CORE2 (HOST_WIDE_INT_1U<<PROCESSOR_CORE2) +#define m_NEHALEM (HOST_WIDE_INT_1U<<PROCESSOR_NEHALEM) +#define m_SANDYBRIDGE (HOST_WIDE_INT_1U<<PROCESSOR_SANDYBRIDGE) +#define m_HASWELL (HOST_WIDE_INT_1U<<PROCESSOR_HASWELL) #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL) -#define m_BONNELL (1U<<PROCESSOR_BONNELL) -#define m_SILVERMONT (1U<<PROCESSOR_SILVERMONT) -#define m_KNL (1U<<PROCESSOR_KNL) -#define m_KNM (1U<<PROCESSOR_KNM) -#define m_SKYLAKE_AVX512 (1U<<PROCESSOR_SKYLAKE_AVX512) -#define m_CANNONLAKE (1U<<PROCESSOR_CANNONLAKE) -#define m_ICELAKE (1U<<PROCESSOR_ICELAKE) -#define m_INTEL (1U<<PROCESSOR_INTEL) - -#define m_GEODE (1U<<PROCESSOR_GEODE) -#define m_K6 (1U<<PROCESSOR_K6) +#define m_BONNELL (HOST_WIDE_INT_1U<<PROCESSOR_BONNELL) +#define m_SILVERMONT (HOST_WIDE_INT_1U<<PROCESSOR_SILVERMONT) +#define m_KNL (HOST_WIDE_INT_1U<<PROCESSOR_KNL) +#define m_KNM (HOST_WIDE_INT_1U<<PROCESSOR_KNM) +#define m_SKYLAKE_AVX512 (HOST_WIDE_INT_1U<<PROCESSOR_SKYLAKE_AVX512) +#define m_CANNONLAKE (HOST_WIDE_INT_1U<<PROCESSOR_CANNONLAKE) +#define m_ICELAKE_CLIENT (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_CLIENT) +#define m_ICELAKE_SERVER (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_SERVER) +#define m_INTEL (HOST_WIDE_INT_1U<<PROCESSOR_INTEL) + +#define m_GEODE (HOST_WIDE_INT_1U<<PROCESSOR_GEODE) +#define m_K6 (HOST_WIDE_INT_1U<<PROCESSOR_K6) #define m_K6_GEODE (m_K6 | m_GEODE) -#define m_K8 (1U<<PROCESSOR_K8) -#define m_ATHLON (1U<<PROCESSOR_ATHLON) +#define m_K8 (HOST_WIDE_INT_1U<<PROCESSOR_K8) +#define m_ATHLON (HOST_WIDE_INT_1U<<PROCESSOR_ATHLON) #define m_ATHLON_K8 (m_K8 | m_ATHLON) -#define m_AMDFAM10 (1U<<PROCESSOR_AMDFAM10) -#define m_BDVER1 (1U<<PROCESSOR_BDVER1) -#define m_BDVER2 (1U<<PROCESSOR_BDVER2) -#define m_BDVER3 (1U<<PROCESSOR_BDVER3) -#define m_BDVER4 (1U<<PROCESSOR_BDVER4) -#define m_ZNVER1 (1U<<PROCESSOR_ZNVER1) -#define m_BTVER1 (1U<<PROCESSOR_BTVER1) -#define m_BTVER2 (1U<<PROCESSOR_BTVER2) +#define m_AMDFAM10 (HOST_WIDE_INT_1U<<PROCESSOR_AMDFAM10) +#define m_BDVER1 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER1) +#define m_BDVER2 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER2) +#define m_BDVER3 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER3) +#define m_BDVER4 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER4) +#define m_ZNVER1 (HOST_WIDE_INT_1U<<PROCESSOR_ZNVER1) +#define m_BTVER1 (HOST_WIDE_INT_1U<<PROCESSOR_BTVER1) +#define m_BTVER2 (HOST_WIDE_INT_1U<<PROCESSOR_BTVER2) #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4) #define m_BTVER (m_BTVER1 | m_BTVER2) #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER \ | m_ZNVER1) -#define m_GENERIC (1U<<PROCESSOR_GENERIC) +#define m_GENERIC (HOST_WIDE_INT_1U<<PROCESSOR_GENERIC) const char* ix86_tune_feature_names[X86_TUNE_LAST] = { #undef DEF_TUNE @@ -182,7 +183,7 @@ unsigned char ix86_tune_features[X86_TUNE_LAST]; /* Feature tests against the various tunings used to create ix86_tune_features based on the processor mask. */ -static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = { +static unsigned long long initial_ix86_tune_features[X86_TUNE_LAST] = { #undef DEF_TUNE #define DEF_TUNE(tune, name, selector) selector, #include "x86-tune.def" @@ -194,7 +195,7 @@ unsigned char ix86_arch_features[X86_ARCH_LAST]; /* Feature tests against the various architecture variations, used to create ix86_arch_features based on the processor mask. */ -static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = { +static unsigned long long initial_ix86_arch_features[X86_ARCH_LAST] = { /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */ ~(m_386 | m_486 | m_PENT | m_LAKEMONT | m_K6), @@ -860,7 +861,8 @@ static const struct ptt processor_target_table[PROCESSOR_max] = {"knm", &slm_cost, 16, 15, 16, 7, 16}, {"skylake-avx512", &skylake_cost, 16, 10, 16, 10, 16}, {"cannonlake", &skylake_cost, 16, 10, 16, 10, 16}, - {"icelake", &skylake_cost, 16, 10, 16, 10, 16}, + {"icelake-client", &skylake_cost, 16, 10, 16, 10, 16}, + {"icelake-server", &skylake_cost, 16, 10, 16, 10, 16}, {"intel", &intel_cost, 16, 15, 16, 7, 16}, {"geode", &geode_cost, 0, 0, 0, 0, 0}, {"k6", &k6_cost, 32, 7, 32, 7, 32}, @@ -3445,6 +3447,8 @@ ix86_option_override_internal (bool main_args_p, const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4); const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5); const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6); + const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7); + const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8); const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR; @@ -3467,9 +3471,12 @@ ix86_option_override_internal (bool main_args_p, const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA; - const wide_int_bitmask PTA_ICELAKE = PTA_CANNONLAKE | PTA_AVX512VNNI + const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG | PTA_RDPID; + const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_CANNONLAKE | PTA_AVX512VNNI + | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG + | PTA_RDPID | PTA_PCONFIG | PTA_WBNOINVD; const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD; const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; @@ -3541,7 +3548,10 @@ ix86_option_override_internal (bool main_args_p, {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_SKYLAKE_AVX512}, {"cannonlake", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_CANNONLAKE}, - {"icelake", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_ICELAKE}, + {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL, + PTA_ICELAKE_CLIENT}, + {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL, + PTA_ICELAKE_SERVER}, {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL}, {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL}, {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT}, @@ -4150,6 +4160,12 @@ ix86_option_override_internal (bool main_args_p, if (((processor_alias_table[i].flags & PTA_RDPID) != 0) && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID)) opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID; + if (((processor_alias_table[i].flags & PTA_PCONFIG) != 0) + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_PCONFIG)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG; + if (((processor_alias_table[i].flags & PTA_WBNOINVD) != 0) + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_WBNOINVD)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD; if ((processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)) != 0) @@ -32376,8 +32392,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) break; case PROCESSOR_HASWELL: case PROCESSOR_SKYLAKE_AVX512: - if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_GFNI) - arg_str = "icelake"; + if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_WBNOINVD) + arg_str = "icelake-server"; + else if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_GFNI) + arg_str = "icelake-client"; else if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VBMI) arg_str = "cannonlake"; @@ -33105,7 +33123,8 @@ fold_builtin_cpu (tree fndecl, tree *args) M_INTEL_COREI7_SKYLAKE, M_INTEL_COREI7_SKYLAKE_AVX512, M_INTEL_COREI7_CANNONLAKE, - M_INTEL_COREI7_ICELAKE + M_INTEL_COREI7_ICELAKE_CLIENT, + M_INTEL_COREI7_ICELAKE_SERVER }; static struct _arch_names_table @@ -33130,7 +33149,8 @@ fold_builtin_cpu (tree fndecl, tree *args) {"skylake", M_INTEL_COREI7_SKYLAKE}, {"skylake-avx512", M_INTEL_COREI7_SKYLAKE_AVX512}, {"cannonlake", M_INTEL_COREI7_CANNONLAKE}, - {"icelake", M_INTEL_COREI7_ICELAKE}, + {"icelake-client", M_INTEL_COREI7_ICELAKE_CLIENT}, + {"icelake-server", M_INTEL_COREI7_ICELAKE_SERVER}, {"bonnell", M_INTEL_BONNELL}, {"silvermont", M_INTEL_SILVERMONT}, {"knl", M_INTEL_KNL}, diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index e43edd7..7f4b04f 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -387,7 +387,8 @@ extern const struct processor_costs ix86_size_cost; #define TARGET_KNM (ix86_tune == PROCESSOR_KNM) #define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512) #define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE) -#define TARGET_ICELAKE (ix86_tune == PROCESSOR_ICELAKE) +#define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT) +#define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER) #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) @@ -2268,7 +2269,8 @@ enum processor_type PROCESSOR_KNM, PROCESSOR_SKYLAKE_AVX512, PROCESSOR_CANNONLAKE, - PROCESSOR_ICELAKE, + PROCESSOR_ICELAKE_CLIENT, + PROCESSOR_ICELAKE_SERVER, PROCESSOR_INTEL, PROCESSOR_GEODE, PROCESSOR_K6, diff --git a/gcc/testsuite/g++.dg/ext/mv16.C b/gcc/testsuite/g++.dg/ext/mv16.C index 8fbdb47..3e7c228 100644 --- a/gcc/testsuite/g++.dg/ext/mv16.C +++ b/gcc/testsuite/g++.dg/ext/mv16.C @@ -60,10 +60,14 @@ int __attribute__ ((target("arch=cannonlake"))) foo () { return 16; } -int __attribute__ ((target("arch=icelake"))) foo () { +int __attribute__ ((target("arch=icelake-client"))) foo () { return 17; } +int __attribute__ ((target("arch=icelake-server"))) foo () { + return 18; +} + int main () { int val = foo (); @@ -86,8 +90,10 @@ int main () assert (val == 15); else if (__builtin_cpu_is ("cannonlake")) assert (val == 16); - else if (__builtin_cpu_is ("icelake")) + else if (__builtin_cpu_is ("icelake-client")) assert (val == 17); + else if (__builtin_cpu_is ("icelake-server")) + assert (val == 18); else assert (val == 0); diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc index 837cdc3..35b287a 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc @@ -145,7 +145,8 @@ extern void test_arch_knl (void) __attribute__((__target__("arch=knl"))); extern void test_arch_knm (void) __attribute__((__target__("arch=knm"))); extern void test_arch_skylake_avx512 (void) __attribute__((__target__("arch=skylake-avx512"))); extern void test_arch_cannonlake (void) __attribute__((__target__("arch=cannonlake"))); -extern void test_arch_icelake (void) __attribute__((__target__("arch=icelake"))); +extern void test_arch_icelake_client (void) __attribute__((__target__("arch=icelake-client"))); +extern void test_arch_icelake_server (void) __attribute__((__target__("arch=icelake-server"))); extern void test_arch_k8 (void) __attribute__((__target__("arch=k8"))); extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3"))); extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron"))); diff --git a/libgcc/config/i386/cpuinfo.h b/libgcc/config/i386/cpuinfo.h index a247072..17e2abf 100644 --- a/libgcc/config/i386/cpuinfo.h +++ b/libgcc/config/i386/cpuinfo.h @@ -70,7 +70,8 @@ enum processor_subtypes INTEL_COREI7_SKYLAKE, INTEL_COREI7_SKYLAKE_AVX512, INTEL_COREI7_CANNONLAKE, - INTEL_COREI7_ICELAKE, + INTEL_COREI7_ICELAKE_CLIENT, + INTEL_COREI7_ICELAKE_SERVER, CPU_SUBTYPE_MAX }; -- 2.5.5 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [patch][x86] Split-up march icelake on march=icelake-server and march=icelake-client 2018-03-12 20:47 [patch][x86] Split-up march icelake on march=icelake-server and march=icelake-client Koval, Julia @ 2018-03-12 21:20 ` Joseph Myers 2018-03-13 7:42 ` Koval, Julia 0 siblings, 1 reply; 5+ messages in thread From: Joseph Myers @ 2018-03-12 21:20 UTC (permalink / raw) To: Koval, Julia; +Cc: 'GCC Patches', Uros Bizjak On Mon, 12 Mar 2018, Koval, Julia wrote: > Hi, > This patch introduces separate client and server arch options instead of > -march=icelake. Ok for trunk? I don't see any invoke.texi updates here to document what these two options mean (including, presumably, different lists of features for them). -- Joseph S. Myers joseph@codesourcery.com ^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [patch][x86] Split-up march icelake on march=icelake-server and march=icelake-client 2018-03-12 21:20 ` Joseph Myers @ 2018-03-13 7:42 ` Koval, Julia 2018-03-14 7:48 ` Koval, Julia 0 siblings, 1 reply; 5+ messages in thread From: Koval, Julia @ 2018-03-13 7:42 UTC (permalink / raw) To: Joseph Myers; +Cc: 'GCC Patches', Uros Bizjak [-- Attachment #1: Type: text/plain, Size: 1627 bytes --] Fixed invoke.texi. Here is the new version. gcc/ * config.gcc (icelake-client, icelake-server): New. (icelake): Remove. * config/i386/i386.c (initial_ix86_tune_features): Extend to 64 bit. (initial_ix86_arch_features): Ditto. (ix86_option_override_internal): Split up icelake on icelake client and icelake server. (get_builtin_code_for_version): Ditto. (fold_builtin_cpu): Ditto. * config/i386/driver-i386.c (config/i386/driver-i386.c): Ditto. * config/i386/i386-c.c (ix86_target_macros_internal): Ditto * config/i386/i386.h (processor_type) Ditto. * doc/invoke.texi: Ditto. gcc/testsuite/ * g++.dg/ext/mv16.C: Split up icelake on icelake client and icelake-server. * gcc.target/i386/funcspec-56.inc: Ditto. libgcc/ * config/i386/cpuinfo.h (processor_subtypes): Split up icelake on icelake client and icelake-server. Thanks, Julia > -----Original Message----- > From: Joseph Myers [mailto:joseph@codesourcery.com] > Sent: Monday, March 12, 2018 10:21 PM > To: Koval, Julia <julia.koval@intel.com> > Cc: 'GCC Patches' <gcc-patches@gcc.gnu.org>; Uros Bizjak > <ubizjak@gmail.com> > Subject: Re: [patch][x86] Split-up march icelake on march=icelake-server and > march=icelake-client > > On Mon, 12 Mar 2018, Koval, Julia wrote: > > > Hi, > > This patch introduces separate client and server arch options instead of > > -march=icelake. Ok for trunk? > > I don't see any invoke.texi updates here to document what these two > options mean (including, presumably, different lists of features for > them). > > -- > Joseph S. Myers > joseph@codesourcery.com [-- Attachment #2: 0001-icelake-client.patch --] [-- Type: application/octet-stream, Size: 18016 bytes --] From 235d50fdbcdc5cd5fa7568e20751f7e290824e58 Mon Sep 17 00:00:00 2001 From: julia <jkoval@gkticlel801.igk.intel.com> Date: Mon, 12 Mar 2018 16:28:54 +0300 Subject: [PATCH] icelake-client --- gcc/config.gcc | 2 +- gcc/config/i386/driver-i386.c | 7 +- gcc/config/i386/i386-c.c | 17 +++-- gcc/config/i386/i386.c | 104 +++++++++++++++----------- gcc/config/i386/i386.h | 6 +- gcc/doc/invoke.texi | 13 +++- gcc/testsuite/g++.dg/ext/mv16.C | 10 ++- gcc/testsuite/gcc.target/i386/funcspec-56.inc | 3 +- libgcc/config/i386/cpuinfo.h | 3 +- 9 files changed, 107 insertions(+), 58 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 81627d5..f7b2659 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -637,7 +637,7 @@ x86_64_archs="amdfam10 athlon64 athlon64-sse3 barcelona bdver1 bdver2 \ bdver3 bdver4 znver1 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \ core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \ sandybridge ivybridge haswell broadwell bonnell silvermont knl knm \ -skylake-avx512 cannonlake icelake x86-64 native" +skylake-avx512 cannonlake icelake-client icelake-server x86-64 native" # Additional x86 processors supported by --with-cpu=. Each processor # MUST be separated by exactly one space. diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index 8c95c2e..4f59854 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -825,9 +825,12 @@ const char *host_detect_local_cpu (int argc, const char **argv) if (arch) { /* This is unknown family 0x6 CPU. */ + /* Assume Ice Lake Server. */ + if (has_wbnoinvd) + cpu = "icelake-server"; /* Assume Ice Lake. */ - if (has_gfni) - cpu = "icelake"; + else if (has_gfni) + cpu = "icelake-client"; /* Assume Cannon Lake. */ else if (has_avx512vbmi) cpu = "cannonlake"; diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 644958a..6c50e20 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -190,9 +190,13 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__cannonlake"); def_or_undef (parse_in, "__cannonlake__"); break; - case PROCESSOR_ICELAKE: - def_or_undef (parse_in, "__icelake"); - def_or_undef (parse_in, "__icelake__"); + case PROCESSOR_ICELAKE_CLIENT: + def_or_undef (parse_in, "__icelake_client"); + def_or_undef (parse_in, "__icelake_client__"); + break; + case PROCESSOR_ICELAKE_SERVER: + def_or_undef (parse_in, "__icelake_server"); + def_or_undef (parse_in, "__icelake_server__"); break; /* use PROCESSOR_max to not set/unset the arch macro. */ case PROCESSOR_max: @@ -315,8 +319,11 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, case PROCESSOR_CANNONLAKE: def_or_undef (parse_in, "__tune_cannonlake__"); break; - case PROCESSOR_ICELAKE: - def_or_undef (parse_in, "__tune_icelake__"); + case PROCESSOR_ICELAKE_CLIENT: + def_or_undef (parse_in, "__tune_icelake_client__"); + break; + case PROCESSOR_ICELAKE_SERVER: + def_or_undef (parse_in, "__tune_icelake_server__"); break; case PROCESSOR_LAKEMONT: def_or_undef (parse_in, "__tune_lakemont__"); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index af24c6e..d747a0a 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -127,48 +127,49 @@ const struct processor_costs *ix86_tune_cost = NULL; const struct processor_costs *ix86_cost = NULL; /* Processor feature/optimization bitmasks. */ -#define m_386 (1U<<PROCESSOR_I386) -#define m_486 (1U<<PROCESSOR_I486) -#define m_PENT (1U<<PROCESSOR_PENTIUM) -#define m_LAKEMONT (1U<<PROCESSOR_LAKEMONT) -#define m_PPRO (1U<<PROCESSOR_PENTIUMPRO) -#define m_PENT4 (1U<<PROCESSOR_PENTIUM4) -#define m_NOCONA (1U<<PROCESSOR_NOCONA) +#define m_386 (HOST_WIDE_INT_1U<<PROCESSOR_I386) +#define m_486 (HOST_WIDE_INT_1U<<PROCESSOR_I486) +#define m_PENT (HOST_WIDE_INT_1U<<PROCESSOR_PENTIUM) +#define m_LAKEMONT (HOST_WIDE_INT_1U<<PROCESSOR_LAKEMONT) +#define m_PPRO (HOST_WIDE_INT_1U<<PROCESSOR_PENTIUMPRO) +#define m_PENT4 (HOST_WIDE_INT_1U<<PROCESSOR_PENTIUM4) +#define m_NOCONA (HOST_WIDE_INT_1U<<PROCESSOR_NOCONA) #define m_P4_NOCONA (m_PENT4 | m_NOCONA) -#define m_CORE2 (1U<<PROCESSOR_CORE2) -#define m_NEHALEM (1U<<PROCESSOR_NEHALEM) -#define m_SANDYBRIDGE (1U<<PROCESSOR_SANDYBRIDGE) -#define m_HASWELL (1U<<PROCESSOR_HASWELL) +#define m_CORE2 (HOST_WIDE_INT_1U<<PROCESSOR_CORE2) +#define m_NEHALEM (HOST_WIDE_INT_1U<<PROCESSOR_NEHALEM) +#define m_SANDYBRIDGE (HOST_WIDE_INT_1U<<PROCESSOR_SANDYBRIDGE) +#define m_HASWELL (HOST_WIDE_INT_1U<<PROCESSOR_HASWELL) #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL) -#define m_BONNELL (1U<<PROCESSOR_BONNELL) -#define m_SILVERMONT (1U<<PROCESSOR_SILVERMONT) -#define m_KNL (1U<<PROCESSOR_KNL) -#define m_KNM (1U<<PROCESSOR_KNM) -#define m_SKYLAKE_AVX512 (1U<<PROCESSOR_SKYLAKE_AVX512) -#define m_CANNONLAKE (1U<<PROCESSOR_CANNONLAKE) -#define m_ICELAKE (1U<<PROCESSOR_ICELAKE) -#define m_INTEL (1U<<PROCESSOR_INTEL) - -#define m_GEODE (1U<<PROCESSOR_GEODE) -#define m_K6 (1U<<PROCESSOR_K6) +#define m_BONNELL (HOST_WIDE_INT_1U<<PROCESSOR_BONNELL) +#define m_SILVERMONT (HOST_WIDE_INT_1U<<PROCESSOR_SILVERMONT) +#define m_KNL (HOST_WIDE_INT_1U<<PROCESSOR_KNL) +#define m_KNM (HOST_WIDE_INT_1U<<PROCESSOR_KNM) +#define m_SKYLAKE_AVX512 (HOST_WIDE_INT_1U<<PROCESSOR_SKYLAKE_AVX512) +#define m_CANNONLAKE (HOST_WIDE_INT_1U<<PROCESSOR_CANNONLAKE) +#define m_ICELAKE_CLIENT (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_CLIENT) +#define m_ICELAKE_SERVER (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_SERVER) +#define m_INTEL (HOST_WIDE_INT_1U<<PROCESSOR_INTEL) + +#define m_GEODE (HOST_WIDE_INT_1U<<PROCESSOR_GEODE) +#define m_K6 (HOST_WIDE_INT_1U<<PROCESSOR_K6) #define m_K6_GEODE (m_K6 | m_GEODE) -#define m_K8 (1U<<PROCESSOR_K8) -#define m_ATHLON (1U<<PROCESSOR_ATHLON) +#define m_K8 (HOST_WIDE_INT_1U<<PROCESSOR_K8) +#define m_ATHLON (HOST_WIDE_INT_1U<<PROCESSOR_ATHLON) #define m_ATHLON_K8 (m_K8 | m_ATHLON) -#define m_AMDFAM10 (1U<<PROCESSOR_AMDFAM10) -#define m_BDVER1 (1U<<PROCESSOR_BDVER1) -#define m_BDVER2 (1U<<PROCESSOR_BDVER2) -#define m_BDVER3 (1U<<PROCESSOR_BDVER3) -#define m_BDVER4 (1U<<PROCESSOR_BDVER4) -#define m_ZNVER1 (1U<<PROCESSOR_ZNVER1) -#define m_BTVER1 (1U<<PROCESSOR_BTVER1) -#define m_BTVER2 (1U<<PROCESSOR_BTVER2) +#define m_AMDFAM10 (HOST_WIDE_INT_1U<<PROCESSOR_AMDFAM10) +#define m_BDVER1 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER1) +#define m_BDVER2 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER2) +#define m_BDVER3 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER3) +#define m_BDVER4 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER4) +#define m_ZNVER1 (HOST_WIDE_INT_1U<<PROCESSOR_ZNVER1) +#define m_BTVER1 (HOST_WIDE_INT_1U<<PROCESSOR_BTVER1) +#define m_BTVER2 (HOST_WIDE_INT_1U<<PROCESSOR_BTVER2) #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4) #define m_BTVER (m_BTVER1 | m_BTVER2) #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER \ | m_ZNVER1) -#define m_GENERIC (1U<<PROCESSOR_GENERIC) +#define m_GENERIC (HOST_WIDE_INT_1U<<PROCESSOR_GENERIC) const char* ix86_tune_feature_names[X86_TUNE_LAST] = { #undef DEF_TUNE @@ -182,7 +183,7 @@ unsigned char ix86_tune_features[X86_TUNE_LAST]; /* Feature tests against the various tunings used to create ix86_tune_features based on the processor mask. */ -static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = { +static unsigned long long initial_ix86_tune_features[X86_TUNE_LAST] = { #undef DEF_TUNE #define DEF_TUNE(tune, name, selector) selector, #include "x86-tune.def" @@ -194,7 +195,7 @@ unsigned char ix86_arch_features[X86_ARCH_LAST]; /* Feature tests against the various architecture variations, used to create ix86_arch_features based on the processor mask. */ -static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = { +static unsigned long long initial_ix86_arch_features[X86_ARCH_LAST] = { /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */ ~(m_386 | m_486 | m_PENT | m_LAKEMONT | m_K6), @@ -860,7 +861,8 @@ static const struct ptt processor_target_table[PROCESSOR_max] = {"knm", &slm_cost, 16, 15, 16, 7, 16}, {"skylake-avx512", &skylake_cost, 16, 10, 16, 10, 16}, {"cannonlake", &skylake_cost, 16, 10, 16, 10, 16}, - {"icelake", &skylake_cost, 16, 10, 16, 10, 16}, + {"icelake-client", &skylake_cost, 16, 10, 16, 10, 16}, + {"icelake-server", &skylake_cost, 16, 10, 16, 10, 16}, {"intel", &intel_cost, 16, 15, 16, 7, 16}, {"geode", &geode_cost, 0, 0, 0, 0, 0}, {"k6", &k6_cost, 32, 7, 32, 7, 32}, @@ -3445,6 +3447,8 @@ ix86_option_override_internal (bool main_args_p, const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4); const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5); const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6); + const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7); + const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8); const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR; @@ -3467,9 +3471,12 @@ ix86_option_override_internal (bool main_args_p, const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA; - const wide_int_bitmask PTA_ICELAKE = PTA_CANNONLAKE | PTA_AVX512VNNI + const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG | PTA_RDPID; + const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_CANNONLAKE | PTA_AVX512VNNI + | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG + | PTA_RDPID | PTA_PCONFIG | PTA_WBNOINVD; const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD; const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; @@ -3541,7 +3548,10 @@ ix86_option_override_internal (bool main_args_p, {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_SKYLAKE_AVX512}, {"cannonlake", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_CANNONLAKE}, - {"icelake", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_ICELAKE}, + {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL, + PTA_ICELAKE_CLIENT}, + {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL, + PTA_ICELAKE_SERVER}, {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL}, {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL}, {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT}, @@ -4150,6 +4160,12 @@ ix86_option_override_internal (bool main_args_p, if (((processor_alias_table[i].flags & PTA_RDPID) != 0) && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID)) opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID; + if (((processor_alias_table[i].flags & PTA_PCONFIG) != 0) + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_PCONFIG)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG; + if (((processor_alias_table[i].flags & PTA_WBNOINVD) != 0) + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_WBNOINVD)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD; if ((processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)) != 0) @@ -32376,8 +32392,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) break; case PROCESSOR_HASWELL: case PROCESSOR_SKYLAKE_AVX512: - if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_GFNI) - arg_str = "icelake"; + if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_WBNOINVD) + arg_str = "icelake-server"; + else if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_GFNI) + arg_str = "icelake-client"; else if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VBMI) arg_str = "cannonlake"; @@ -33105,7 +33123,8 @@ fold_builtin_cpu (tree fndecl, tree *args) M_INTEL_COREI7_SKYLAKE, M_INTEL_COREI7_SKYLAKE_AVX512, M_INTEL_COREI7_CANNONLAKE, - M_INTEL_COREI7_ICELAKE + M_INTEL_COREI7_ICELAKE_CLIENT, + M_INTEL_COREI7_ICELAKE_SERVER }; static struct _arch_names_table @@ -33130,7 +33149,8 @@ fold_builtin_cpu (tree fndecl, tree *args) {"skylake", M_INTEL_COREI7_SKYLAKE}, {"skylake-avx512", M_INTEL_COREI7_SKYLAKE_AVX512}, {"cannonlake", M_INTEL_COREI7_CANNONLAKE}, - {"icelake", M_INTEL_COREI7_ICELAKE}, + {"icelake-client", M_INTEL_COREI7_ICELAKE_CLIENT}, + {"icelake-server", M_INTEL_COREI7_ICELAKE_SERVER}, {"bonnell", M_INTEL_BONNELL}, {"silvermont", M_INTEL_SILVERMONT}, {"knl", M_INTEL_KNL}, diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index e43edd7..7f4b04f 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -387,7 +387,8 @@ extern const struct processor_costs ix86_size_cost; #define TARGET_KNM (ix86_tune == PROCESSOR_KNM) #define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512) #define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE) -#define TARGET_ICELAKE (ix86_tune == PROCESSOR_ICELAKE) +#define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT) +#define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER) #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) @@ -2268,7 +2269,8 @@ enum processor_type PROCESSOR_KNM, PROCESSOR_SKYLAKE_AVX512, PROCESSOR_CANNONLAKE, - PROCESSOR_ICELAKE, + PROCESSOR_ICELAKE_CLIENT, + PROCESSOR_ICELAKE_SERVER, PROCESSOR_INTEL, PROCESSOR_GEODE, PROCESSOR_K6, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 2492148..339604c 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -26552,14 +26552,23 @@ RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB and UMIP instruction set support. -@item Icelake -Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, +@item icelake-client +Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support. +@item icelake-server +Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, +SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, +XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, +AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, +AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG and WBNOINVD instruction +set support. + @item k6 AMD K6 CPU with MMX instruction set support. diff --git a/gcc/testsuite/g++.dg/ext/mv16.C b/gcc/testsuite/g++.dg/ext/mv16.C index 8fbdb47..3e7c228 100644 --- a/gcc/testsuite/g++.dg/ext/mv16.C +++ b/gcc/testsuite/g++.dg/ext/mv16.C @@ -60,10 +60,14 @@ int __attribute__ ((target("arch=cannonlake"))) foo () { return 16; } -int __attribute__ ((target("arch=icelake"))) foo () { +int __attribute__ ((target("arch=icelake-client"))) foo () { return 17; } +int __attribute__ ((target("arch=icelake-server"))) foo () { + return 18; +} + int main () { int val = foo (); @@ -86,8 +90,10 @@ int main () assert (val == 15); else if (__builtin_cpu_is ("cannonlake")) assert (val == 16); - else if (__builtin_cpu_is ("icelake")) + else if (__builtin_cpu_is ("icelake-client")) assert (val == 17); + else if (__builtin_cpu_is ("icelake-server")) + assert (val == 18); else assert (val == 0); diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc index 837cdc3..35b287a 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc @@ -145,7 +145,8 @@ extern void test_arch_knl (void) __attribute__((__target__("arch=knl"))); extern void test_arch_knm (void) __attribute__((__target__("arch=knm"))); extern void test_arch_skylake_avx512 (void) __attribute__((__target__("arch=skylake-avx512"))); extern void test_arch_cannonlake (void) __attribute__((__target__("arch=cannonlake"))); -extern void test_arch_icelake (void) __attribute__((__target__("arch=icelake"))); +extern void test_arch_icelake_client (void) __attribute__((__target__("arch=icelake-client"))); +extern void test_arch_icelake_server (void) __attribute__((__target__("arch=icelake-server"))); extern void test_arch_k8 (void) __attribute__((__target__("arch=k8"))); extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3"))); extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron"))); diff --git a/libgcc/config/i386/cpuinfo.h b/libgcc/config/i386/cpuinfo.h index a247072..17e2abf 100644 --- a/libgcc/config/i386/cpuinfo.h +++ b/libgcc/config/i386/cpuinfo.h @@ -70,7 +70,8 @@ enum processor_subtypes INTEL_COREI7_SKYLAKE, INTEL_COREI7_SKYLAKE_AVX512, INTEL_COREI7_CANNONLAKE, - INTEL_COREI7_ICELAKE, + INTEL_COREI7_ICELAKE_CLIENT, + INTEL_COREI7_ICELAKE_SERVER, CPU_SUBTYPE_MAX }; -- 2.5.5 ^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [patch][x86] Split-up march icelake on march=icelake-server and march=icelake-client 2018-03-13 7:42 ` Koval, Julia @ 2018-03-14 7:48 ` Koval, Julia 2018-03-14 9:10 ` Uros Bizjak 0 siblings, 1 reply; 5+ messages in thread From: Koval, Julia @ 2018-03-14 7:48 UTC (permalink / raw) To: 'GCC Patches'; +Cc: Joseph Myers, 'Uros Bizjak' [-- Attachment #1: Type: text/plain, Size: 3010 bytes --] Small fix. gcc/ * config.gcc (icelake-client, icelake-server): New. (icelake): Remove. * config/i386/i386.c (initial_ix86_tune_features): Extend to 64 bit. (initial_ix86_arch_features): Ditto. (PTA_SKYLAKE): Add SGX. (PTA_ICELAKE): Remove. (PTA_ICELAKE_CLIENT): New. (PTA_ICELAKE_SERVER): New. (ix86_option_override_internal): Split up icelake on icelake client and icelake server. (get_builtin_code_for_version): Ditto. (fold_builtin_cpu): Ditto. * config/i386/driver-i386.c (config/i386/driver-i386.c): Ditto. * config/i386/i386-c.c (ix86_target_macros_internal): Ditto * config/i386/i386.h (processor_type) Ditto. * doc/invoke.texi: Ditto. gcc/testsuite/ * g++.dg/ext/mv16.C: Split up icelake on icelake client and icelake-server. * gcc.target/i386/funcspec-56.inc: Ditto. libgcc/ * config/i386/cpuinfo.h (processor_subtypes): Split up icelake on icelake client and icelake-server. Thanks, Julia > -----Original Message----- > From: Koval, Julia > Sent: Tuesday, March 13, 2018 8:42 AM > To: Joseph Myers <joseph@codesourcery.com> > Cc: 'GCC Patches' <gcc-patches@gcc.gnu.org>; Uros Bizjak > <ubizjak@gmail.com> > Subject: RE: [patch][x86] Split-up march icelake on march=icelake-server and > march=icelake-client > > Fixed invoke.texi. Here is the new version. > > gcc/ > * config.gcc (icelake-client, icelake-server): New. > (icelake): Remove. > * config/i386/i386.c (initial_ix86_tune_features): Extend to 64 bit. > (initial_ix86_arch_features): Ditto. > (ix86_option_override_internal): Split up icelake on icelake client and > icelake server. > (get_builtin_code_for_version): Ditto. > (fold_builtin_cpu): Ditto. > * config/i386/driver-i386.c (config/i386/driver-i386.c): Ditto. > * config/i386/i386-c.c (ix86_target_macros_internal): Ditto > * config/i386/i386.h (processor_type) Ditto. > * doc/invoke.texi: Ditto. > > gcc/testsuite/ > * g++.dg/ext/mv16.C: Split up icelake on icelake client and > icelake-server. > * gcc.target/i386/funcspec-56.inc: Ditto. > > libgcc/ > * config/i386/cpuinfo.h (processor_subtypes): Split up icelake on icelake > client and icelake-server. > > Thanks, > Julia > > > -----Original Message----- > > From: Joseph Myers [mailto:joseph@codesourcery.com] > > Sent: Monday, March 12, 2018 10:21 PM > > To: Koval, Julia <julia.koval@intel.com> > > Cc: 'GCC Patches' <gcc-patches@gcc.gnu.org>; Uros Bizjak > > <ubizjak@gmail.com> > > Subject: Re: [patch][x86] Split-up march icelake on march=icelake-server and > > march=icelake-client > > > > On Mon, 12 Mar 2018, Koval, Julia wrote: > > > > > Hi, > > > This patch introduces separate client and server arch options instead of > > > -march=icelake. Ok for trunk? > > > > I don't see any invoke.texi updates here to document what these two > > options mean (including, presumably, different lists of features for > > them). > > > > -- > > Joseph S. Myers > > joseph@codesourcery.com [-- Attachment #2: 0001-icelake-client.patch --] [-- Type: application/octet-stream, Size: 18748 bytes --] From de082b1eac98696870ab274a8fef9fccf1744574 Mon Sep 17 00:00:00 2001 From: julia <jkoval@gkticlel801.igk.intel.com> Date: Mon, 12 Mar 2018 16:28:54 +0300 Subject: [PATCH] icelake-client --- gcc/config.gcc | 2 +- gcc/config/i386/driver-i386.c | 7 +- gcc/config/i386/i386-c.c | 17 ++-- gcc/config/i386/i386.c | 113 ++++++++++++++++---------- gcc/config/i386/i386.h | 6 +- gcc/doc/invoke.texi | 13 ++- gcc/testsuite/g++.dg/ext/mv16.C | 10 ++- gcc/testsuite/gcc.target/i386/funcspec-56.inc | 3 +- libgcc/config/i386/cpuinfo.h | 3 +- 9 files changed, 113 insertions(+), 61 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 81627d5..f7b2659 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -637,7 +637,7 @@ x86_64_archs="amdfam10 athlon64 athlon64-sse3 barcelona bdver1 bdver2 \ bdver3 bdver4 znver1 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \ core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \ sandybridge ivybridge haswell broadwell bonnell silvermont knl knm \ -skylake-avx512 cannonlake icelake x86-64 native" +skylake-avx512 cannonlake icelake-client icelake-server x86-64 native" # Additional x86 processors supported by --with-cpu=. Each processor # MUST be separated by exactly one space. diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index 8c95c2e..4f59854 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -825,9 +825,12 @@ const char *host_detect_local_cpu (int argc, const char **argv) if (arch) { /* This is unknown family 0x6 CPU. */ + /* Assume Ice Lake Server. */ + if (has_wbnoinvd) + cpu = "icelake-server"; /* Assume Ice Lake. */ - if (has_gfni) - cpu = "icelake"; + else if (has_gfni) + cpu = "icelake-client"; /* Assume Cannon Lake. */ else if (has_avx512vbmi) cpu = "cannonlake"; diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 644958a..6c50e20 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -190,9 +190,13 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__cannonlake"); def_or_undef (parse_in, "__cannonlake__"); break; - case PROCESSOR_ICELAKE: - def_or_undef (parse_in, "__icelake"); - def_or_undef (parse_in, "__icelake__"); + case PROCESSOR_ICELAKE_CLIENT: + def_or_undef (parse_in, "__icelake_client"); + def_or_undef (parse_in, "__icelake_client__"); + break; + case PROCESSOR_ICELAKE_SERVER: + def_or_undef (parse_in, "__icelake_server"); + def_or_undef (parse_in, "__icelake_server__"); break; /* use PROCESSOR_max to not set/unset the arch macro. */ case PROCESSOR_max: @@ -315,8 +319,11 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, case PROCESSOR_CANNONLAKE: def_or_undef (parse_in, "__tune_cannonlake__"); break; - case PROCESSOR_ICELAKE: - def_or_undef (parse_in, "__tune_icelake__"); + case PROCESSOR_ICELAKE_CLIENT: + def_or_undef (parse_in, "__tune_icelake_client__"); + break; + case PROCESSOR_ICELAKE_SERVER: + def_or_undef (parse_in, "__tune_icelake_server__"); break; case PROCESSOR_LAKEMONT: def_or_undef (parse_in, "__tune_lakemont__"); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index af24c6e..a87e5d5 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -127,48 +127,49 @@ const struct processor_costs *ix86_tune_cost = NULL; const struct processor_costs *ix86_cost = NULL; /* Processor feature/optimization bitmasks. */ -#define m_386 (1U<<PROCESSOR_I386) -#define m_486 (1U<<PROCESSOR_I486) -#define m_PENT (1U<<PROCESSOR_PENTIUM) -#define m_LAKEMONT (1U<<PROCESSOR_LAKEMONT) -#define m_PPRO (1U<<PROCESSOR_PENTIUMPRO) -#define m_PENT4 (1U<<PROCESSOR_PENTIUM4) -#define m_NOCONA (1U<<PROCESSOR_NOCONA) +#define m_386 (HOST_WIDE_INT_1U<<PROCESSOR_I386) +#define m_486 (HOST_WIDE_INT_1U<<PROCESSOR_I486) +#define m_PENT (HOST_WIDE_INT_1U<<PROCESSOR_PENTIUM) +#define m_LAKEMONT (HOST_WIDE_INT_1U<<PROCESSOR_LAKEMONT) +#define m_PPRO (HOST_WIDE_INT_1U<<PROCESSOR_PENTIUMPRO) +#define m_PENT4 (HOST_WIDE_INT_1U<<PROCESSOR_PENTIUM4) +#define m_NOCONA (HOST_WIDE_INT_1U<<PROCESSOR_NOCONA) #define m_P4_NOCONA (m_PENT4 | m_NOCONA) -#define m_CORE2 (1U<<PROCESSOR_CORE2) -#define m_NEHALEM (1U<<PROCESSOR_NEHALEM) -#define m_SANDYBRIDGE (1U<<PROCESSOR_SANDYBRIDGE) -#define m_HASWELL (1U<<PROCESSOR_HASWELL) +#define m_CORE2 (HOST_WIDE_INT_1U<<PROCESSOR_CORE2) +#define m_NEHALEM (HOST_WIDE_INT_1U<<PROCESSOR_NEHALEM) +#define m_SANDYBRIDGE (HOST_WIDE_INT_1U<<PROCESSOR_SANDYBRIDGE) +#define m_HASWELL (HOST_WIDE_INT_1U<<PROCESSOR_HASWELL) #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL) -#define m_BONNELL (1U<<PROCESSOR_BONNELL) -#define m_SILVERMONT (1U<<PROCESSOR_SILVERMONT) -#define m_KNL (1U<<PROCESSOR_KNL) -#define m_KNM (1U<<PROCESSOR_KNM) -#define m_SKYLAKE_AVX512 (1U<<PROCESSOR_SKYLAKE_AVX512) -#define m_CANNONLAKE (1U<<PROCESSOR_CANNONLAKE) -#define m_ICELAKE (1U<<PROCESSOR_ICELAKE) -#define m_INTEL (1U<<PROCESSOR_INTEL) - -#define m_GEODE (1U<<PROCESSOR_GEODE) -#define m_K6 (1U<<PROCESSOR_K6) +#define m_BONNELL (HOST_WIDE_INT_1U<<PROCESSOR_BONNELL) +#define m_SILVERMONT (HOST_WIDE_INT_1U<<PROCESSOR_SILVERMONT) +#define m_KNL (HOST_WIDE_INT_1U<<PROCESSOR_KNL) +#define m_KNM (HOST_WIDE_INT_1U<<PROCESSOR_KNM) +#define m_SKYLAKE_AVX512 (HOST_WIDE_INT_1U<<PROCESSOR_SKYLAKE_AVX512) +#define m_CANNONLAKE (HOST_WIDE_INT_1U<<PROCESSOR_CANNONLAKE) +#define m_ICELAKE_CLIENT (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_CLIENT) +#define m_ICELAKE_SERVER (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_SERVER) +#define m_INTEL (HOST_WIDE_INT_1U<<PROCESSOR_INTEL) + +#define m_GEODE (HOST_WIDE_INT_1U<<PROCESSOR_GEODE) +#define m_K6 (HOST_WIDE_INT_1U<<PROCESSOR_K6) #define m_K6_GEODE (m_K6 | m_GEODE) -#define m_K8 (1U<<PROCESSOR_K8) -#define m_ATHLON (1U<<PROCESSOR_ATHLON) +#define m_K8 (HOST_WIDE_INT_1U<<PROCESSOR_K8) +#define m_ATHLON (HOST_WIDE_INT_1U<<PROCESSOR_ATHLON) #define m_ATHLON_K8 (m_K8 | m_ATHLON) -#define m_AMDFAM10 (1U<<PROCESSOR_AMDFAM10) -#define m_BDVER1 (1U<<PROCESSOR_BDVER1) -#define m_BDVER2 (1U<<PROCESSOR_BDVER2) -#define m_BDVER3 (1U<<PROCESSOR_BDVER3) -#define m_BDVER4 (1U<<PROCESSOR_BDVER4) -#define m_ZNVER1 (1U<<PROCESSOR_ZNVER1) -#define m_BTVER1 (1U<<PROCESSOR_BTVER1) -#define m_BTVER2 (1U<<PROCESSOR_BTVER2) +#define m_AMDFAM10 (HOST_WIDE_INT_1U<<PROCESSOR_AMDFAM10) +#define m_BDVER1 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER1) +#define m_BDVER2 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER2) +#define m_BDVER3 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER3) +#define m_BDVER4 (HOST_WIDE_INT_1U<<PROCESSOR_BDVER4) +#define m_ZNVER1 (HOST_WIDE_INT_1U<<PROCESSOR_ZNVER1) +#define m_BTVER1 (HOST_WIDE_INT_1U<<PROCESSOR_BTVER1) +#define m_BTVER2 (HOST_WIDE_INT_1U<<PROCESSOR_BTVER2) #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4) #define m_BTVER (m_BTVER1 | m_BTVER2) #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER \ | m_ZNVER1) -#define m_GENERIC (1U<<PROCESSOR_GENERIC) +#define m_GENERIC (HOST_WIDE_INT_1U<<PROCESSOR_GENERIC) const char* ix86_tune_feature_names[X86_TUNE_LAST] = { #undef DEF_TUNE @@ -182,7 +183,7 @@ unsigned char ix86_tune_features[X86_TUNE_LAST]; /* Feature tests against the various tunings used to create ix86_tune_features based on the processor mask. */ -static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = { +static unsigned long long initial_ix86_tune_features[X86_TUNE_LAST] = { #undef DEF_TUNE #define DEF_TUNE(tune, name, selector) selector, #include "x86-tune.def" @@ -194,7 +195,7 @@ unsigned char ix86_arch_features[X86_ARCH_LAST]; /* Feature tests against the various architecture variations, used to create ix86_arch_features based on the processor mask. */ -static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = { +static unsigned long long initial_ix86_arch_features[X86_ARCH_LAST] = { /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */ ~(m_386 | m_486 | m_PENT | m_LAKEMONT | m_K6), @@ -860,7 +861,8 @@ static const struct ptt processor_target_table[PROCESSOR_max] = {"knm", &slm_cost, 16, 15, 16, 7, 16}, {"skylake-avx512", &skylake_cost, 16, 10, 16, 10, 16}, {"cannonlake", &skylake_cost, 16, 10, 16, 10, 16}, - {"icelake", &skylake_cost, 16, 10, 16, 10, 16}, + {"icelake-client", &skylake_cost, 16, 10, 16, 10, 16}, + {"icelake-server", &skylake_cost, 16, 10, 16, 10, 16}, {"intel", &intel_cost, 16, 15, 16, 7, 16}, {"geode", &geode_cost, 0, 0, 0, 0, 0}, {"k6", &k6_cost, 32, 7, 32, 7, 32}, @@ -3445,6 +3447,8 @@ ix86_option_override_internal (bool main_args_p, const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4); const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5); const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6); + const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7); + const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8); const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR; @@ -3460,16 +3464,18 @@ ix86_option_override_internal (bool main_args_p, const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED; const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT - | PTA_XSAVEC | PTA_XSAVES; + | PTA_XSAVEC | PTA_XSAVES | PTA_SGX; const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | PTA_CLWB; const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA; - const wide_int_bitmask PTA_ICELAKE = PTA_CANNONLAKE | PTA_AVX512VNNI + const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG - | PTA_RDPID; + | PTA_RDPID | PTA_CLWB; + const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG + | PTA_WBNOINVD; const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD; const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; @@ -3541,7 +3547,10 @@ ix86_option_override_internal (bool main_args_p, {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_SKYLAKE_AVX512}, {"cannonlake", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_CANNONLAKE}, - {"icelake", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_ICELAKE}, + {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL, + PTA_ICELAKE_CLIENT}, + {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL, + PTA_ICELAKE_SERVER}, {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL}, {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL}, {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT}, @@ -4150,6 +4159,12 @@ ix86_option_override_internal (bool main_args_p, if (((processor_alias_table[i].flags & PTA_RDPID) != 0) && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID)) opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID; + if (((processor_alias_table[i].flags & PTA_PCONFIG) != 0) + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_PCONFIG)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG; + if (((processor_alias_table[i].flags & PTA_WBNOINVD) != 0) + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_WBNOINVD)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD; if ((processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)) != 0) @@ -32376,9 +32391,7 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) break; case PROCESSOR_HASWELL: case PROCESSOR_SKYLAKE_AVX512: - if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_GFNI) - arg_str = "icelake"; - else if (new_target->x_ix86_isa_flags + if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VBMI) arg_str = "cannonlake"; else if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VL) @@ -32391,6 +32404,14 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) arg_str = "haswell"; priority = P_PROC_AVX2; break; + case PROCESSOR_ICELAKE_CLIENT: + arg_str = "icelake-client"; + priority = P_PROC_AVX2; + break; + case PROCESSOR_ICELAKE_SERVER: + arg_str = "icelake-server"; + priority = P_PROC_AVX2; + break; case PROCESSOR_BONNELL: arg_str = "bonnell"; priority = P_PROC_SSSE3; @@ -33105,7 +33126,8 @@ fold_builtin_cpu (tree fndecl, tree *args) M_INTEL_COREI7_SKYLAKE, M_INTEL_COREI7_SKYLAKE_AVX512, M_INTEL_COREI7_CANNONLAKE, - M_INTEL_COREI7_ICELAKE + M_INTEL_COREI7_ICELAKE_CLIENT, + M_INTEL_COREI7_ICELAKE_SERVER }; static struct _arch_names_table @@ -33130,7 +33152,8 @@ fold_builtin_cpu (tree fndecl, tree *args) {"skylake", M_INTEL_COREI7_SKYLAKE}, {"skylake-avx512", M_INTEL_COREI7_SKYLAKE_AVX512}, {"cannonlake", M_INTEL_COREI7_CANNONLAKE}, - {"icelake", M_INTEL_COREI7_ICELAKE}, + {"icelake-client", M_INTEL_COREI7_ICELAKE_CLIENT}, + {"icelake-server", M_INTEL_COREI7_ICELAKE_SERVER}, {"bonnell", M_INTEL_BONNELL}, {"silvermont", M_INTEL_SILVERMONT}, {"knl", M_INTEL_KNL}, diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index e43edd7..7f4b04f 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -387,7 +387,8 @@ extern const struct processor_costs ix86_size_cost; #define TARGET_KNM (ix86_tune == PROCESSOR_KNM) #define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512) #define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE) -#define TARGET_ICELAKE (ix86_tune == PROCESSOR_ICELAKE) +#define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT) +#define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER) #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) @@ -2268,7 +2269,8 @@ enum processor_type PROCESSOR_KNM, PROCESSOR_SKYLAKE_AVX512, PROCESSOR_CANNONLAKE, - PROCESSOR_ICELAKE, + PROCESSOR_ICELAKE_CLIENT, + PROCESSOR_ICELAKE_SERVER, PROCESSOR_INTEL, PROCESSOR_GEODE, PROCESSOR_K6, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 2492148..339604c 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -26552,14 +26552,23 @@ RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB and UMIP instruction set support. -@item Icelake -Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, +@item icelake-client +Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support. +@item icelake-server +Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, +SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, +XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, +AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, +AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES, PCONFIG and WBNOINVD instruction +set support. + @item k6 AMD K6 CPU with MMX instruction set support. diff --git a/gcc/testsuite/g++.dg/ext/mv16.C b/gcc/testsuite/g++.dg/ext/mv16.C index 8fbdb47..3e7c228 100644 --- a/gcc/testsuite/g++.dg/ext/mv16.C +++ b/gcc/testsuite/g++.dg/ext/mv16.C @@ -60,10 +60,14 @@ int __attribute__ ((target("arch=cannonlake"))) foo () { return 16; } -int __attribute__ ((target("arch=icelake"))) foo () { +int __attribute__ ((target("arch=icelake-client"))) foo () { return 17; } +int __attribute__ ((target("arch=icelake-server"))) foo () { + return 18; +} + int main () { int val = foo (); @@ -86,8 +90,10 @@ int main () assert (val == 15); else if (__builtin_cpu_is ("cannonlake")) assert (val == 16); - else if (__builtin_cpu_is ("icelake")) + else if (__builtin_cpu_is ("icelake-client")) assert (val == 17); + else if (__builtin_cpu_is ("icelake-server")) + assert (val == 18); else assert (val == 0); diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc index 837cdc3..35b287a 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc @@ -145,7 +145,8 @@ extern void test_arch_knl (void) __attribute__((__target__("arch=knl"))); extern void test_arch_knm (void) __attribute__((__target__("arch=knm"))); extern void test_arch_skylake_avx512 (void) __attribute__((__target__("arch=skylake-avx512"))); extern void test_arch_cannonlake (void) __attribute__((__target__("arch=cannonlake"))); -extern void test_arch_icelake (void) __attribute__((__target__("arch=icelake"))); +extern void test_arch_icelake_client (void) __attribute__((__target__("arch=icelake-client"))); +extern void test_arch_icelake_server (void) __attribute__((__target__("arch=icelake-server"))); extern void test_arch_k8 (void) __attribute__((__target__("arch=k8"))); extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3"))); extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron"))); diff --git a/libgcc/config/i386/cpuinfo.h b/libgcc/config/i386/cpuinfo.h index a247072..17e2abf 100644 --- a/libgcc/config/i386/cpuinfo.h +++ b/libgcc/config/i386/cpuinfo.h @@ -70,7 +70,8 @@ enum processor_subtypes INTEL_COREI7_SKYLAKE, INTEL_COREI7_SKYLAKE_AVX512, INTEL_COREI7_CANNONLAKE, - INTEL_COREI7_ICELAKE, + INTEL_COREI7_ICELAKE_CLIENT, + INTEL_COREI7_ICELAKE_SERVER, CPU_SUBTYPE_MAX }; -- 2.5.5 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [patch][x86] Split-up march icelake on march=icelake-server and march=icelake-client 2018-03-14 7:48 ` Koval, Julia @ 2018-03-14 9:10 ` Uros Bizjak 0 siblings, 0 replies; 5+ messages in thread From: Uros Bizjak @ 2018-03-14 9:10 UTC (permalink / raw) To: Koval, Julia; +Cc: GCC Patches, Joseph Myers On Wed, Mar 14, 2018 at 8:44 AM, Koval, Julia <julia.koval@intel.com> wrote: > Small fix. > > gcc/ > * config.gcc (icelake-client, icelake-server): New. > (icelake): Remove. > * config/i386/i386.c (initial_ix86_tune_features): Extend to 64 bit. > (initial_ix86_arch_features): Ditto. > (PTA_SKYLAKE): Add SGX. > (PTA_ICELAKE): Remove. > (PTA_ICELAKE_CLIENT): New. > (PTA_ICELAKE_SERVER): New. > (ix86_option_override_internal): Split up icelake on icelake client and > icelake server. > (get_builtin_code_for_version): Ditto. > (fold_builtin_cpu): Ditto. > * config/i386/driver-i386.c (config/i386/driver-i386.c): Ditto. > * config/i386/i386-c.c (ix86_target_macros_internal): Ditto > * config/i386/i386.h (processor_type) Ditto. > * doc/invoke.texi: Ditto. > > gcc/testsuite/ > * g++.dg/ext/mv16.C: Split up icelake on icelake client and > icelake-server. > * gcc.target/i386/funcspec-56.inc: Ditto. > > libgcc/ > * config/i386/cpuinfo.h (processor_subtypes): Split up icelake on icelake > client and icelake-server. OK. Thanks, Uros. > Thanks, > Julia > >> -----Original Message----- >> From: Koval, Julia >> Sent: Tuesday, March 13, 2018 8:42 AM >> To: Joseph Myers <joseph@codesourcery.com> >> Cc: 'GCC Patches' <gcc-patches@gcc.gnu.org>; Uros Bizjak >> <ubizjak@gmail.com> >> Subject: RE: [patch][x86] Split-up march icelake on march=icelake-server and >> march=icelake-client >> >> Fixed invoke.texi. Here is the new version. >> >> gcc/ >> * config.gcc (icelake-client, icelake-server): New. >> (icelake): Remove. >> * config/i386/i386.c (initial_ix86_tune_features): Extend to 64 bit. >> (initial_ix86_arch_features): Ditto. >> (ix86_option_override_internal): Split up icelake on icelake client and >> icelake server. >> (get_builtin_code_for_version): Ditto. >> (fold_builtin_cpu): Ditto. >> * config/i386/driver-i386.c (config/i386/driver-i386.c): Ditto. >> * config/i386/i386-c.c (ix86_target_macros_internal): Ditto >> * config/i386/i386.h (processor_type) Ditto. >> * doc/invoke.texi: Ditto. >> >> gcc/testsuite/ >> * g++.dg/ext/mv16.C: Split up icelake on icelake client and >> icelake-server. >> * gcc.target/i386/funcspec-56.inc: Ditto. >> >> libgcc/ >> * config/i386/cpuinfo.h (processor_subtypes): Split up icelake on icelake >> client and icelake-server. >> >> Thanks, >> Julia >> >> > -----Original Message----- >> > From: Joseph Myers [mailto:joseph@codesourcery.com] >> > Sent: Monday, March 12, 2018 10:21 PM >> > To: Koval, Julia <julia.koval@intel.com> >> > Cc: 'GCC Patches' <gcc-patches@gcc.gnu.org>; Uros Bizjak >> > <ubizjak@gmail.com> >> > Subject: Re: [patch][x86] Split-up march icelake on march=icelake-server and >> > march=icelake-client >> > >> > On Mon, 12 Mar 2018, Koval, Julia wrote: >> > >> > > Hi, >> > > This patch introduces separate client and server arch options instead of >> > > -march=icelake. Ok for trunk? >> > >> > I don't see any invoke.texi updates here to document what these two >> > options mean (including, presumably, different lists of features for >> > them). >> > >> > -- >> > Joseph S. Myers >> > joseph@codesourcery.com ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-03-14 8:47 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-03-12 20:47 [patch][x86] Split-up march icelake on march=icelake-server and march=icelake-client Koval, Julia 2018-03-12 21:20 ` Joseph Myers 2018-03-13 7:42 ` Koval, Julia 2018-03-14 7:48 ` Koval, Julia 2018-03-14 9:10 ` Uros Bizjak
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