* [cxx-mem-model] Handle x86-64 with -m32
@ 2011-10-20 21:50 Aldy Hernandez
2011-10-21 1:31 ` Joseph S. Myers
0 siblings, 1 reply; 12+ messages in thread
From: Aldy Hernandez @ 2011-10-20 21:50 UTC (permalink / raw)
To: Andrew MacLeod, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 324 bytes --]
These operations don't exist on x86-32 bits, and when running multilibed
tests, the target is still x86_64-unknown-linux-gnu but the target is
32-bits when using -m32.
The following change checks that we are actually running in 64-bits
before assuming sync_int_128 or sync_long_long exist on the target.
OK for branch?
[-- Attachment #2: curr --]
[-- Type: text/plain, Size: 1068 bytes --]
* lib/target-supports.exp (check_effective_target_sync_int_128):
Only set when running in 64-bit mode.
(check_effective_target_sync_long_long): Same.
Index: lib/target-supports.exp
===================================================================
--- lib/target-supports.exp (revision 180156)
+++ lib/target-supports.exp (working copy)
@@ -3456,7 +3456,7 @@ proc check_effective_target_sync_int_128
verbose "check_effective_target_sync_int_128: using cached result" 2
} else {
set et_sync_int_128_saved 0
- if { [istarget x86_64-*-*] } {
+ if { [istarget x86_64-*-*] && [is-effective-target lp64] } {
set et_sync_int_128_saved 1
}
}
@@ -3474,7 +3474,7 @@ proc check_effective_target_sync_long_lo
verbose "check_effective_target_sync_long_long: using cached result" 2
} else {
set et_sync_long_long_saved 0
- if { [istarget x86_64-*-*] } {
+ if { [istarget x86_64-*-*] && [is-effective-target lp64] } {
set et_sync_long_long_saved 1
}
}
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [cxx-mem-model] Handle x86-64 with -m32
2011-10-20 21:50 [cxx-mem-model] Handle x86-64 with -m32 Aldy Hernandez
@ 2011-10-21 1:31 ` Joseph S. Myers
2011-10-21 2:17 ` H.J. Lu
0 siblings, 1 reply; 12+ messages in thread
From: Joseph S. Myers @ 2011-10-21 1:31 UTC (permalink / raw)
To: Aldy Hernandez; +Cc: Andrew MacLeod, gcc-patches
On Thu, 20 Oct 2011, Aldy Hernandez wrote:
> These operations don't exist on x86-32 bits, and when running multilibed
> tests, the target is still x86_64-unknown-linux-gnu but the target is 32-bits
> when using -m32.
Any test that only handles one of x86_64-* and i?86-* is automatically
wrong; you can use -m64 with i?86-* targets. You always need to handle
both together.
Do these operations exist for x32 as well as for -m64? If they do, then
lp64 isn't the right test either; if not, then it is.
--
Joseph S. Myers
joseph@codesourcery.com
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [cxx-mem-model] Handle x86-64 with -m32
2011-10-21 1:31 ` Joseph S. Myers
@ 2011-10-21 2:17 ` H.J. Lu
2011-10-21 12:37 ` Andrew MacLeod
0 siblings, 1 reply; 12+ messages in thread
From: H.J. Lu @ 2011-10-21 2:17 UTC (permalink / raw)
To: Joseph S. Myers; +Cc: Aldy Hernandez, Andrew MacLeod, gcc-patches
On Thu, Oct 20, 2011 at 3:38 PM, Joseph S. Myers
<joseph@codesourcery.com> wrote:
> On Thu, 20 Oct 2011, Aldy Hernandez wrote:
>
>> These operations don't exist on x86-32 bits, and when running multilibed
>> tests, the target is still x86_64-unknown-linux-gnu but the target is 32-bits
>> when using -m32.
>
> Any test that only handles one of x86_64-* and i?86-* is automatically
> wrong; you can use -m64 with i?86-* targets. You always need to handle
> both together.
>
> Do these operations exist for x32 as well as for -m64? If they do, then
> lp64 isn't the right test either; if not, then it is.
>
X32 has native int64 and int128.
--
H.J.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [cxx-mem-model] Handle x86-64 with -m32
2011-10-21 2:17 ` H.J. Lu
@ 2011-10-21 12:37 ` Andrew MacLeod
2011-10-21 16:09 ` H.J. Lu
0 siblings, 1 reply; 12+ messages in thread
From: Andrew MacLeod @ 2011-10-21 12:37 UTC (permalink / raw)
To: H.J. Lu; +Cc: Joseph S. Myers, Aldy Hernandez, gcc-patches
On 10/20/2011 06:50 PM, H.J. Lu wrote:
> On Thu, Oct 20, 2011 at 3:38 PM, Joseph S. Myers
> <joseph@codesourcery.com> wrote:
>>
>> Do these operations exist for x32 as well as for -m64? If they do, then
>> lp64 isn't the right test either; if not, then it is.
>>
> X32 has native int64 and int128.
>
I presume there is no atomic support for int128 though, and thats what
'condition check_effective_target_sync_int_128' is testing for.
Andrew
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [cxx-mem-model] Handle x86-64 with -m32
2011-10-21 12:37 ` Andrew MacLeod
@ 2011-10-21 16:09 ` H.J. Lu
2011-10-21 16:48 ` Andrew MacLeod
0 siblings, 1 reply; 12+ messages in thread
From: H.J. Lu @ 2011-10-21 16:09 UTC (permalink / raw)
To: Andrew MacLeod; +Cc: Joseph S. Myers, Aldy Hernandez, gcc-patches
On Fri, Oct 21, 2011 at 5:11 AM, Andrew MacLeod <amacleod@redhat.com> wrote:
> On 10/20/2011 06:50 PM, H.J. Lu wrote:
>>
>> On Thu, Oct 20, 2011 at 3:38 PM, Joseph S. Myers
>> <joseph@codesourcery.com> wrote:
>>>
>>> Do these operations exist for x32 as well as for -m64? If they do, then
>>> lp64 isn't the right test either; if not, then it is.
>>>
>> X32 has native int64 and int128.
>>
> I presume there is no atomic support for int128 though, and thats what
> 'condition check_effective_target_sync_int_128' is testing for.
>
X32 uses x86-64 instruction set with 32bit pointers. It has the same
atomic support as x86-64 and has atomic support for int128.
--
H.J.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [cxx-mem-model] Handle x86-64 with -m32
2011-10-21 16:09 ` H.J. Lu
@ 2011-10-21 16:48 ` Andrew MacLeod
2011-10-21 17:06 ` H.J. Lu
2011-10-21 18:17 ` Aldy Hernandez
0 siblings, 2 replies; 12+ messages in thread
From: Andrew MacLeod @ 2011-10-21 16:48 UTC (permalink / raw)
To: H.J. Lu; +Cc: Joseph S. Myers, Aldy Hernandez, gcc-patches
On 10/21/2011 11:28 AM, H.J. Lu wrote:
> On Fri, Oct 21, 2011 at 5:11 AM, Andrew MacLeod<amacleod@redhat.com> wrote:
>>>
>>> X32 has native int64 and int128.
>>>
>> I presume there is no atomic support for int128 though, and thats what
>> 'condition check_effective_target_sync_int_128' is testing for.
>>
> X32 uses x86-64 instruction set with 32bit pointers. It has the same
> atomic support as x86-64 and has atomic support for int128.
Oh, you aren't talking about 32 bit, but a 32 bit abi on a 64 bit machine.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [cxx-mem-model] Handle x86-64 with -m32
2011-10-21 16:48 ` Andrew MacLeod
@ 2011-10-21 17:06 ` H.J. Lu
2011-10-21 18:17 ` Aldy Hernandez
1 sibling, 0 replies; 12+ messages in thread
From: H.J. Lu @ 2011-10-21 17:06 UTC (permalink / raw)
To: Andrew MacLeod; +Cc: Joseph S. Myers, Aldy Hernandez, gcc-patches
On Fri, Oct 21, 2011 at 9:08 AM, Andrew MacLeod <amacleod@redhat.com> wrote:
> On 10/21/2011 11:28 AM, H.J. Lu wrote:
>>
>> On Fri, Oct 21, 2011 at 5:11 AM, Andrew MacLeod<amacleod@redhat.com>
>> wrote:
>>>>
>>>> X32 has native int64 and int128.
>>>>
>>> I presume there is no atomic support for int128 though, and thats what
>>> 'condition check_effective_target_sync_int_128' is testing for.
>>>
>> X32 uses x86-64 instruction set with 32bit pointers. It has the same
>> atomic support as x86-64 and has atomic support for int128.
>
> Oh, you aren't talking about 32 bit, but a 32 bit abi on a 64 bit machine.
>
Yes.
--
H.J.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [cxx-mem-model] Handle x86-64 with -m32
2011-10-21 16:48 ` Andrew MacLeod
2011-10-21 17:06 ` H.J. Lu
@ 2011-10-21 18:17 ` Aldy Hernandez
2011-10-21 21:28 ` Joseph S. Myers
1 sibling, 1 reply; 12+ messages in thread
From: Aldy Hernandez @ 2011-10-21 18:17 UTC (permalink / raw)
To: Andrew MacLeod; +Cc: H.J. Lu, Joseph S. Myers, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 732 bytes --]
On 10/21/11 11:08, Andrew MacLeod wrote:
> On 10/21/2011 11:28 AM, H.J. Lu wrote:
>> On Fri, Oct 21, 2011 at 5:11 AM, Andrew MacLeod<amacleod@redhat.com>
>> wrote:
>>>>
>>>> X32 has native int64 and int128.
>>>>
>>> I presume there is no atomic support for int128 though, and thats what
>>> 'condition check_effective_target_sync_int_128' is testing for.
>>>
>> X32 uses x86-64 instruction set with 32bit pointers. It has the same
>> atomic support as x86-64 and has atomic support for int128.
>
> Oh, you aren't talking about 32 bit, but a 32 bit abi on a 64 bit machine.
Thanks for pointing this out Joseph.
The following patch handles both x86_64 and i?86, but only returns true
for LP64. Is this what you had in mind?
Aldy
[-- Attachment #2: curr --]
[-- Type: text/plain, Size: 2311 bytes --]
* lib/target-supports.exp (check_effective_target_sync_int_128):
Handle both 32-bit and 64-bit triplets on x86.
(check_effective_target_sync_long_long): Same.
* gcc.dg/simulate-thread/atomic-load-int128.c: Handle i?86-*-*.
* gcc.dg/simulate-thread/atomic-other-int128.c: Same.
Index: lib/target-supports.exp
===================================================================
--- lib/target-supports.exp (revision 180156)
+++ lib/target-supports.exp (working copy)
@@ -3456,7 +3456,8 @@ proc check_effective_target_sync_int_128
verbose "check_effective_target_sync_int_128: using cached result" 2
} else {
set et_sync_int_128_saved 0
- if { [istarget x86_64-*-*] } {
+ if { ([istarget x86_64-*-*] || [istarget i?86-*-*])
+ && [is-effective-target lp64] } {
set et_sync_int_128_saved 1
}
}
@@ -3474,7 +3475,8 @@ proc check_effective_target_sync_long_lo
verbose "check_effective_target_sync_long_long: using cached result" 2
} else {
set et_sync_long_long_saved 0
- if { [istarget x86_64-*-*] } {
+ if { ([istarget x86_64-*-*] || [istarget i?86-*-*])
+ && [is-effective-target lp64] } {
set et_sync_long_long_saved 1
}
}
Index: gcc.dg/simulate-thread/atomic-load-int128.c
===================================================================
--- gcc.dg/simulate-thread/atomic-load-int128.c (revision 180156)
+++ gcc.dg/simulate-thread/atomic-load-int128.c (working copy)
@@ -1,6 +1,6 @@
/* { dg-do link } */
/* { dg-require-effective-target sync_int_128 } */
-/* { dg-options "-mcx16" { target { x86_64-*-* } } } */
+/* { dg-options "-mcx16" { target { x86_64-*-* i?86-*-* } } } */
/* { dg-final { simulate-thread } } */
#include <stdio.h>
Index: gcc.dg/simulate-thread/atomic-other-int128.c
===================================================================
--- gcc.dg/simulate-thread/atomic-other-int128.c (revision 180156)
+++ gcc.dg/simulate-thread/atomic-other-int128.c (working copy)
@@ -1,6 +1,6 @@
/* { dg-do link } */
/* { dg-require-effective-target sync_int_128 } */
-/* { dg-options "-mcx16" { target { x86_64-*-* } } } */
+/* { dg-options "-mcx16" { target { x86_64-*-* i?86-*-*] } } } */
/* { dg-final { simulate-thread } } */
#include <stdio.h>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [cxx-mem-model] Handle x86-64 with -m32
2011-10-21 18:17 ` Aldy Hernandez
@ 2011-10-21 21:28 ` Joseph S. Myers
2011-10-24 15:48 ` Aldy Hernandez
0 siblings, 1 reply; 12+ messages in thread
From: Joseph S. Myers @ 2011-10-21 21:28 UTC (permalink / raw)
To: Aldy Hernandez; +Cc: Andrew MacLeod, H.J. Lu, gcc-patches
On Fri, 21 Oct 2011, Aldy Hernandez wrote:
> > > X32 uses x86-64 instruction set with 32bit pointers. It has the same
> > > atomic support as x86-64 and has atomic support for int128.
> >
> > Oh, you aren't talking about 32 bit, but a 32 bit abi on a 64 bit machine.
>
> Thanks for pointing this out Joseph.
>
> The following patch handles both x86_64 and i?86, but only returns true for
> LP64. Is this what you had in mind?
My understanding from the x32 discussion is that the relevant condition is
"using 64-bit instructions", not "using an LP64 ABI". That might be "!
ia32" in effective-target terms.
--
Joseph S. Myers
joseph@codesourcery.com
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [cxx-mem-model] Handle x86-64 with -m32
2011-10-21 21:28 ` Joseph S. Myers
@ 2011-10-24 15:48 ` Aldy Hernandez
2011-10-24 16:12 ` H.J. Lu
0 siblings, 1 reply; 12+ messages in thread
From: Aldy Hernandez @ 2011-10-24 15:48 UTC (permalink / raw)
To: Joseph S. Myers; +Cc: Andrew MacLeod, H.J. Lu, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 700 bytes --]
On 10/21/11 15:46, Joseph S. Myers wrote:
> On Fri, 21 Oct 2011, Aldy Hernandez wrote:
>
>>>> X32 uses x86-64 instruction set with 32bit pointers. It has the same
>>>> atomic support as x86-64 and has atomic support for int128.
>>>
>>> Oh, you aren't talking about 32 bit, but a 32 bit abi on a 64 bit machine.
>>
>> Thanks for pointing this out Joseph.
>>
>> The following patch handles both x86_64 and i?86, but only returns true for
>> LP64. Is this what you had in mind?
>
> My understanding from the x32 discussion is that the relevant condition is
> "using 64-bit instructions", not "using an LP64 ABI". That might be "!
> ia32" in effective-target terms.
This works for me. Do you agree?
[-- Attachment #2: curr --]
[-- Type: text/plain, Size: 2313 bytes --]
* lib/target-supports.exp (check_effective_target_sync_int_128):
Handle both 32-bit and 64-bit triplets on x86.
(check_effective_target_sync_long_long): Same.
* gcc.dg/simulate-thread/atomic-load-int128.c: Handle i?86-*-*.
* gcc.dg/simulate-thread/atomic-other-int128.c: Same.
Index: lib/target-supports.exp
===================================================================
--- lib/target-supports.exp (revision 180156)
+++ lib/target-supports.exp (working copy)
@@ -3456,7 +3456,8 @@ proc check_effective_target_sync_int_128
verbose "check_effective_target_sync_int_128: using cached result" 2
} else {
set et_sync_int_128_saved 0
- if { [istarget x86_64-*-*] } {
+ if { ([istarget x86_64-*-*] || [istarget i?86-*-*])
+ && ![is-effective-target ia32] } {
set et_sync_int_128_saved 1
}
}
@@ -3474,7 +3475,8 @@ proc check_effective_target_sync_long_lo
verbose "check_effective_target_sync_long_long: using cached result" 2
} else {
set et_sync_long_long_saved 0
- if { [istarget x86_64-*-*] } {
+ if { ([istarget x86_64-*-*] || [istarget i?86-*-*])
+ && ![is-effective-target ia32] } {
set et_sync_long_long_saved 1
}
}
Index: gcc.dg/simulate-thread/atomic-load-int128.c
===================================================================
--- gcc.dg/simulate-thread/atomic-load-int128.c (revision 180156)
+++ gcc.dg/simulate-thread/atomic-load-int128.c (working copy)
@@ -1,6 +1,6 @@
/* { dg-do link } */
/* { dg-require-effective-target sync_int_128 } */
-/* { dg-options "-mcx16" { target { x86_64-*-* } } } */
+/* { dg-options "-mcx16" { target { x86_64-*-* i?86-*-* } } } */
/* { dg-final { simulate-thread } } */
#include <stdio.h>
Index: gcc.dg/simulate-thread/atomic-other-int128.c
===================================================================
--- gcc.dg/simulate-thread/atomic-other-int128.c (revision 180156)
+++ gcc.dg/simulate-thread/atomic-other-int128.c (working copy)
@@ -1,6 +1,6 @@
/* { dg-do link } */
/* { dg-require-effective-target sync_int_128 } */
-/* { dg-options "-mcx16" { target { x86_64-*-* } } } */
+/* { dg-options "-mcx16" { target { x86_64-*-* i?86-*-*] } } } */
/* { dg-final { simulate-thread } } */
#include <stdio.h>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [cxx-mem-model] Handle x86-64 with -m32
2011-10-24 15:48 ` Aldy Hernandez
@ 2011-10-24 16:12 ` H.J. Lu
2011-10-24 16:28 ` Aldy Hernandez
0 siblings, 1 reply; 12+ messages in thread
From: H.J. Lu @ 2011-10-24 16:12 UTC (permalink / raw)
To: Aldy Hernandez; +Cc: Joseph S. Myers, Andrew MacLeod, gcc-patches
On Mon, Oct 24, 2011 at 8:31 AM, Aldy Hernandez <aldyh@redhat.com> wrote:
> On 10/21/11 15:46, Joseph S. Myers wrote:
>>
>> On Fri, 21 Oct 2011, Aldy Hernandez wrote:
>>
>>>>> X32 uses x86-64 instruction set with 32bit pointers. It has the same
>>>>> atomic support as x86-64 and has atomic support for int128.
>>>>
>>>> Oh, you aren't talking about 32 bit, but a 32 bit abi on a 64 bit
>>>> machine.
>>>
>>> Thanks for pointing this out Joseph.
>>>
>>> The following patch handles both x86_64 and i?86, but only returns true
>>> for
>>> LP64. Is this what you had in mind?
>>
>> My understanding from the x32 discussion is that the relevant condition is
>> "using 64-bit instructions", not "using an LP64 ABI". That might be "!
>> ia32" in effective-target terms.
>
>
> This works for me. Do you agree?
>
It looks good to me.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [cxx-mem-model] Handle x86-64 with -m32
2011-10-24 16:12 ` H.J. Lu
@ 2011-10-24 16:28 ` Aldy Hernandez
0 siblings, 0 replies; 12+ messages in thread
From: Aldy Hernandez @ 2011-10-24 16:28 UTC (permalink / raw)
To: H.J. Lu; +Cc: Joseph S. Myers, Andrew MacLeod, gcc-patches
>> This works for me. Do you agree?
>>
>
> It looks good to me.
OK, will commit.
Thanks guys.
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2011-10-24 15:41 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-10-20 21:50 [cxx-mem-model] Handle x86-64 with -m32 Aldy Hernandez
2011-10-21 1:31 ` Joseph S. Myers
2011-10-21 2:17 ` H.J. Lu
2011-10-21 12:37 ` Andrew MacLeod
2011-10-21 16:09 ` H.J. Lu
2011-10-21 16:48 ` Andrew MacLeod
2011-10-21 17:06 ` H.J. Lu
2011-10-21 18:17 ` Aldy Hernandez
2011-10-21 21:28 ` Joseph S. Myers
2011-10-24 15:48 ` Aldy Hernandez
2011-10-24 16:12 ` H.J. Lu
2011-10-24 16:28 ` Aldy Hernandez
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