Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

["juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>]

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>> Why remove this? I saw this change was introduced in v3?

The "@" was introduced by this patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630184.html 
At the first time, I thought I need to explicitly call emit_insn (gen_vec_extract (mode, mode, ....)
That's why I added in the last patch.

However, I found I don't need to call gen_vec_extract, so I remove "@" in this patch:
+      enum insn_code icode
+	= convert_optab_handler (vec_extract_optab, vmode, mode);
+      gcc_assert (icode != CODE_FOR_nothing);
+      class expand_operand ops[3];
+      create_output_operand (&ops[0], dest, mode);
+      ops[0].target = 1;
+      create_input_operand (&ops[1], gen_lowpart (vmode, SUBREG_REG (src)),
+			    vmode);
+      unsigned int index = SUBREG_BYTE (src).to_constant () / mode_size;
+      create_integer_operand (&ops[2], index);
+      expand_insn (icode, 3, ops);
This code is copied from optabs-query.cc



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2023-09-14 16:11
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]
On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote:
>
> This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
>
> I notice that previous patch (V2 patch) cause additional execution fail of pr69719.c
> This FAIL is because of the latent BUG of VSETVL PASS.
>
> So this patch includes VSETVL PASS fix even though it's not related to the PR111391.
>
> I have confirm the whole regression no additional FAILs are introduced.
>
>         PR target/111391
>
> gcc/ChangeLog:
>
>         * config/riscv/autovec.md (@vec_extract<mode><vel>): Remove @.
>         (vec_extract<mode><vel>): Ditto.
>         * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
>         (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
>         * config/riscv/riscv.cc (riscv_legitimize_move): Expand move.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
>         * gcc.target/riscv/rvv/autovec/pr111391.c: New test.
>
> ---
>  gcc/config/riscv/autovec.md                   |  2 +-
>  gcc/config/riscv/riscv-vsetvl.cc              |  4 ++-
>  gcc/config/riscv/riscv.cc                     | 32 +++++++++++++++++++
>  .../riscv/rvv/autovec/partial/slp-9.c         |  1 -
>  .../gcc.target/riscv/rvv/autovec/pr111391.c   | 28 ++++++++++++++++
>  5 files changed, 64 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index e74a1695709..7121bab1716 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1442,7 +1442,7 @@
>  ;; -------------------------------------------------------------------------
>  ;; ---- [INT,FP] Extract a vector element.
>  ;; -------------------------------------------------------------------------
> -(define_expand "@vec_extract<mode><vel>"
> +(define_expand "vec_extract<mode><vel>"
 
Why remove this? I saw this change was introduced in v3?
 
 
>    [(set (match_operand:<VEL>     0 "register_operand")
>       (vec_select:<VEL>
>         (match_operand:V_VLS      1 "register_operand")