From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7503 invoked by alias); 26 Mar 2012 10:14:58 -0000 Received: (qmail 7486 invoked by uid 22791); 26 Mar 2012 10:14:56 -0000 X-SWARE-Spam-Status: No, hits=-1.0 required=5.0 tests=AWL,BAYES_00,MISSING_HEADERS,TW_FM,TW_VF X-Spam-Check-By: sourceware.org Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 26 Mar 2012 10:14:40 +0000 Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1SC6wh-00077F-8L from Andrew_Stubbs@mentor.com ; Mon, 26 Mar 2012 03:14:39 -0700 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 26 Mar 2012 03:14:38 -0700 Received: from [172.30.14.214] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.1.289.1; Mon, 26 Mar 2012 11:14:36 +0100 Message-ID: <4F704189.4010302@codesourcery.com> Date: Mon, 26 Mar 2012 10:14:00 -0000 From: Andrew Stubbs User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:11.0) Gecko/20120310 Thunderbird/11.0 MIME-Version: 1.0 CC: "gcc-patches@gcc.gnu.org" , "patches@linaro.org" Subject: Re: [PATCH][ARM] NEON DImode neg References: <4F4D12C5.9070805@codesourcery.com> In-Reply-To: <4F4D12C5.9070805@codesourcery.com> Content-Type: multipart/mixed; boundary="------------070901070407090506080408" Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2012-03/txt/msg01639.txt.bz2 --------------070901070407090506080408 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Content-length: 823 On 28/02/12 17:45, Andrew Stubbs wrote: > Hi all, > > This patch adds a DImode negate pattern for NEON. > > Unfortunately, the NEON vneg instruction only supports vectors, not > singletons, so there's no direct way to do it in DImode, and the > compiler ends up moving the value back to core registers, negating it, > and returning to NEON afterwards: > > fmrrd r2, r3, d16 @ int > negs r2, r2 > sbc r3, r3, r3, lsl #1 > fmdrr d16, r2, r3 @ int > > The new patch does it entirely in NEON: > > vmov.i32 d17, #0 @ di > vsub.i64 d16, d17, d16 > > (Note that this is the result when combined with my recent patch for > NEON DImode immediates. Without that you get a constant pool load.) This updates fixes a bootstrap failure caused by an early clobber error. I've also got a native regression test running now. OK? Andrew --------------070901070407090506080408 Content-Type: text/x-patch; name="neon-neg64.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="neon-neg64.patch" Content-length: 2523 2012-03-26 Andrew Stubbs gcc/ * config/arm/arm.md (negdi2): Use gen_negdi2_neon. * config/arm/neon.md (negdi2_neon): New insn. Also add splitters for core and NEON registers. --- gcc/config/arm/arm.md | 8 +++++++- gcc/config/arm/neon.md | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 1 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 751997f..f1dbbf7 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4048,7 +4048,13 @@ (neg:DI (match_operand:DI 1 "s_register_operand" ""))) (clobber (reg:CC CC_REGNUM))])] "TARGET_EITHER" - "" + { + if (TARGET_NEON) + { + emit_insn (gen_negdi2_neon (operands[0], operands[1])); + DONE; + } + } ) ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1). diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 3c88568..bf229a7 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -922,6 +922,43 @@ (const_string "neon_int_3")))] ) +(define_insn "negdi2_neon" + [(set (match_operand:DI 0 "s_register_operand" "= w,?r,?&r,?w") + (neg:DI (match_operand:DI 1 "s_register_operand" " w, 0, r, w"))) + (clobber (match_scratch:DI 2 "=&w, X, X,&w")) + (clobber (reg:CC CC_REGNUM))] + "TARGET_NEON" + "#" + [(set_attr "length" "8") + (set_attr "arch" "nota8,*,*,onlya8")] +) + +; Split negdi2_neon for vfp registers +(define_split + [(set (match_operand:DI 0 "s_register_operand" "") + (neg:DI (match_operand:DI 1 "s_register_operand" ""))) + (clobber (match_scratch:DI 2 "")) + (clobber (reg:CC CC_REGNUM))] + "TARGET_NEON && reload_completed && IS_VFP_REGNUM (REGNO (operands[0]))" + [(set (match_dup 2) (const_int 0)) + (parallel [(set (match_dup 0) (minus:DI (match_dup 2) (match_dup 1))) + (clobber (reg:CC CC_REGNUM))])] + "" +) + +; Split negdi2_neon for core registers +(define_split + [(set (match_operand:DI 0 "s_register_operand" "") + (neg:DI (match_operand:DI 1 "s_register_operand" ""))) + (clobber (match_scratch:DI 2 "")) + (clobber (reg:CC CC_REGNUM))] + "TARGET_32BIT && reload_completed + && arm_general_register_operand (operands[0], DImode)" + [(parallel [(set (match_dup 0) (neg:DI (match_dup 1))) + (clobber (reg:CC CC_REGNUM))])] + "" +) + (define_insn "*umin3_neon" [(set (match_operand:VDQIW 0 "s_register_operand" "=w") (umin:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w") --------------070901070407090506080408--