* [arm] Remove obsolete FPA support (2/n): Remove command-line options
@ 2012-06-14 9:40 Richard Earnshaw
2012-06-14 14:43 ` [arm] Remove obsolete FPA support (3/n): Remove FPA patterns from MD files Richard Earnshaw
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: Richard Earnshaw @ 2012-06-14 9:40 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 375 bytes --]
This patch removes the command line options that enabled generation of
FPA and maverick instructions, along with their associated documentation.
* arm.opt (mfp=2, mfp=3, mfpe, mfpe=2, mfpe=3): Delete options.
* arm-fpus.def (fpa, fpe2, fpe3, maverick): Delete FPU types.
* arm-tables.opt: Regenerated.
* doc/invoke.texi: Remove references to deleted options.
R.
[-- Attachment #2: nofpa2.patch --]
[-- Type: text/plain, Size: 5553 bytes --]
Index: doc/invoke.texi
===================================================================
--- doc/invoke.texi (revision 188510)
+++ doc/invoke.texi (working copy)
@@ -479,7 +479,7 @@ Objective-C and Objective-C++ Dialects}.
-mapcs-reentrant -mno-apcs-reentrant @gol
-msched-prolog -mno-sched-prolog @gol
-mlittle-endian -mbig-endian -mwords-little-endian @gol
--mfloat-abi=@var{name} -mfpe @gol
+-mfloat-abi=@var{name} @gol
-mfp16-format=@var{name}
-mthumb-interwork -mno-thumb-interwork @gol
-mcpu=@var{name} -march=@var{name} -mfpu=@var{name} @gol
@@ -10823,20 +10823,12 @@ Linux, and not all architectures are rec
unsuccessful the option has no effect.
@item -mfpu=@var{name}
-@itemx -mfpe=@var{number}
-@itemx -mfp=@var{number}
@opindex mfpu
-@opindex mfpe
-@opindex mfp
This specifies what floating-point hardware (or hardware emulation) is
-available on the target. Permissible names are: @samp{fpa}, @samp{fpe2},
-@samp{fpe3}, @samp{maverick}, @samp{vfp}, @samp{vfpv3}, @samp{vfpv3-fp16},
-@samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd}, @samp{vfpv3xd-fp16},
-@samp{neon}, @samp{neon-fp16}, @samp{vfpv4}, @samp{vfpv4-d16},
-@samp{fpv4-sp-d16} and @samp{neon-vfpv4}.
-@option{-mfp} and @option{-mfpe} are synonyms for
-@option{-mfpu}=@samp{fpe}@var{number}, for compatibility with older versions
-of GCC@.
+available on the target. Permissible names are: @samp{vfp}, @samp{vfpv3},
+@samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd},
+@samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4},
+@samp{vfpv4-d16}, @samp{fpv4-sp-d16} and @samp{neon-vfpv4}.
If @option{-msoft-float} is specified this specifies the format of
floating-point values.
Index: config/arm/arm-tables.opt
===================================================================
--- config/arm/arm-tables.opt (revision 188510)
+++ config/arm/arm-tables.opt (working copy)
@@ -360,56 +360,44 @@ Name(arm_fpu) Type(int)
Known ARM FPUs (for use with the -mfpu= option):
EnumValue
-Enum(arm_fpu) String(fpa) Value(0)
+Enum(arm_fpu) String(vfp) Value(0)
EnumValue
-Enum(arm_fpu) String(fpe2) Value(1)
+Enum(arm_fpu) String(vfpv3) Value(1)
EnumValue
-Enum(arm_fpu) String(fpe3) Value(2)
+Enum(arm_fpu) String(vfpv3-fp16) Value(2)
EnumValue
-Enum(arm_fpu) String(maverick) Value(3)
+Enum(arm_fpu) String(vfpv3-d16) Value(3)
EnumValue
-Enum(arm_fpu) String(vfp) Value(4)
+Enum(arm_fpu) String(vfpv3-d16-fp16) Value(4)
EnumValue
-Enum(arm_fpu) String(vfpv3) Value(5)
+Enum(arm_fpu) String(vfpv3xd) Value(5)
EnumValue
-Enum(arm_fpu) String(vfpv3-fp16) Value(6)
+Enum(arm_fpu) String(vfpv3xd-fp16) Value(6)
EnumValue
-Enum(arm_fpu) String(vfpv3-d16) Value(7)
+Enum(arm_fpu) String(neon) Value(7)
EnumValue
-Enum(arm_fpu) String(vfpv3-d16-fp16) Value(8)
+Enum(arm_fpu) String(neon-fp16) Value(8)
EnumValue
-Enum(arm_fpu) String(vfpv3xd) Value(9)
+Enum(arm_fpu) String(vfpv4) Value(9)
EnumValue
-Enum(arm_fpu) String(vfpv3xd-fp16) Value(10)
+Enum(arm_fpu) String(vfpv4-d16) Value(10)
EnumValue
-Enum(arm_fpu) String(neon) Value(11)
+Enum(arm_fpu) String(fpv4-sp-d16) Value(11)
EnumValue
-Enum(arm_fpu) String(neon-fp16) Value(12)
+Enum(arm_fpu) String(neon-vfpv4) Value(12)
EnumValue
-Enum(arm_fpu) String(vfpv4) Value(13)
-
-EnumValue
-Enum(arm_fpu) String(vfpv4-d16) Value(14)
-
-EnumValue
-Enum(arm_fpu) String(fpv4-sp-d16) Value(15)
-
-EnumValue
-Enum(arm_fpu) String(neon-vfpv4) Value(16)
-
-EnumValue
-Enum(arm_fpu) String(vfp3) Value(17)
+Enum(arm_fpu) String(vfp3) Value(13)
Index: config/arm/arm.opt
===================================================================
--- config/arm/arm.opt (revision 188510)
+++ config/arm/arm.opt (working copy)
@@ -126,12 +126,6 @@ Enum(float_abi_type) String(softfp) Valu
EnumValue
Enum(float_abi_type) String(hard) Value(ARM_FLOAT_ABI_HARD)
-mfp=2
-Target RejectNegative Undocumented Alias(mfpu=, fpe2)
-
-mfp=3
-Target RejectNegative Undocumented Alias(mfpu=, fpe3)
-
mfp16-format=
Target RejectNegative Joined Enum(arm_fp16_format_type) Var(arm_fp16_format) Init(ARM_FP16_FORMAT_NONE)
Specify the __fp16 floating-point format
@@ -149,16 +143,6 @@ Enum(arm_fp16_format_type) String(ieee)
EnumValue
Enum(arm_fp16_format_type) String(alternative) Value(ARM_FP16_FORMAT_ALTERNATIVE)
-;; Now ignored.
-mfpe
-Target RejectNegative Mask(FPE) Undocumented
-
-mfpe=2
-Target RejectNegative Undocumented Alias(mfpu=, fpe2)
-
-mfpe=3
-Target RejectNegative Undocumented Alias(mfpu=, fpe3)
-
mfpu=
Target RejectNegative Joined Enum(arm_fpu) Var(arm_fpu_index)
Specify the name of the target floating point hardware/format
Index: config/arm/arm-fpus.def
===================================================================
--- config/arm/arm-fpus.def (revision 188510)
+++ config/arm/arm-fpus.def (working copy)
@@ -27,10 +27,6 @@
genopt.sh assumes no whitespace up to the first "," in each entry. */
-ARM_FPU("fpa", ARM_FP_MODEL_FPA, 0, VFP_NONE, false, false)
-ARM_FPU("fpe2", ARM_FP_MODEL_FPA, 2, VFP_NONE, false, false)
-ARM_FPU("fpe3", ARM_FP_MODEL_FPA, 3, VFP_NONE, false, false)
-ARM_FPU("maverick", ARM_FP_MODEL_MAVERICK, 0, VFP_NONE, false, false)
ARM_FPU("vfp", ARM_FP_MODEL_VFP, 2, VFP_REG_D16, false, false)
ARM_FPU("vfpv3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false)
ARM_FPU("vfpv3-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, true)
^ permalink raw reply [flat|nested] 8+ messages in thread
* [arm] Remove obsolete FPA support (3/n): Remove FPA patterns from MD files
2012-06-14 9:40 [arm] Remove obsolete FPA support (2/n): Remove command-line options Richard Earnshaw
@ 2012-06-14 14:43 ` Richard Earnshaw
2012-06-14 16:54 ` [arm] Remove obsolete FPA support (4/n): Remove Maverick " Richard Earnshaw
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Richard Earnshaw @ 2012-06-14 14:43 UTC (permalink / raw)
To: gcc-patches
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This patch removes the define_insn and define_expand support for the FPA.
Tested on arm-eabi and committed to trunk.
* arm.md (divsf3, divdf3): Remove FPA support.
(negsf2, negdf2): Likewise.
(sqrtsf2, sqrtdf2): Likewise.
(movdfcc): Likewise.
(modsf3, moddf3, movxf): Delete.
(push_fp_multi): Delete.
(fpa.md): Don't include it.
* fpa.md: Delete file.
* t-arm (MD_INCLUDES): Remove fpa.md.
R.
[-- Attachment #2: nofpa3.patch --]
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Index: config/arm/t-arm
===================================================================
--- config/arm/t-arm (revision 188602)
+++ config/arm/t-arm (working copy)
@@ -46,7 +46,6 @@ MD_INCLUDES= $(srcdir)/config/arm/arm102
$(srcdir)/config/arm/fa626te.md \
$(srcdir)/config/arm/fa726te.md \
$(srcdir)/config/arm/fmp626.md \
- $(srcdir)/config/arm/fpa.md \
$(srcdir)/config/arm/iterators.md \
$(srcdir)/config/arm/iwmmxt.md \
$(srcdir)/config/arm/iwmmxt2.md \
Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md (revision 188602)
+++ config/arm/arm.md (working copy)
@@ -1967,30 +1967,14 @@ (define_expand "divsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
(div:SF (match_operand:SF 1 "arm_float_rhs_operand" "")
(match_operand:SF 2 "arm_float_rhs_operand" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"")
(define_expand "divdf3"
[(set (match_operand:DF 0 "s_register_operand" "")
(div:DF (match_operand:DF 1 "arm_float_rhs_operand" "")
(match_operand:DF 2 "arm_float_rhs_operand" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
- "")
-\f
-;; Modulo insns
-
-(define_expand "modsf3"
- [(set (match_operand:SF 0 "s_register_operand" "")
- (mod:SF (match_operand:SF 1 "s_register_operand" "")
- (match_operand:SF 2 "arm_float_rhs_operand" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "")
-
-(define_expand "moddf3"
- [(set (match_operand:DF 0 "s_register_operand" "")
- (mod:DF (match_operand:DF 1 "s_register_operand" "")
- (match_operand:DF 2 "arm_float_rhs_operand" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"")
\f
;; Boolean and,ior,xor insns
@@ -4216,14 +4200,14 @@ (define_insn "*thumb1_negsi2"
(define_expand "negsf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(neg:SF (match_operand:SF 1 "s_register_operand" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
""
)
(define_expand "negdf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(neg:DF (match_operand:DF 1 "s_register_operand" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"")
;; abssi2 doesn't really clobber the condition codes if a different register
@@ -4315,13 +4299,13 @@ (define_expand "absdf2"
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(sqrt:SF (match_operand:SF 1 "s_register_operand" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"")
(define_expand "sqrtdf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(sqrt:DF (match_operand:DF 1 "s_register_operand" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"")
(define_insn_and_split "one_cmpldi2"
@@ -6821,17 +6805,6 @@ (define_insn "*thumb_movdf_insn"
(set_attr "insn" "*,*,*,*,*,mov")
(set_attr "pool_range" "*,*,*,1020,*,*")]
)
-
-(define_expand "movxf"
- [(set (match_operand:XF 0 "general_operand" "")
- (match_operand:XF 1 "general_operand" ""))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "
- if (GET_CODE (operands[0]) == MEM)
- operands[1] = force_reg (XFmode, operands[1]);
- "
-)
-
\f
;; load- and store-multiple insns
@@ -8199,7 +8172,7 @@ (define_expand "movdfcc"
(if_then_else:DF (match_operand 1 "expandable_comparison_operator" "")
(match_operand:DF 2 "s_register_operand" "")
(match_operand:DF 3 "arm_float_add_operand" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"
{
enum rtx_code code = GET_CODE (operands[1]);
@@ -11002,24 +10975,6 @@ (define_insn "stack_tie"
[(set_attr "length" "0")]
)
-;; Similarly for the floating point registers
-(define_insn "*push_fp_multi"
- [(match_parallel 2 "multi_register_push"
- [(set (match_operand:BLK 0 "memory_operand" "=m")
- (unspec:BLK [(match_operand:XF 1 "f_register_operand" "")]
- UNSPEC_PUSH_MULT))])]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "*
- {
- char pattern[100];
-
- sprintf (pattern, \"sfm%%(fd%%)\\t%%1, %d, [%%m0]!\", XVECLEN (operands[2], 0));
- output_asm_insn (pattern, operands);
- return \"\";
- }"
- [(set_attr "type" "f_fpa_store")]
-)
-
;; Special patterns for dealing with the constant pool
(define_insn "align_4"
@@ -11451,8 +11406,6 @@ (define_expand "bswapsi2"
;; Load the load/store multiple patterns
(include "ldmstm.md")
-;; Load the FPA co-processor patterns
-(include "fpa.md")
;; Load the Maverick co-processor patterns
(include "cirrus.md")
;; Vector bits common to IWMMXT and Neon
Index: config/arm/fpa.md
===================================================================
--- config/arm/fpa.md (revision 188602)
+++ config/arm/fpa.md (working copy)
@@ -1,889 +0,0 @@
-;;- Machine description for FPA co-processor for ARM cpus.
-;; Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000,
-;; 2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
-;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
-;; and Martin Simmons (@harleqn.co.uk).
-;; More major hacks by Richard Earnshaw (rearnsha@arm.com).
-
-;; This file is part of GCC.
-
-;; GCC is free software; you can redistribute it and/or modify it
-;; under the terms of the GNU General Public License as published
-;; by the Free Software Foundation; either version 3, or (at your
-;; option) any later version.
-
-;; GCC is distributed in the hope that it will be useful, but WITHOUT
-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
-;; License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING3. If not see
-;; <http://www.gnu.org/licenses/>.
-
-;; Some FPA mnemonics are ambiguous between conditional infixes and
-;; conditional suffixes. All instructions use a conditional infix,
-;; even in unified assembly mode.
-
-;; FPA automaton.
-(define_automaton "armfp")
-
-;; Floating point unit (FPA)
-(define_cpu_unit "fpa" "armfp")
-
-; The fpa10 doesn't really have a memory read unit, but it can start
-; to speculatively execute the instruction in the pipeline, provided
-; the data is already loaded, so pretend reads have a delay of 2 (and
-; that the pipeline is infinite).
-(define_cpu_unit "fpa_mem" "arm")
-
-(define_insn_reservation "fdivx" 71
- (and (eq_attr "fpu" "fpa")
- (eq_attr "type" "fdivx"))
- "core+fpa*69")
-
-(define_insn_reservation "fdivd" 59
- (and (eq_attr "fpu" "fpa")
- (eq_attr "type" "fdivd"))
- "core+fpa*57")
-
-(define_insn_reservation "fdivs" 31
- (and (eq_attr "fpu" "fpa")
- (eq_attr "type" "fdivs"))
- "core+fpa*29")
-
-(define_insn_reservation "fmul" 9
- (and (eq_attr "fpu" "fpa")
- (eq_attr "type" "fmul"))
- "core+fpa*7")
-
-(define_insn_reservation "ffmul" 6
- (and (eq_attr "fpu" "fpa")
- (eq_attr "type" "ffmul"))
- "core+fpa*4")
-
-(define_insn_reservation "farith" 4
- (and (eq_attr "fpu" "fpa")
- (eq_attr "type" "farith"))
- "core+fpa*2")
-
-(define_insn_reservation "ffarith" 2
- (and (eq_attr "fpu" "fpa")
- (eq_attr "type" "ffarith"))
- "core+fpa*2")
-
-(define_insn_reservation "r_2_f" 5
- (and (eq_attr "fpu" "fpa")
- (eq_attr "type" "r_2_f"))
- "core+fpa*3")
-
-(define_insn_reservation "f_2_r" 1
- (and (eq_attr "fpu" "fpa")
- (eq_attr "type" "f_2_r"))
- "core+fpa*2")
-
-(define_insn_reservation "f_load" 3
- (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_fpa_load"))
- "fpa_mem+core*3")
-
-(define_insn_reservation "f_store" 4
- (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_fpa_store"))
- "core*4")
-
-(define_insn_reservation "r_mem_f" 6
- (and (eq_attr "model_wbuf" "no")
- (and (eq_attr "fpu" "fpa") (eq_attr "type" "r_mem_f")))
- "core*6")
-
-(define_insn_reservation "f_mem_r" 7
- (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_mem_r"))
- "core*7")
-
-
-(define_insn "*addsf3_fpa"
- [(set (match_operand:SF 0 "s_register_operand" "=f,f")
- (plus:SF (match_operand:SF 1 "s_register_operand" "%f,f")
- (match_operand:SF 2 "arm_float_add_operand" "fG,H")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- adf%?s\\t%0, %1, %2
- suf%?s\\t%0, %1, #%N2"
- [(set_attr "type" "farith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*adddf3_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f,f")
- (plus:DF (match_operand:DF 1 "s_register_operand" "%f,f")
- (match_operand:DF 2 "arm_float_add_operand" "fG,H")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- adf%?d\\t%0, %1, %2
- suf%?d\\t%0, %1, #%N2"
- [(set_attr "type" "farith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*adddf_esfdf_df_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f,f")
- (plus:DF (float_extend:DF
- (match_operand:SF 1 "s_register_operand" "f,f"))
- (match_operand:DF 2 "arm_float_add_operand" "fG,H")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- adf%?d\\t%0, %1, %2
- suf%?d\\t%0, %1, #%N2"
- [(set_attr "type" "farith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*adddf_df_esfdf_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (plus:DF (match_operand:DF 1 "s_register_operand" "f")
- (float_extend:DF
- (match_operand:SF 2 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "adf%?d\\t%0, %1, %2"
- [(set_attr "type" "farith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*adddf_esfdf_esfdf_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (plus:DF (float_extend:DF
- (match_operand:SF 1 "s_register_operand" "f"))
- (float_extend:DF
- (match_operand:SF 2 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "adf%?d\\t%0, %1, %2"
- [(set_attr "type" "farith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*subsf3_fpa"
- [(set (match_operand:SF 0 "s_register_operand" "=f,f")
- (minus:SF (match_operand:SF 1 "arm_float_rhs_operand" "f,G")
- (match_operand:SF 2 "arm_float_rhs_operand" "fG,f")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- suf%?s\\t%0, %1, %2
- rsf%?s\\t%0, %2, %1"
- [(set_attr "type" "farith")]
-)
-
-(define_insn "*subdf3_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f,f")
- (minus:DF (match_operand:DF 1 "arm_float_rhs_operand" "f,G")
- (match_operand:DF 2 "arm_float_rhs_operand" "fG,f")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- suf%?d\\t%0, %1, %2
- rsf%?d\\t%0, %2, %1"
- [(set_attr "type" "farith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*subdf_esfdf_df_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (minus:DF (float_extend:DF
- (match_operand:SF 1 "s_register_operand" "f"))
- (match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "suf%?d\\t%0, %1, %2"
- [(set_attr "type" "farith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*subdf_df_esfdf_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f,f")
- (minus:DF (match_operand:DF 1 "arm_float_rhs_operand" "f,G")
- (float_extend:DF
- (match_operand:SF 2 "s_register_operand" "f,f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- suf%?d\\t%0, %1, %2
- rsf%?d\\t%0, %2, %1"
- [(set_attr "type" "farith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*subdf_esfdf_esfdf_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (minus:DF (float_extend:DF
- (match_operand:SF 1 "s_register_operand" "f"))
- (float_extend:DF
- (match_operand:SF 2 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "suf%?d\\t%0, %1, %2"
- [(set_attr "type" "farith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*mulsf3_fpa"
- [(set (match_operand:SF 0 "s_register_operand" "=f")
- (mult:SF (match_operand:SF 1 "s_register_operand" "f")
- (match_operand:SF 2 "arm_float_rhs_operand" "fG")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "fml%?s\\t%0, %1, %2"
- [(set_attr "type" "ffmul")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*muldf3_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (mult:DF (match_operand:DF 1 "s_register_operand" "f")
- (match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "muf%?d\\t%0, %1, %2"
- [(set_attr "type" "fmul")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*muldf_esfdf_df_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (mult:DF (float_extend:DF
- (match_operand:SF 1 "s_register_operand" "f"))
- (match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "muf%?d\\t%0, %1, %2"
- [(set_attr "type" "fmul")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*muldf_df_esfdf_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (mult:DF (match_operand:DF 1 "s_register_operand" "f")
- (float_extend:DF
- (match_operand:SF 2 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "muf%?d\\t%0, %1, %2"
- [(set_attr "type" "fmul")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*muldf_esfdf_esfdf_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (mult:DF
- (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))
- (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "muf%?d\\t%0, %1, %2"
- [(set_attr "type" "fmul")
- (set_attr "predicable" "yes")]
-)
-
-;; Division insns
-
-(define_insn "*divsf3_fpa"
- [(set (match_operand:SF 0 "s_register_operand" "=f,f")
- (div:SF (match_operand:SF 1 "arm_float_rhs_operand" "f,G")
- (match_operand:SF 2 "arm_float_rhs_operand" "fG,f")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- fdv%?s\\t%0, %1, %2
- frd%?s\\t%0, %2, %1"
- [(set_attr "type" "fdivs")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*divdf3_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f,f")
- (div:DF (match_operand:DF 1 "arm_float_rhs_operand" "f,G")
- (match_operand:DF 2 "arm_float_rhs_operand" "fG,f")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- dvf%?d\\t%0, %1, %2
- rdf%?d\\t%0, %2, %1"
- [(set_attr "type" "fdivd")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*divdf_esfdf_df_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (div:DF (float_extend:DF
- (match_operand:SF 1 "s_register_operand" "f"))
- (match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "dvf%?d\\t%0, %1, %2"
- [(set_attr "type" "fdivd")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*divdf_df_esfdf_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (div:DF (match_operand:DF 1 "arm_float_rhs_operand" "fG")
- (float_extend:DF
- (match_operand:SF 2 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "rdf%?d\\t%0, %2, %1"
- [(set_attr "type" "fdivd")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*divdf_esfdf_esfdf_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (div:DF (float_extend:DF
- (match_operand:SF 1 "s_register_operand" "f"))
- (float_extend:DF
- (match_operand:SF 2 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "dvf%?d\\t%0, %1, %2"
- [(set_attr "type" "fdivd")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*modsf3_fpa"
- [(set (match_operand:SF 0 "s_register_operand" "=f")
- (mod:SF (match_operand:SF 1 "s_register_operand" "f")
- (match_operand:SF 2 "arm_float_rhs_operand" "fG")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "rmf%?s\\t%0, %1, %2"
- [(set_attr "type" "fdivs")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*moddf3_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (mod:DF (match_operand:DF 1 "s_register_operand" "f")
- (match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "rmf%?d\\t%0, %1, %2"
- [(set_attr "type" "fdivd")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*moddf_esfdf_df_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (mod:DF (float_extend:DF
- (match_operand:SF 1 "s_register_operand" "f"))
- (match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "rmf%?d\\t%0, %1, %2"
- [(set_attr "type" "fdivd")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*moddf_df_esfdf_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (mod:DF (match_operand:DF 1 "s_register_operand" "f")
- (float_extend:DF
- (match_operand:SF 2 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "rmf%?d\\t%0, %1, %2"
- [(set_attr "type" "fdivd")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*moddf_esfdf_esfdf_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (mod:DF (float_extend:DF
- (match_operand:SF 1 "s_register_operand" "f"))
- (float_extend:DF
- (match_operand:SF 2 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "rmf%?d\\t%0, %1, %2"
- [(set_attr "type" "fdivd")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*negsf2_fpa"
- [(set (match_operand:SF 0 "s_register_operand" "=f")
- (neg:SF (match_operand:SF 1 "s_register_operand" "f")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "mnf%?s\\t%0, %1"
- [(set_attr "type" "ffarith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*negdf2_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (neg:DF (match_operand:DF 1 "s_register_operand" "f")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "mnf%?d\\t%0, %1"
- [(set_attr "type" "ffarith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*negdf_esfdf_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (neg:DF (float_extend:DF
- (match_operand:SF 1 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "mnf%?d\\t%0, %1"
- [(set_attr "type" "ffarith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*abssf2_fpa"
- [(set (match_operand:SF 0 "s_register_operand" "=f")
- (abs:SF (match_operand:SF 1 "s_register_operand" "f")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "abs%?s\\t%0, %1"
- [(set_attr "type" "ffarith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*absdf2_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (abs:DF (match_operand:DF 1 "s_register_operand" "f")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "abs%?d\\t%0, %1"
- [(set_attr "type" "ffarith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*absdf_esfdf_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (abs:DF (float_extend:DF
- (match_operand:SF 1 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "abs%?d\\t%0, %1"
- [(set_attr "type" "ffarith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*sqrtsf2_fpa"
- [(set (match_operand:SF 0 "s_register_operand" "=f")
- (sqrt:SF (match_operand:SF 1 "s_register_operand" "f")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "sqt%?s\\t%0, %1"
- [(set_attr "type" "float_em")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*sqrtdf2_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (sqrt:DF (match_operand:DF 1 "s_register_operand" "f")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "sqt%?d\\t%0, %1"
- [(set_attr "type" "float_em")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*sqrtdf_esfdf_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (sqrt:DF (float_extend:DF
- (match_operand:SF 1 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "sqt%?d\\t%0, %1"
- [(set_attr "type" "float_em")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*floatsisf2_fpa"
- [(set (match_operand:SF 0 "s_register_operand" "=f")
- (float:SF (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "flt%?s\\t%0, %1"
- [(set_attr "type" "r_2_f")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*floatsidf2_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (float:DF (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "flt%?d\\t%0, %1"
- [(set_attr "type" "r_2_f")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*fix_truncsfsi2_fpa"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "fix%?z\\t%0, %1"
- [(set_attr "type" "f_2_r")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*fix_truncdfsi2_fpa"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "fix%?z\\t%0, %1"
- [(set_attr "type" "f_2_r")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*truncdfsf2_fpa"
- [(set (match_operand:SF 0 "s_register_operand" "=f")
- (float_truncate:SF
- (match_operand:DF 1 "s_register_operand" "f")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "mvf%?s\\t%0, %1"
- [(set_attr "type" "ffarith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*extendsfdf2_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "mvf%?d\\t%0, %1"
- [(set_attr "type" "ffarith")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*movsf_fpa"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f, m,f,r,r,r, m")
- (match_operand:SF 1 "general_operand" "fG,H,mE,f,r,f,r,mE,r"))]
- "TARGET_ARM
- && TARGET_HARD_FLOAT && TARGET_FPA
- && (GET_CODE (operands[0]) != MEM
- || register_operand (operands[1], SFmode))"
- "@
- mvf%?s\\t%0, %1
- mnf%?s\\t%0, #%N1
- ldf%?s\\t%0, %1
- stf%?s\\t%1, %0
- str%?\\t%1, [%|sp, #-4]!\;ldf%?s\\t%0, [%|sp], #4
- stf%?s\\t%1, [%|sp, #-4]!\;ldr%?\\t%0, [%|sp], #4
- mov%?\\t%0, %1
- ldr%?\\t%0, %1\\t%@ float
- str%?\\t%1, %0\\t%@ float"
- [(set_attr "length" "4,4,4,4,8,8,4,4,4")
- (set_attr "predicable" "yes")
- (set_attr "type"
- "ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r,*,load1,store1")
- (set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*")
- (set_attr "neg_pool_range" "*,*,1012,*,*,*,*,4084,*")]
-)
-
-(define_insn "*movdf_fpa"
- [(set (match_operand:DF 0 "nonimmediate_operand"
- "=r,Q,r,m,r, f, f,f, m,!f,!r")
- (match_operand:DF 1 "general_operand"
- "Q, r,r,r,mF,fG,H,mF,f,r, f"))]
- "TARGET_ARM
- && TARGET_HARD_FLOAT && TARGET_FPA
- && (GET_CODE (operands[0]) != MEM
- || register_operand (operands[1], DFmode))"
- "*
- {
- switch (which_alternative)
- {
- default:
- case 0: return \"ldm%(ia%)\\t%m1, %M0\\t%@ double\";
- case 1: return \"stm%(ia%)\\t%m0, %M1\\t%@ double\";
- case 2: return \"#\";
- case 3: case 4: return output_move_double (operands, true, NULL);
- case 5: return \"mvf%?d\\t%0, %1\";
- case 6: return \"mnf%?d\\t%0, #%N1\";
- case 7: return \"ldf%?d\\t%0, %1\";
- case 8: return \"stf%?d\\t%1, %0\";
- case 9: return output_mov_double_fpa_from_arm (operands);
- case 10: return output_mov_double_arm_from_fpa (operands);
- }
- }
- "
- [(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8")
- (set_attr "predicable" "yes")
- (set_attr "type"
- "load1,store2,*,store2,load1,ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r")
- (set_attr "pool_range" "*,*,*,*,1020,*,*,1024,*,*,*")
- (set_attr "neg_pool_range" "*,*,*,*,1008,*,*,1008,*,*,*")]
-)
-
-;; We treat XFmode as meaning 'internal format'. It's the right size and we
-;; don't use it for anything else. We only support moving between FPA
-;; registers and moving an FPA register to/from memory.
-(define_insn "*movxf_fpa"
- [(set (match_operand:XF 0 "nonimmediate_operand" "=f,f,m")
- (match_operand:XF 1 "general_operand" "f,m,f"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA
- && (register_operand (operands[0], XFmode)
- || register_operand (operands[1], XFmode))"
- "*
- switch (which_alternative)
- {
- default:
- case 0: return \"mvf%?e\\t%0, %1\";
- case 1: if (TARGET_FPA_EMU2)
- return \"ldf%?e\\t%0, %1\";
- return \"lfm%?\\t%0, 1, %1\";
- case 2: if (TARGET_FPA_EMU2)
- return \"stf%?e\\t%1, %0\";
- return \"sfm%?\\t%1, 1, %0\";
- }
- "
- [(set_attr "length" "4,4,4")
- (set_attr "predicable" "yes")
- (set_attr "type" "ffarith,f_fpa_load,f_fpa_store")]
-)
-
-;; stfs/ldfs always use a conditional infix. This works around the
-;; ambiguity between "stf pl s" and "sftp ls".
-(define_insn "*thumb2_movsf_fpa"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f, m,f,r,r,r, m")
- (match_operand:SF 1 "general_operand" "fG,H,mE,f,r,f,r,mE,r"))]
- "TARGET_THUMB2
- && TARGET_HARD_FLOAT && TARGET_FPA
- && (GET_CODE (operands[0]) != MEM
- || register_operand (operands[1], SFmode))"
- "@
- mvf%?s\\t%0, %1
- mnf%?s\\t%0, #%N1
- ldf%?s\\t%0, %1
- stf%?s\\t%1, %0
- str%?\\t%1, [%|sp, #-4]!\;ldf%?s\\t%0, [%|sp], #4
- stf%?s\\t%1, [%|sp, #-4]!\;ldr%?\\t%0, [%|sp], #4
- mov%?\\t%0, %1 @bar
- ldr%?\\t%0, %1\\t%@ float
- str%?\\t%1, %0\\t%@ float"
- [(set_attr "length" "4,4,4,4,8,8,4,4,4")
- (set_attr "ce_count" "1,1,1,1,2,2,1,1,1")
- (set_attr "predicable" "yes")
- (set_attr "type"
- "ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r,*,load1,store1")
- (set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*")
- (set_attr "neg_pool_range" "*,*,1012,*,*,*,*,0,*")]
-)
-
-;; Not predicable because we don't know the number of instructions.
-(define_insn "*thumb2_movdf_fpa"
- [(set (match_operand:DF 0 "nonimmediate_operand"
- "=r,Q,r,m,r, f, f,f, m,!f,!r")
- (match_operand:DF 1 "general_operand"
- "Q, r,r,r,mF,fG,H,mF,f,r, f"))]
- "TARGET_THUMB2
- && TARGET_HARD_FLOAT && TARGET_FPA
- && (GET_CODE (operands[0]) != MEM
- || register_operand (operands[1], DFmode))"
- "*
- {
- switch (which_alternative)
- {
- default:
- case 0: return \"ldm%(ia%)\\t%m1, %M0\\t%@ double\";
- case 1: return \"stm%(ia%)\\t%m0, %M1\\t%@ double\";
- case 2: case 3: case 4: return output_move_double (operands, true, NULL);
- case 5: return \"mvf%?d\\t%0, %1\";
- case 6: return \"mnf%?d\\t%0, #%N1\";
- case 7: return \"ldf%?d\\t%0, %1\";
- case 8: return \"stf%?d\\t%1, %0\";
- case 9: return output_mov_double_fpa_from_arm (operands);
- case 10: return output_mov_double_arm_from_fpa (operands);
- }
- }
- "
- [(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8")
- (set_attr "type"
- "load1,store2,*,store2,load1,ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r")
- (set_attr "pool_range" "*,*,*,*,4092,*,*,1024,*,*,*")
- (set_attr "neg_pool_range" "*,*,*,*,0,*,*,1008,*,*,*")]
-)
-
-;; Saving and restoring the floating point registers in the prologue should
-;; be done in XFmode, even though we don't support that for anything else
-;; (Well, strictly it's 'internal representation', but that's effectively
-;; XFmode).
-;; Not predicable because we don't know the number of instructions.
-
-(define_insn "*thumb2_movxf_fpa"
- [(set (match_operand:XF 0 "nonimmediate_operand" "=f,f,f,m,f,r,r")
- (match_operand:XF 1 "general_operand" "fG,H,m,f,r,f,r"))]
- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_FPA && reload_completed"
- "*
- switch (which_alternative)
- {
- default:
- case 0: return \"mvf%?e\\t%0, %1\";
- case 1: return \"mnf%?e\\t%0, #%N1\";
- case 2: return \"ldf%?e\\t%0, %1\";
- case 3: return \"stf%?e\\t%1, %0\";
- case 4: return output_mov_long_double_fpa_from_arm (operands);
- case 5: return output_mov_long_double_arm_from_fpa (operands);
- case 6: return output_mov_long_double_arm_from_arm (operands);
- }
- "
- [(set_attr "length" "4,4,4,4,8,8,12")
- (set_attr "type" "ffarith,ffarith,f_fpa_load,f_fpa_store,r_mem_f,f_mem_r,*")
- (set_attr "pool_range" "*,*,1024,*,*,*,*")
- (set_attr "neg_pool_range" "*,*,1004,*,*,*,*")]
-)
-
-(define_insn "*cmpsf_fpa"
- [(set (reg:CCFP CC_REGNUM)
- (compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f")
- (match_operand:SF 1 "arm_float_add_operand" "fG,H")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- cmf%?\\t%0, %1
- cnf%?\\t%0, #%N1"
- [(set_attr "conds" "set")
- (set_attr "type" "f_2_r")]
-)
-
-(define_insn "*cmpdf_fpa"
- [(set (reg:CCFP CC_REGNUM)
- (compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f")
- (match_operand:DF 1 "arm_float_add_operand" "fG,H")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- cmf%?\\t%0, %1
- cnf%?\\t%0, #%N1"
- [(set_attr "conds" "set")
- (set_attr "type" "f_2_r")]
-)
-
-(define_insn "*cmpesfdf_df_fpa"
- [(set (reg:CCFP CC_REGNUM)
- (compare:CCFP (float_extend:DF
- (match_operand:SF 0 "s_register_operand" "f,f"))
- (match_operand:DF 1 "arm_float_add_operand" "fG,H")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- cmf%?\\t%0, %1
- cnf%?\\t%0, #%N1"
- [(set_attr "conds" "set")
- (set_attr "type" "f_2_r")]
-)
-
-(define_insn "*cmpdf_esfdf_fpa"
- [(set (reg:CCFP CC_REGNUM)
- (compare:CCFP (match_operand:DF 0 "s_register_operand" "f")
- (float_extend:DF
- (match_operand:SF 1 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "cmf%?\\t%0, %1"
- [(set_attr "conds" "set")
- (set_attr "type" "f_2_r")]
-)
-
-(define_insn "*cmpsf_trap_fpa"
- [(set (reg:CCFPE CC_REGNUM)
- (compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f")
- (match_operand:SF 1 "arm_float_add_operand" "fG,H")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- cmf%?e\\t%0, %1
- cnf%?e\\t%0, #%N1"
- [(set_attr "conds" "set")
- (set_attr "type" "f_2_r")]
-)
-
-(define_insn "*cmpdf_trap_fpa"
- [(set (reg:CCFPE CC_REGNUM)
- (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f")
- (match_operand:DF 1 "arm_float_add_operand" "fG,H")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- cmf%?e\\t%0, %1
- cnf%?e\\t%0, #%N1"
- [(set_attr "conds" "set")
- (set_attr "type" "f_2_r")]
-)
-
-(define_insn "*cmp_esfdf_df_trap_fpa"
- [(set (reg:CCFPE CC_REGNUM)
- (compare:CCFPE (float_extend:DF
- (match_operand:SF 0 "s_register_operand" "f,f"))
- (match_operand:DF 1 "arm_float_add_operand" "fG,H")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- cmf%?e\\t%0, %1
- cnf%?e\\t%0, #%N1"
- [(set_attr "conds" "set")
- (set_attr "type" "f_2_r")]
-)
-
-(define_insn "*cmp_df_esfdf_trap_fpa"
- [(set (reg:CCFPE CC_REGNUM)
- (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f")
- (float_extend:DF
- (match_operand:SF 1 "s_register_operand" "f"))))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA"
- "cmf%?e\\t%0, %1"
- [(set_attr "conds" "set")
- (set_attr "type" "f_2_r")]
-)
-
-(define_insn "*movsfcc_fpa"
- [(set (match_operand:SF 0 "s_register_operand" "=f,f,f,f,f,f,f,f")
- (if_then_else:SF
- (match_operator 3 "arm_comparison_operator"
- [(match_operand 4 "cc_register" "") (const_int 0)])
- (match_operand:SF 1 "arm_float_add_operand" "0,0,fG,H,fG,fG,H,H")
- (match_operand:SF 2 "arm_float_add_operand" "fG,H,0,0,fG,H,fG,H")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- mvf%D3s\\t%0, %2
- mnf%D3s\\t%0, #%N2
- mvf%d3s\\t%0, %1
- mnf%d3s\\t%0, #%N1
- mvf%d3s\\t%0, %1\;mvf%D3s\\t%0, %2
- mvf%d3s\\t%0, %1\;mnf%D3s\\t%0, #%N2
- mnf%d3s\\t%0, #%N1\;mvf%D3s\\t%0, %2
- mnf%d3s\\t%0, #%N1\;mnf%D3s\\t%0, #%N2"
- [(set_attr "length" "4,4,4,4,8,8,8,8")
- (set_attr "type" "ffarith")
- (set_attr "conds" "use")]
-)
-
-(define_insn "*movdfcc_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f,f,f,f,f,f,f,f")
- (if_then_else:DF
- (match_operator 3 "arm_comparison_operator"
- [(match_operand 4 "cc_register" "") (const_int 0)])
- (match_operand:DF 1 "arm_float_add_operand" "0,0,fG,H,fG,fG,H,H")
- (match_operand:DF 2 "arm_float_add_operand" "fG,H,0,0,fG,H,fG,H")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- mvf%D3d\\t%0, %2
- mnf%D3d\\t%0, #%N2
- mvf%d3d\\t%0, %1
- mnf%d3d\\t%0, #%N1
- mvf%d3d\\t%0, %1\;mvf%D3d\\t%0, %2
- mvf%d3d\\t%0, %1\;mnf%D3d\\t%0, #%N2
- mnf%d3d\\t%0, #%N1\;mvf%D3d\\t%0, %2
- mnf%d3d\\t%0, #%N1\;mnf%D3d\\t%0, #%N2"
- [(set_attr "length" "4,4,4,4,8,8,8,8")
- (set_attr "type" "ffarith")
- (set_attr "conds" "use")]
-)
-
-(define_insn "*thumb2_movsfcc_fpa"
- [(set (match_operand:SF 0 "s_register_operand" "=f,f,f,f,f,f,f,f")
- (if_then_else:SF
- (match_operator 3 "arm_comparison_operator"
- [(match_operand 4 "cc_register" "") (const_int 0)])
- (match_operand:SF 1 "arm_float_add_operand" "0,0,fG,H,fG,fG,H,H")
- (match_operand:SF 2 "arm_float_add_operand" "fG,H,0,0,fG,H,fG,H")))]
- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- it\\t%D3\;mvf%D3s\\t%0, %2
- it\\t%D3\;mnf%D3s\\t%0, #%N2
- it\\t%d3\;mvf%d3s\\t%0, %1
- it\\t%d3\;mnf%d3s\\t%0, #%N1
- ite\\t%d3\;mvf%d3s\\t%0, %1\;mvf%D3s\\t%0, %2
- ite\\t%d3\;mvf%d3s\\t%0, %1\;mnf%D3s\\t%0, #%N2
- ite\\t%d3\;mnf%d3s\\t%0, #%N1\;mvf%D3s\\t%0, %2
- ite\\t%d3\;mnf%d3s\\t%0, #%N1\;mnf%D3s\\t%0, #%N2"
- [(set_attr "length" "6,6,6,6,10,10,10,10")
- (set_attr "type" "ffarith")
- (set_attr "conds" "use")]
-)
-
-(define_insn "*thumb2_movdfcc_fpa"
- [(set (match_operand:DF 0 "s_register_operand" "=f,f,f,f,f,f,f,f")
- (if_then_else:DF
- (match_operator 3 "arm_comparison_operator"
- [(match_operand 4 "cc_register" "") (const_int 0)])
- (match_operand:DF 1 "arm_float_add_operand" "0,0,fG,H,fG,fG,H,H")
- (match_operand:DF 2 "arm_float_add_operand" "fG,H,0,0,fG,H,fG,H")))]
- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_FPA"
- "@
- it\\t%D3\;mvf%D3d\\t%0, %2
- it\\t%D3\;mnf%D3d\\t%0, #%N2
- it\\t%d3\;mvf%d3d\\t%0, %1
- it\\t%d3\;mnf%d3d\\t%0, #%N1
- ite\\t%d3\;mvf%d3d\\t%0, %1\;mvf%D3d\\t%0, %2
- ite\\t%d3\;mvf%d3d\\t%0, %1\;mnf%D3d\\t%0, #%N2
- ite\\t%d3\;mnf%d3d\\t%0, #%N1\;mvf%D3d\\t%0, %2
- ite\\t%d3\;mnf%d3d\\t%0, #%N1\;mnf%D3d\\t%0, #%N2"
- [(set_attr "length" "6,6,6,6,10,10,10,10")
- (set_attr "type" "ffarith")
- (set_attr "conds" "use")]
-)
-
^ permalink raw reply [flat|nested] 8+ messages in thread
* [arm] Remove obsolete FPA support (4/n): Remove Maverick patterns from MD files
2012-06-14 9:40 [arm] Remove obsolete FPA support (2/n): Remove command-line options Richard Earnshaw
2012-06-14 14:43 ` [arm] Remove obsolete FPA support (3/n): Remove FPA patterns from MD files Richard Earnshaw
@ 2012-06-14 16:54 ` Richard Earnshaw
2012-06-15 14:16 ` [arm] Remove obsolete FPA support (5/n): Clean up predicates and constraints Richard Earnshaw
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Richard Earnshaw @ 2012-06-14 16:54 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1059 bytes --]
This patch removes the define_insn and define_expand support for the
obsolete Maverick co-processor.
There's some necessary purging of code in arm.c as well (though the
major cleanups here are still to come).
Tested on arm-eabi and committed to trunk.
* arm.c (arm_cirrus_insn_p): Delete.
(cirrus_reorg): Delete.
(arm_reorg): Don't call cirrus_reorg.
(arm_final_prescan_insn_p): Don't check for cirrus insns.
* arm.md (define_attr "type"): Remove mav_farith and mav_dmult.
(adddi3, subdi3): Remove Maverick support.
(arm_adddi3): Likewise.
(adddi_sesidi_di, adddi_zesidi_di): Likewise.
(addsf3, adddf3): Likewise.
(subsf3, subdf3): Likewise.
(mulsf3, muldf3): Likewise.
(ashldi3, ashrdi3, lshrdi3): Likewise.
(floatsisf2, floatsidf2): Likewise.
(fix_truncsfsi2, fix_truncdfsi2): Likewise.
(arm_movdi, thumb1_movdi_insn): Likewise.
(arm_cmpdi_insn): Likewise.
(cirrus_cmpsf, cirrus_cmpdf, cirrus_cmpdi): Likewise.
(cirrus.md): Don't include.
* cirrus.md: Delete file.
* t-arm (MD_INCLUDES): Remove cirrus.md.
[-- Attachment #2: nofpa4.patch --]
[-- Type: text/plain, Size: 40061 bytes --]
Index: config/arm/arm.c
===================================================================
--- config/arm/arm.c (revision 188614)
+++ config/arm/arm.c (working copy)
@@ -167,8 +167,6 @@ static int arm_address_cost (rtx, bool);
static int arm_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
static int arm_memory_move_cost (enum machine_mode, reg_class_t, bool);
static bool arm_memory_load_p (rtx);
-static bool arm_cirrus_insn_p (rtx);
-static void cirrus_reorg (rtx);
static void arm_init_builtins (void);
static void arm_init_iwmmxt_builtins (void);
static rtx safe_vector_operand (rtx, enum machine_mode);
@@ -9821,144 +9819,6 @@ arm_memory_load_p (rtx insn)
|| note_invalid_constants (insn, -1, false));
}
-/* Return TRUE if INSN is a Cirrus instruction. */
-static bool
-arm_cirrus_insn_p (rtx insn)
-{
- enum attr_cirrus attr;
-
- /* get_attr cannot accept USE or CLOBBER. */
- if (!insn
- || GET_CODE (insn) != INSN
- || GET_CODE (PATTERN (insn)) == USE
- || GET_CODE (PATTERN (insn)) == CLOBBER)
- return 0;
-
- attr = get_attr_cirrus (insn);
-
- return attr != CIRRUS_NOT;
-}
-
-/* Cirrus reorg for invalid instruction combinations. */
-static void
-cirrus_reorg (rtx first)
-{
- enum attr_cirrus attr;
- rtx body = PATTERN (first);
- rtx t;
- int nops;
-
- /* Any branch must be followed by 2 non Cirrus instructions. */
- if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
- {
- nops = 0;
- t = next_nonnote_insn (first);
-
- if (arm_cirrus_insn_p (t))
- ++ nops;
-
- if (arm_cirrus_insn_p (next_nonnote_insn (t)))
- ++ nops;
-
- while (nops --)
- emit_insn_after (gen_nop (), first);
-
- return;
- }
-
- /* (float (blah)) is in parallel with a clobber. */
- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
- body = XVECEXP (body, 0, 0);
-
- if (GET_CODE (body) == SET)
- {
- rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
-
- /* cfldrd, cfldr64, cfstrd, cfstr64 must
- be followed by a non Cirrus insn. */
- if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
- {
- if (arm_cirrus_insn_p (next_nonnote_insn (first)))
- emit_insn_after (gen_nop (), first);
-
- return;
- }
- else if (arm_memory_load_p (first))
- {
- unsigned int arm_regno;
-
- /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
- ldr/cfmv64hr combination where the Rd field is the same
- in both instructions must be split with a non Cirrus
- insn. Example:
-
- ldr r0, blah
- nop
- cfmvsr mvf0, r0. */
-
- /* Get Arm register number for ldr insn. */
- if (GET_CODE (lhs) == REG)
- arm_regno = REGNO (lhs);
- else
- {
- gcc_assert (GET_CODE (rhs) == REG);
- arm_regno = REGNO (rhs);
- }
-
- /* Next insn. */
- first = next_nonnote_insn (first);
-
- if (! arm_cirrus_insn_p (first))
- return;
-
- body = PATTERN (first);
-
- /* (float (blah)) is in parallel with a clobber. */
- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
- body = XVECEXP (body, 0, 0);
-
- if (GET_CODE (body) == FLOAT)
- body = XEXP (body, 0);
-
- if (get_attr_cirrus (first) == CIRRUS_MOVE
- && GET_CODE (XEXP (body, 1)) == REG
- && arm_regno == REGNO (XEXP (body, 1)))
- emit_insn_after (gen_nop (), first);
-
- return;
- }
- }
-
- /* get_attr cannot accept USE or CLOBBER. */
- if (!first
- || GET_CODE (first) != INSN
- || GET_CODE (PATTERN (first)) == USE
- || GET_CODE (PATTERN (first)) == CLOBBER)
- return;
-
- attr = get_attr_cirrus (first);
-
- /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
- must be followed by a non-coprocessor instruction. */
- if (attr == CIRRUS_COMPARE)
- {
- nops = 0;
-
- t = next_nonnote_insn (first);
-
- if (arm_cirrus_insn_p (t))
- ++ nops;
-
- if (arm_cirrus_insn_p (next_nonnote_insn (t)))
- ++ nops;
-
- while (nops --)
- emit_insn_after (gen_nop (), first);
-
- return;
- }
-}
-
/* Return TRUE if X references a SYMBOL_REF. */
int
symbol_mentioned_p (rtx x)
@@ -13698,12 +13558,6 @@ arm_reorg (void)
/* Scan all the insns and record the operands that will need fixing. */
for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
{
- if (TARGET_CIRRUS_FIX_INVALID_INSNS
- && (arm_cirrus_insn_p (insn)
- || GET_CODE (insn) == JUMP_INSN
- || arm_memory_load_p (insn)))
- cirrus_reorg (insn);
-
if (GET_CODE (insn) == BARRIER)
push_minipool_barrier (insn, address);
else if (INSN_P (insn))
@@ -18984,18 +18838,6 @@ arm_final_prescan_insn (rtx insn)
|| GET_CODE (scanbody) == PARALLEL)
|| get_attr_conds (this_insn) != CONDS_NOCOND)
fail = TRUE;
-
- /* A conditional cirrus instruction must be followed by
- a non Cirrus instruction. However, since we
- conditionalize instructions in this function and by
- the time we get here we can't add instructions
- (nops), because shorten_branches() has already been
- called, we will disable conditionalizing Cirrus
- instructions to be safe. */
- if (GET_CODE (scanbody) != USE
- && GET_CODE (scanbody) != CLOBBER
- && get_attr_cirrus (this_insn) != CIRRUS_NOT)
- fail = TRUE;
break;
default:
Index: config/arm/t-arm
===================================================================
--- config/arm/t-arm (revision 188616)
+++ config/arm/t-arm (working copy)
@@ -29,7 +29,6 @@ MD_INCLUDES= $(srcdir)/config/arm/arm102
$(srcdir)/config/arm/arm-fixed.md \
$(srcdir)/config/arm/arm-generic.md \
$(srcdir)/config/arm/arm-tune.md \
- $(srcdir)/config/arm/cirrus.md \
$(srcdir)/config/arm/constraints.md \
$(srcdir)/config/arm/cortex-a15.md \
$(srcdir)/config/arm/cortex-a5.md \
Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md (revision 188616)
+++ config/arm/arm.md (working copy)
@@ -348,13 +348,10 @@ (define_attr "insn"
; store2 store 2 words
; store3 store 3 words
; store4 store 4 (or more) words
-; Additions for Cirrus Maverick co-processor:
-; mav_farith Floating point arithmetic (4 cycle)
-; mav_dmult Double multiplies (7 cycle)
;
(define_attr "type"
- "alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,fmuls,fmuld,fmacs,fmacd,ffmul,farith,ffarith,f_flag,float_em,f_fpa_load,f_fpa_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult,fconsts,fconstd,fadds,faddd,ffariths,ffarithd,fcmps,fcmpd,fcpys"
+ "alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,fmuls,fmuld,fmacs,fmacd,ffmul,farith,ffarith,f_flag,float_em,f_fpa_load,f_fpa_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,fconsts,fconstd,fadds,faddd,ffariths,ffarithd,fcmps,fcmpd,fcpys"
(if_then_else
(eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
(const_string "mult")
@@ -577,8 +574,6 @@ (define_attr "generic_vfp" "yes,no"
;; Note: For DImode insns, there is normally no reason why operands should
;; not be in the same register, what we don't want is for something being
;; written to partially overlap something that is an input.
-;; Cirrus 64bit additions should not be split because we have a native
-;; 64bit addition instructions.
(define_expand "adddi3"
[(parallel
@@ -588,16 +583,6 @@ (define_expand "adddi3"
(clobber (reg:CC CC_REGNUM))])]
"TARGET_EITHER"
"
- if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
- {
- if (!cirrus_fp_register (operands[0], DImode))
- operands[0] = force_reg (DImode, operands[0]);
- if (!cirrus_fp_register (operands[1], DImode))
- operands[1] = force_reg (DImode, operands[1]);
- emit_insn (gen_cirrus_adddi3 (operands[0], operands[1], operands[2]));
- DONE;
- }
-
if (TARGET_THUMB1)
{
if (GET_CODE (operands[1]) != REG)
@@ -624,7 +609,7 @@ (define_insn_and_split "*arm_adddi3"
(plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0")
(match_operand:DI 2 "s_register_operand" "r, 0")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && !TARGET_NEON"
+ "TARGET_32BIT && !TARGET_NEON"
"#"
"TARGET_32BIT && reload_completed
&& ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))"
@@ -653,7 +638,7 @@ (define_insn_and_split "*adddi_sesidi_di
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:DI 1 "s_register_operand" "0,r")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
+ "TARGET_32BIT"
"#"
"TARGET_32BIT && reload_completed"
[(parallel [(set (reg:CC_C CC_REGNUM)
@@ -682,7 +667,7 @@ (define_insn_and_split "*adddi_zesidi_di
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:DI 1 "s_register_operand" "0,r")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
+ "TARGET_32BIT"
"#"
"TARGET_32BIT && reload_completed"
[(parallel [(set (reg:CC_C CC_REGNUM)
@@ -1078,9 +1063,6 @@ (define_expand "addsf3"
(match_operand:SF 2 "arm_float_add_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"
- if (TARGET_MAVERICK
- && !cirrus_fp_register (operands[2], SFmode))
- operands[2] = force_reg (SFmode, operands[2]);
")
(define_expand "adddf3"
@@ -1089,9 +1071,6 @@ (define_expand "adddf3"
(match_operand:DF 2 "arm_float_add_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
- if (TARGET_MAVERICK
- && !cirrus_fp_register (operands[2], DFmode))
- operands[2] = force_reg (DFmode, operands[2]);
")
(define_expand "subdi3"
@@ -1102,15 +1081,6 @@ (define_expand "subdi3"
(clobber (reg:CC CC_REGNUM))])]
"TARGET_EITHER"
"
- if (TARGET_HARD_FLOAT && TARGET_MAVERICK
- && TARGET_32BIT
- && cirrus_fp_register (operands[0], DImode)
- && cirrus_fp_register (operands[1], DImode))
- {
- emit_insn (gen_cirrus_subdi3 (operands[0], operands[1], operands[2]));
- DONE;
- }
-
if (TARGET_THUMB1)
{
if (GET_CODE (operands[1]) != REG)
@@ -1325,13 +1295,6 @@ (define_expand "subsf3"
(match_operand:SF 2 "arm_float_rhs_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"
- if (TARGET_MAVERICK)
- {
- if (!cirrus_fp_register (operands[1], SFmode))
- operands[1] = force_reg (SFmode, operands[1]);
- if (!cirrus_fp_register (operands[2], SFmode))
- operands[2] = force_reg (SFmode, operands[2]);
- }
")
(define_expand "subdf3"
@@ -1340,13 +1303,6 @@ (define_expand "subdf3"
(match_operand:DF 2 "arm_float_rhs_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
- if (TARGET_MAVERICK)
- {
- if (!cirrus_fp_register (operands[1], DFmode))
- operands[1] = force_reg (DFmode, operands[1]);
- if (!cirrus_fp_register (operands[2], DFmode))
- operands[2] = force_reg (DFmode, operands[2]);
- }
")
\f
@@ -1945,9 +1901,6 @@ (define_expand "mulsf3"
(match_operand:SF 2 "arm_float_rhs_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"
- if (TARGET_MAVERICK
- && !cirrus_fp_register (operands[2], SFmode))
- operands[2] = force_reg (SFmode, operands[2]);
")
(define_expand "muldf3"
@@ -1956,9 +1909,6 @@ (define_expand "muldf3"
(match_operand:DF 2 "arm_float_rhs_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
- if (TARGET_MAVERICK
- && !cirrus_fp_register (operands[2], DFmode))
- operands[2] = force_reg (DFmode, operands[2]);
")
\f
;; Division insns
@@ -3514,8 +3464,7 @@ (define_expand "ashldi3"
(match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_32BIT"
"
- if (!CONST_INT_P (operands[2])
- && (TARGET_REALLY_IWMMXT || (TARGET_HARD_FLOAT && TARGET_MAVERICK)))
+ if (!CONST_INT_P (operands[2]) && TARGET_REALLY_IWMMXT)
; /* No special preparation statements; expand pattern as above. */
else
{
@@ -3589,8 +3538,7 @@ (define_expand "ashrdi3"
(match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_32BIT"
"
- if (!CONST_INT_P (operands[2])
- && (TARGET_REALLY_IWMMXT || (TARGET_HARD_FLOAT && TARGET_MAVERICK)))
+ if (!CONST_INT_P (operands[2]) && TARGET_REALLY_IWMMXT)
; /* No special preparation statements; expand pattern as above. */
else
{
@@ -3662,8 +3610,7 @@ (define_expand "lshrdi3"
(match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_32BIT"
"
- if (!CONST_INT_P (operands[2])
- && (TARGET_REALLY_IWMMXT || (TARGET_HARD_FLOAT && TARGET_MAVERICK)))
+ if (!CONST_INT_P (operands[2]) && TARGET_REALLY_IWMMXT)
; /* No special preparation statements; expand pattern as above. */
else
{
@@ -4417,11 +4364,6 @@ (define_expand "floatsisf2"
(float:SF (match_operand:SI 1 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"
- if (TARGET_MAVERICK)
- {
- emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1]));
- DONE;
- }
")
(define_expand "floatsidf2"
@@ -4429,11 +4371,6 @@ (define_expand "floatsidf2"
(float:DF (match_operand:SI 1 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
- if (TARGET_MAVERICK)
- {
- emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1]));
- DONE;
- }
")
(define_expand "fix_trunchfsi2"
@@ -4465,15 +4402,6 @@ (define_expand "fix_truncsfsi2"
(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"
- if (TARGET_MAVERICK)
- {
- if (!cirrus_fp_register (operands[0], SImode))
- operands[0] = force_reg (SImode, operands[0]);
- if (!cirrus_fp_register (operands[1], SFmode))
- operands[1] = force_reg (SFmode, operands[0]);
- emit_insn (gen_cirrus_truncsfsi2 (operands[0], operands[1]));
- DONE;
- }
")
(define_expand "fix_truncdfsi2"
@@ -4481,13 +4409,6 @@ (define_expand "fix_truncdfsi2"
(fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))]
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
- if (TARGET_MAVERICK)
- {
- if (!cirrus_fp_register (operands[1], DFmode))
- operands[1] = force_reg (DFmode, operands[0]);
- emit_insn (gen_cirrus_truncdfsi2 (operands[0], operands[1]));
- DONE;
- }
")
;; Truncation insns
@@ -5341,7 +5262,7 @@ (define_insn "*arm_movdi"
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
(match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))]
"TARGET_32BIT
- && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP))
+ && !(TARGET_HARD_FLOAT && TARGET_VFP)
&& !TARGET_IWMMXT
&& ( register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
@@ -5463,7 +5384,6 @@ (define_insn "*thumb1_movdi_insn"
[(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r")
(match_operand:DI 1 "general_operand" "l, I,J,>,l,mi,l,*r"))]
"TARGET_THUMB1
- && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)
&& ( register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
"*
@@ -7664,7 +7584,7 @@ (define_insn "*arm_cmpdi_insn"
(compare:CC_NCV (match_operand:DI 0 "s_register_operand" "r")
(match_operand:DI 1 "arm_di_operand" "rDi")))
(clobber (match_scratch:SI 2 "=r"))]
- "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
+ "TARGET_32BIT"
"cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1"
[(set_attr "conds" "set")
(set_attr "length" "8")]
@@ -7701,38 +7621,6 @@ (define_insn "*thumb_cmpdi_zero"
(set_attr "length" "2")]
)
-;; Cirrus SF compare instruction
-(define_insn "*cirrus_cmpsf"
- [(set (reg:CCFP CC_REGNUM)
- (compare:CCFP (match_operand:SF 0 "cirrus_fp_register" "v")
- (match_operand:SF 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfcmps%?\\tr15, %V0, %V1"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "compare")]
-)
-
-;; Cirrus DF compare instruction
-(define_insn "*cirrus_cmpdf"
- [(set (reg:CCFP CC_REGNUM)
- (compare:CCFP (match_operand:DF 0 "cirrus_fp_register" "v")
- (match_operand:DF 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfcmpd%?\\tr15, %V0, %V1"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "compare")]
-)
-
-(define_insn "*cirrus_cmpdi"
- [(set (reg:CC CC_REGNUM)
- (compare:CC (match_operand:DI 0 "cirrus_fp_register" "v")
- (match_operand:DI 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfcmp64%?\\tr15, %V0, %V1"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "compare")]
-)
-
; This insn allows redundant compares to be removed by cse, nothing should
; ever appear in the output file since (set (reg x) (reg x)) is a no-op that
; is deleted later on. The match_dup will match the mode here, so that
@@ -11406,8 +11294,6 @@ (define_expand "bswapsi2"
;; Load the load/store multiple patterns
(include "ldmstm.md")
-;; Load the Maverick co-processor patterns
-(include "cirrus.md")
;; Vector bits common to IWMMXT and Neon
(include "vec-common.md")
;; Load the Intel Wireless Multimedia Extension patterns
Index: config/arm/cirrus.md
===================================================================
--- config/arm/cirrus.md (revision 188614)
+++ config/arm/cirrus.md (working copy)
@@ -1,540 +0,0 @@
-;; CIRRUS EP9312 "Maverick" ARM floating point co-processor description.
-;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
-;; Contributed by Red Hat.
-;; Written by Aldy Hernandez (aldyh@redhat.com)
-
-;; This file is part of GCC.
-
-;; GCC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 3, or (at your option)
-;; any later version.
-
-;; GCC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING3. If not see
-;; <http://www.gnu.org/licenses/>.
-
-
-; Cirrus types for invalid insn combinations
-; not Not a cirrus insn
-; normal Any Cirrus insn not covered by the special cases below
-; double cfldrd, cfldr64, cfstrd, cfstr64
-; compare cfcmps, cfcmpd, cfcmp32, cfcmp64
-; move cfmvdlr, cfmvdhr, cfmvsr, cfmv64lr, cfmv64hr
-(define_attr "cirrus" "not,normal,double,compare,move" (const_string "not"))
-
-\f
-(define_insn "cirrus_adddi3"
- [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
- (plus:DI (match_operand:DI 1 "cirrus_fp_register" "v")
- (match_operand:DI 2 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfadd64%?\\t%V0, %V1, %V2"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_addsi3"
- [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
- (plus:SI (match_operand:SI 1 "cirrus_fp_register" "v")
- (match_operand:SI 2 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
- "cfadd32%?\\t%V0, %V1, %V2"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_addsf3"
- [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
- (plus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
- (match_operand:SF 2 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfadds%?\\t%V0, %V1, %V2"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_adddf3"
- [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
- (plus:DF (match_operand:DF 1 "cirrus_fp_register" "v")
- (match_operand:DF 2 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfaddd%?\\t%V0, %V1, %V2"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "normal")]
-)
-
-(define_insn "cirrus_subdi3"
- [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
- (minus:DI (match_operand:DI 1 "cirrus_fp_register" "v")
- (match_operand:DI 2 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfsub64%?\\t%V0, %V1, %V2"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_subsi3_insn"
- [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
- (minus:SI (match_operand:SI 1 "cirrus_fp_register" "v")
- (match_operand:SI 2 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
- "cfsub32%?\\t%V0, %V1, %V2"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_subsf3"
- [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
- (minus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
- (match_operand:SF 2 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfsubs%?\\t%V0, %V1, %V2"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_subdf3"
- [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
- (minus:DF (match_operand:DF 1 "cirrus_fp_register" "v")
- (match_operand:DF 2 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfsubd%?\\t%V0, %V1, %V2"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_mulsi3"
- [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
- (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v")
- (match_operand:SI 1 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
- "cfmul32%?\\t%V0, %V1, %V2"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "normal")]
-)
-
-(define_insn "muldi3"
- [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
- (mult:DI (match_operand:DI 2 "cirrus_fp_register" "v")
- (match_operand:DI 1 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfmul64%?\\t%V0, %V1, %V2"
- [(set_attr "type" "mav_dmult")
- (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_mulsi3addsi"
- [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
- (plus:SI
- (mult:SI (match_operand:SI 1 "cirrus_fp_register" "v")
- (match_operand:SI 2 "cirrus_fp_register" "v"))
- (match_operand:SI 3 "cirrus_fp_register" "0")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
- "cfmac32%?\\t%V0, %V1, %V2"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "normal")]
-)
-
-;; Cirrus SI multiply-subtract
-(define_insn "*cirrus_mulsi3subsi"
- [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
- (minus:SI
- (match_operand:SI 1 "cirrus_fp_register" "0")
- (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v")
- (match_operand:SI 3 "cirrus_fp_register" "v"))))]
- "0 && TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfmsc32%?\\t%V0, %V2, %V3"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_mulsf3"
- [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
- (mult:SF (match_operand:SF 1 "cirrus_fp_register" "v")
- (match_operand:SF 2 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfmuls%?\\t%V0, %V1, %V2"
- [(set_attr "type" "mav_farith")
- (set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_muldf3"
- [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
- (mult:DF (match_operand:DF 1 "cirrus_fp_register" "v")
- (match_operand:DF 2 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfmuld%?\\t%V0, %V1, %V2"
- [(set_attr "type" "mav_dmult")
- (set_attr "cirrus" "normal")]
-)
-
-(define_insn "cirrus_ashl_const"
- [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
- (ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v")
- (match_operand:SI 2 "cirrus_shift_const" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
- "cfsh32%?\\t%V0, %V1, #%s2"
- [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "cirrus_ashiftrt_const"
- [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
- (ashiftrt:SI (match_operand:SI 1 "cirrus_fp_register" "v")
- (match_operand:SI 2 "cirrus_shift_const" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
- "cfsh32%?\\t%V0, %V1, #-%s2"
- [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "cirrus_ashlsi3"
- [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
- (ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v")
- (match_operand:SI 2 "register_operand" "r")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
- "cfrshl32%?\\t%V1, %V0, %s2"
- [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "ashldi3_cirrus"
- [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
- (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v")
- (match_operand:SI 2 "register_operand" "r")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfrshl64%?\\t%V1, %V0, %s2"
- [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "cirrus_ashldi_const"
- [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
- (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v")
- (match_operand:SI 2 "cirrus_shift_const" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfsh64%?\\t%V0, %V1, #%s2"
- [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "cirrus_ashiftrtdi_const"
- [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
- (ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v")
- (match_operand:SI 2 "cirrus_shift_const" "")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfsh64%?\\t%V0, %V1, #-%s2"
- [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_absdi2"
- [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
- (abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfabs64%?\\t%V0, %V1"
- [(set_attr "cirrus" "normal")]
-)
-
-;; This doesn't really clobber ``cc''. Fixme: aldyh.
-(define_insn "*cirrus_negdi2"
- [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
- (neg:DI (match_operand:DI 1 "cirrus_fp_register" "v")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfneg64%?\\t%V0, %V1"
- [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_negsi2"
- [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
- (neg:SI (match_operand:SI 1 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
- "cfneg32%?\\t%V0, %V1"
- [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_negsf2"
- [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
- (neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfnegs%?\\t%V0, %V1"
- [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_negdf2"
- [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
- (neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfnegd%?\\t%V0, %V1"
- [(set_attr "cirrus" "normal")]
-)
-
-;; This doesn't really clobber the condition codes either.
-(define_insn "*cirrus_abssi2"
- [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
- (abs:SI (match_operand:SI 1 "cirrus_fp_register" "v")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
- "cfabs32%?\\t%V0, %V1"
- [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_abssf2"
- [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
- (abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfabss%?\\t%V0, %V1"
- [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_absdf2"
- [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
- (abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfabsd%?\\t%V0, %V1"
- [(set_attr "cirrus" "normal")]
-)
-
-;; Convert Cirrus-SI to Cirrus-SF
-(define_insn "cirrus_floatsisf2"
- [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
- (float:SF (match_operand:SI 1 "s_register_operand" "r")))
- (clobber (match_scratch:DF 2 "=v"))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2"
- [(set_attr "length" "8")
- (set_attr "cirrus" "move")]
-)
-
-(define_insn "cirrus_floatsidf2"
- [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
- (float:DF (match_operand:SI 1 "s_register_operand" "r")))
- (clobber (match_scratch:DF 2 "=v"))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2"
- [(set_attr "length" "8")
- (set_attr "cirrus" "move")]
-)
-
-(define_insn "floatdisf2"
- [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
- (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfcvt64s%?\\t%V0, %V1"
- [(set_attr "cirrus" "normal")])
-
-(define_insn "floatdidf2"
- [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
- (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfcvt64d%?\\t%V0, %V1"
- [(set_attr "cirrus" "normal")])
-
-(define_insn "cirrus_truncsfsi2"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v"))))
- (clobber (match_scratch:DF 2 "=v"))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
- [(set_attr "length" "8")
- (set_attr "cirrus" "normal")]
-)
-
-(define_insn "cirrus_truncdfsi2"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v"))))
- (clobber (match_scratch:DF 2 "=v"))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
- [(set_attr "length" "8")]
-)
-
-(define_insn "*cirrus_truncdfsf2"
- [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
- (float_truncate:SF
- (match_operand:DF 1 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfcvtds%?\\t%V0, %V1"
- [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_extendsfdf2"
- [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
- (float_extend:DF (match_operand:SF 1 "cirrus_fp_register" "v")))]
- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "cfcvtsd%?\\t%V0, %V1"
- [(set_attr "cirrus" "normal")]
-)
-
-(define_insn "*cirrus_arm_movdi"
- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
- (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "*
- {
- switch (which_alternative)
- {
- case 0:
- return \"#\";
- case 1:
- case 2:
- return output_move_double (operands, true, NULL);
-
- case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\";
- case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\";
-
- case 5: return \"cfldr64%?\\t%V0, %1\";
- case 6: return \"cfstr64%?\\t%V1, %0\";
-
- /* Shifting by 0 will just copy %1 into %0. */
- case 7: return \"cfsh64%?\\t%V0, %V1, #0\";
-
- default: gcc_unreachable ();
- }
- }"
- [(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4")
- (set_attr "type" " *,load2,store2, *, *, load2,store2, *")
- (set_attr "pool_range" " *,1020, *, *, *, 1020, *, *")
- (set_attr "neg_pool_range" " *,1012, *, *, *, 1008, *, *")
- (set_attr "cirrus" "not, not, not,move,normal,double,double,normal")]
-)
-
-;; Cirrus SI values have been outlawed. Look in arm.h for the comment
-;; on HARD_REGNO_MODE_OK.
-
-(define_insn "*cirrus_movsf_hard_insn"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m")
- (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK
- && (GET_CODE (operands[0]) != MEM
- || register_operand (operands[1], SFmode))"
- "@
- cfcpys%?\\t%V0, %V1
- cfldrs%?\\t%V0, %1
- cfmvsr%?\\t%V0, %1
- cfmvrs%?\\t%0, %V1
- cfstrs%?\\t%V1, %0
- mov%?\\t%0, %1
- ldr%?\\t%0, %1\\t%@ float
- str%?\\t%1, %0\\t%@ float"
- [(set_attr "length" " *, *, *, *, *, 4, 4, 4")
- (set_attr "type" " *, load1, *, *,store1, *,load1,store1")
- (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *")
- (set_attr "neg_pool_range" " *, 1008, *, *, *, *,4084, *")
- (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")]
-)
-
-(define_insn "*cirrus_movdf_hard_insn"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m")
- (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))]
- "TARGET_ARM
- && TARGET_HARD_FLOAT && TARGET_MAVERICK
- && (GET_CODE (operands[0]) != MEM
- || register_operand (operands[1], DFmode))"
- "*
- {
- switch (which_alternative)
- {
- case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
- case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
- case 2: return \"#\";
- case 3: case 4: return output_move_double (operands, true, NULL);
- case 5: return \"cfcpyd%?\\t%V0, %V1\";
- case 6: return \"cfldrd%?\\t%V0, %1\";
- case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\";
- case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\";
- case 9: return \"cfstrd%?\\t%V1, %0\";
- default: gcc_unreachable ();
- }
- }"
- [(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2")
- (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4")
- (set_attr "pool_range" " *, *, *, *, 252, *, 1020, *, *, *")
- (set_attr "neg_pool_range" " *, *, *, *, 244, *, 1008, *, *, *")
- (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")]
-)
-
-(define_insn "*cirrus_thumb2_movdi"
- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
- (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))]
- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "*
- {
- switch (which_alternative)
- {
- case 0:
- case 1:
- case 2:
- return (output_move_double (operands, true, NULL));
-
- case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\";
- case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\";
-
- case 5: return \"cfldr64%?\\t%V0, %1\";
- case 6: return \"cfstr64%?\\t%V1, %0\";
-
- /* Shifting by 0 will just copy %1 into %0. */
- case 7: return \"cfsh64%?\\t%V0, %V1, #0\";
-
- default: abort ();
- }
- }"
- [(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4")
- (set_attr "type" " *,load2,store2, *, *, load2,store2, *")
- (set_attr "pool_range" " *,4096, *, *, *, 1020, *, *")
- (set_attr "neg_pool_range" " *, 0, *, *, *, 1008, *, *")
- (set_attr "cirrus" "not, not, not,move,normal,double,double,normal")]
-)
-
-(define_insn "*thumb2_cirrus_movsf_hard_insn"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m")
- (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))]
- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_MAVERICK
- && (GET_CODE (operands[0]) != MEM
- || register_operand (operands[1], SFmode))"
- "@
- cfcpys%?\\t%V0, %V1
- cfldrs%?\\t%V0, %1
- cfmvsr%?\\t%V0, %1
- cfmvrs%?\\t%0, %V1
- cfstrs%?\\t%V1, %0
- mov%?\\t%0, %1
- ldr%?\\t%0, %1\\t%@ float
- str%?\\t%1, %0\\t%@ float"
- [(set_attr "length" " *, *, *, *, *, 4, 4, 4")
- (set_attr "type" " *, load1, *, *,store1, *,load1,store1")
- (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *")
- (set_attr "neg_pool_range" " *, 1008, *, *, *, *, 0, *")
- (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")]
-)
-
-(define_insn "*thumb2_cirrus_movdf_hard_insn"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m")
- (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))]
- "TARGET_THUMB2
- && TARGET_HARD_FLOAT && TARGET_MAVERICK
- && (GET_CODE (operands[0]) != MEM
- || register_operand (operands[1], DFmode))"
- "*
- {
- switch (which_alternative)
- {
- case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
- case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
- case 2: case 3: case 4: return output_move_double (operands, true, NULL);
- case 5: return \"cfcpyd%?\\t%V0, %V1\";
- case 6: return \"cfldrd%?\\t%V0, %1\";
- case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\";
- case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\";
- case 9: return \"cfstrd%?\\t%V1, %0\";
- default: abort ();
- }
- }"
- [(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2")
- (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4")
- (set_attr "pool_range" " *, *, *, *,4092, *, 1020, *, *, *")
- (set_attr "neg_pool_range" " *, *, *, *, 0, *, 1008, *, *, *")
- (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")]
-)
-
^ permalink raw reply [flat|nested] 8+ messages in thread
* [arm] Remove obsolete FPA support (5/n): Clean up predicates and constraints
2012-06-14 9:40 [arm] Remove obsolete FPA support (2/n): Remove command-line options Richard Earnshaw
2012-06-14 14:43 ` [arm] Remove obsolete FPA support (3/n): Remove FPA patterns from MD files Richard Earnshaw
2012-06-14 16:54 ` [arm] Remove obsolete FPA support (4/n): Remove Maverick " Richard Earnshaw
@ 2012-06-15 14:16 ` Richard Earnshaw
2012-06-18 1:59 ` [arm] Remove obsolete FPA support (2/n): Remove command-line options Gerald Pfeifer
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Richard Earnshaw @ 2012-06-15 14:16 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1126 bytes --]
This patch cleans up the predicates and constraints that are now
redundant after the removal of FPA and Maverick co-processor support.
Tested on arm-eabi.
* arm.md (addsf3, adddf3): Use s_register_operand.
(subsf3, subdf3): Likewise.
(mulsf3, muldf3): Likewise.
(difsf3, divdf3): Likewise.
(movsfcc, movdfcc): Likewise.
* predicates.md (f_register_operand): Delete.
(arm_float_rhs_operand): Delete.
(arm_float_add_operand): Delete.
(arm_float_compare_operand): Use s_register_operand when
there's no VFP.
(cirrus_register_operand): Delete.
(cirrus_fp_register): Delete.
(cirrus_shift_const): Delete.
(cmpdi_operand): Remove Maverick support.
* constraints.md (f, v, H): Delete constraints.
(G): Update documentation.
* arm.c (fp_consts_inited): Convert to bool.
(strings_fp): Delete.
(values_fp): Delete.
(value_fp0): New variable.
(init_fp_table): Simplify logic.
(arm_const_double_rtx): Likewise.
(fp_immediate_constant): Likewise.
(fp_const_from_val): Likewise.
(neg_const_double_rtx_ok_for_fpa): Delete.
* doc/md.texi (ARM constraints): Update documentation.
R.
[-- Attachment #2: nofpa5.patch --]
[-- Type: text/plain, Size: 13575 bytes --]
Index: doc/md.texi
===================================================================
--- doc/md.texi (revision 188621)
+++ doc/md.texi (working copy)
@@ -1653,21 +1653,13 @@ table heading for each architecture is t
the meanings of that architecture's constraints.
@table @emph
-@item ARM family---@file{config/arm/arm.h}
+@item ARM family---@file{config/arm/constraints.md}
@table @code
-@item f
-Floating-point register
-
@item w
VFP floating-point register
-@item F
-One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
-or 10.0
-
@item G
-Floating-point constant that would satisfy the constraint @samp{F} if it
-were negated
+The floating-point constant 0.0
@item I
Integer that is valid as an immediate operand in a data processing
Index: config/arm/arm.c
===================================================================
--- config/arm/arm.c (revision 188622)
+++ config/arm/arm.c (working copy)
@@ -8676,33 +8676,18 @@ arm_cortex_a5_branch_cost (bool speed_p,
return speed_p ? 0 : arm_default_branch_cost (speed_p, predictable_p);
}
-static int fp_consts_inited = 0;
+static bool fp_consts_inited = false;
-/* Only zero is valid for VFP. Other values are also valid for FPA. */
-static const char * const strings_fp[8] =
-{
- "0", "1", "2", "3",
- "4", "5", "0.5", "10"
-};
-
-static REAL_VALUE_TYPE values_fp[8];
+static REAL_VALUE_TYPE value_fp0;
static void
init_fp_table (void)
{
- int i;
REAL_VALUE_TYPE r;
- if (TARGET_VFP)
- fp_consts_inited = 1;
- else
- fp_consts_inited = 8;
-
- for (i = 0; i < fp_consts_inited; i++)
- {
- r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
- values_fp[i] = r;
- }
+ r = REAL_VALUE_ATOF ("0", DFmode);
+ value_fp0 = r;
+ fp_consts_inited = true;
}
/* Return TRUE if rtx X is a valid immediate FP constant. */
@@ -8719,36 +8704,12 @@ arm_const_double_rtx (rtx x)
if (REAL_VALUE_MINUS_ZERO (r))
return 0;
- for (i = 0; i < fp_consts_inited; i++)
- if (REAL_VALUES_EQUAL (r, values_fp[i]))
- return 1;
-
- return 0;
-}
-
-/* Return TRUE if rtx X is a valid immediate FPA constant. */
-int
-neg_const_double_rtx_ok_for_fpa (rtx x)
-{
- REAL_VALUE_TYPE r;
- int i;
-
- if (!fp_consts_inited)
- init_fp_table ();
-
- REAL_VALUE_FROM_CONST_DOUBLE (r, x);
- r = real_value_negate (&r);
- if (REAL_VALUE_MINUS_ZERO (r))
- return 0;
-
- for (i = 0; i < 8; i++)
- if (REAL_VALUES_EQUAL (r, values_fp[i]))
- return 1;
+ if (REAL_VALUES_EQUAL (r, value_fp0))
+ return 1;
return 0;
}
-
/* VFPv3 has a fairly wide range of representable immediates, formed from
"quarter-precision" floating-point values. These can be evaluated using this
formula (with ^ for exponentiation):
@@ -13715,11 +13676,9 @@ fp_immediate_constant (rtx x)
init_fp_table ();
REAL_VALUE_FROM_CONST_DOUBLE (r, x);
- for (i = 0; i < 8; i++)
- if (REAL_VALUES_EQUAL (r, values_fp[i]))
- return strings_fp[i];
- gcc_unreachable ();
+ gcc_assert (REAL_VALUES_EQUAL (r, value_fp0));
+ return "0";
}
/* As for fp_immediate_constant, but value is passed directly, not in rtx. */
@@ -13731,11 +13690,8 @@ fp_const_from_val (REAL_VALUE_TYPE *r)
if (!fp_consts_inited)
init_fp_table ();
- for (i = 0; i < 8; i++)
- if (REAL_VALUES_EQUAL (*r, values_fp[i]))
- return strings_fp[i];
-
- gcc_unreachable ();
+ gcc_assert (REAL_VALUES_EQUAL (*r, value_fp0));
+ return "0";
}
/* Output the operands of a LDM/STM instruction to STREAM.
Index: config/arm/constraints.md
===================================================================
--- config/arm/constraints.md (revision 188621)
+++ config/arm/constraints.md (working copy)
@@ -19,14 +19,16 @@
;; <http://www.gnu.org/licenses/>.
;; The following register constraints have been used:
-;; - in ARM/Thumb-2 state: f, t, v, w, x, y, z
+;; - in ARM/Thumb-2 state: t, w, x, y, z
;; - in Thumb state: h, b
;; - in both states: l, c, k
;; In ARM state, 'l' is an alias for 'r'
+;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
;; The following normal constraints have been used:
-;; in ARM/Thumb-2 state: G, H, I, j, J, K, L, M
+;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
;; in Thumb-1 state: I, J, K, L, M, N, O
+;; 'H' was previously used for FPA.
;; The following multi-letter normal constraints have been used:
;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
@@ -39,15 +41,9 @@
;; in Thumb state: Uu, Uw
-(define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS"
- "Legacy FPA registers @code{f0}-@code{f7}.")
-
(define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
"The VFP registers @code{s0}-@code{s31}.")
-(define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS"
- "The Cirrus Maverick co-processor registers.")
-
(define_register_constraint "w"
"TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
"The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
@@ -213,15 +209,10 @@ (define_constraint "Py"
(match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
(define_constraint "G"
- "In ARM/Thumb-2 state a valid FPA immediate constant."
+ "In ARM/Thumb-2 state the floating-point constant 0."
(and (match_code "const_double")
(match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
-(define_constraint "H"
- "In ARM/Thumb-2 state a valid FPA immediate constant when negated."
- (and (match_code "const_double")
- (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))
-
(define_constraint "Dz"
"@internal
In ARM/Thumb-2 state a vector of constant zeros."
Index: config/arm/predicates.md
===================================================================
--- config/arm/predicates.md (revision 188621)
+++ config/arm/predicates.md (working copy)
@@ -60,19 +60,6 @@ (define_predicate "arm_general_register_
|| REGNO (op) >= FIRST_PSEUDO_REGISTER));
})
-(define_predicate "f_register_operand"
- (match_code "reg,subreg")
-{
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- /* We don't consider registers whose class is NO_REGS
- to be a register operand. */
- return (GET_CODE (op) == REG
- && (REGNO (op) >= FIRST_PSEUDO_REGISTER
- || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
-})
-
(define_predicate "vfp_register_operand"
(match_code "reg,subreg")
{
@@ -189,18 +176,6 @@ (define_predicate "arm_reload_memory_ope
|| (GET_CODE (op) == REG
&& REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
-;; True for valid operands for the rhs of an floating point insns.
-;; Allows regs or certain consts on FPA, just regs for everything else.
-(define_predicate "arm_float_rhs_operand"
- (ior (match_operand 0 "s_register_operand")
- (and (match_code "const_double")
- (match_test "TARGET_FPA && arm_const_double_rtx (op)"))))
-
-(define_predicate "arm_float_add_operand"
- (ior (match_operand 0 "arm_float_rhs_operand")
- (and (match_code "const_double")
- (match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)"))))
-
(define_predicate "vfp_compare_operand"
(ior (match_operand 0 "s_register_operand")
(and (match_code "const_double")
@@ -209,7 +184,7 @@ (define_predicate "vfp_compare_operand"
(define_predicate "arm_float_compare_operand"
(if_then_else (match_test "TARGET_VFP")
(match_operand 0 "vfp_compare_operand")
- (match_operand 0 "arm_float_rhs_operand")))
+ (match_operand 0 "s_register_operand")))
;; True for valid index operands.
(define_predicate "index_operand"
@@ -464,36 +439,8 @@ (define_predicate "thumb_cbrch_target_op
;;-------------------------------------------------------------------------
;;
-;; MAVERICK predicates
-;;
-
-(define_predicate "cirrus_register_operand"
- (match_code "reg,subreg")
-{
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- return (GET_CODE (op) == REG
- && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
- || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
-})
-
-(define_predicate "cirrus_fp_register"
- (match_code "reg,subreg")
-{
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- return (GET_CODE (op) == REG
- && (REGNO (op) >= FIRST_PSEUDO_REGISTER
- || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
-})
-
-(define_predicate "cirrus_shift_const"
- (and (match_code "const_int")
- (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))
-
;; iWMMXt predicates
+;;
(define_predicate "imm_or_reg_operand"
(ior (match_operand 0 "immediate_operand")
@@ -563,11 +510,8 @@ (define_predicate "neon_lane_number"
;; Predicates for named expanders that overlap multiple ISAs.
(define_predicate "cmpdi_operand"
- (if_then_else (match_test "TARGET_HARD_FLOAT && TARGET_MAVERICK")
- (and (match_test "TARGET_ARM")
- (match_operand 0 "cirrus_fp_register"))
- (and (match_test "TARGET_32BIT")
- (match_operand 0 "arm_di_operand"))))
+ (and (match_test "TARGET_32BIT")
+ (match_operand 0 "arm_di_operand")))
;; True if the operand is memory reference suitable for a ldrex/strex.
(define_predicate "arm_sync_memory_operand"
Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md (revision 188622)
+++ config/arm/arm.md (working copy)
@@ -1060,7 +1060,7 @@ (define_split
(define_expand "addsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
(plus:SF (match_operand:SF 1 "s_register_operand" "")
- (match_operand:SF 2 "arm_float_add_operand" "")))]
+ (match_operand:SF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"
")
@@ -1068,7 +1068,7 @@ (define_expand "addsf3"
(define_expand "adddf3"
[(set (match_operand:DF 0 "s_register_operand" "")
(plus:DF (match_operand:DF 1 "s_register_operand" "")
- (match_operand:DF 2 "arm_float_add_operand" "")))]
+ (match_operand:DF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
")
@@ -1291,16 +1291,16 @@ (define_insn "*arm_decscc"
(define_expand "subsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
- (minus:SF (match_operand:SF 1 "arm_float_rhs_operand" "")
- (match_operand:SF 2 "arm_float_rhs_operand" "")))]
+ (minus:SF (match_operand:SF 1 "s_register_operand" "")
+ (match_operand:SF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"
")
(define_expand "subdf3"
[(set (match_operand:DF 0 "s_register_operand" "")
- (minus:DF (match_operand:DF 1 "arm_float_rhs_operand" "")
- (match_operand:DF 2 "arm_float_rhs_operand" "")))]
+ (minus:DF (match_operand:DF 1 "s_register_operand" "")
+ (match_operand:DF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
")
@@ -1898,7 +1898,7 @@ (define_insn "*maddhidi4tt"
(define_expand "mulsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
(mult:SF (match_operand:SF 1 "s_register_operand" "")
- (match_operand:SF 2 "arm_float_rhs_operand" "")))]
+ (match_operand:SF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"
")
@@ -1906,7 +1906,7 @@ (define_expand "mulsf3"
(define_expand "muldf3"
[(set (match_operand:DF 0 "s_register_operand" "")
(mult:DF (match_operand:DF 1 "s_register_operand" "")
- (match_operand:DF 2 "arm_float_rhs_operand" "")))]
+ (match_operand:DF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
")
@@ -1915,15 +1915,15 @@ (define_expand "muldf3"
(define_expand "divsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
- (div:SF (match_operand:SF 1 "arm_float_rhs_operand" "")
- (match_operand:SF 2 "arm_float_rhs_operand" "")))]
+ (div:SF (match_operand:SF 1 "s_register_operand" "")
+ (match_operand:SF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"")
(define_expand "divdf3"
[(set (match_operand:DF 0 "s_register_operand" "")
- (div:DF (match_operand:DF 1 "arm_float_rhs_operand" "")
- (match_operand:DF 2 "arm_float_rhs_operand" "")))]
+ (div:DF (match_operand:DF 1 "s_register_operand" "")
+ (match_operand:DF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"")
\f
@@ -8037,7 +8037,7 @@ (define_expand "movsfcc"
[(set (match_operand:SF 0 "s_register_operand" "")
(if_then_else:SF (match_operand 1 "expandable_comparison_operator" "")
(match_operand:SF 2 "s_register_operand" "")
- (match_operand:SF 3 "arm_float_add_operand" "")))]
+ (match_operand:SF 3 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"
{
@@ -8059,7 +8059,7 @@ (define_expand "movdfcc"
[(set (match_operand:DF 0 "s_register_operand" "")
(if_then_else:DF (match_operand 1 "expandable_comparison_operator" "")
(match_operand:DF 2 "s_register_operand" "")
- (match_operand:DF 3 "arm_float_add_operand" "")))]
+ (match_operand:DF 3 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"
{
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [arm] Remove obsolete FPA support (2/n): Remove command-line options
2012-06-14 9:40 [arm] Remove obsolete FPA support (2/n): Remove command-line options Richard Earnshaw
` (2 preceding siblings ...)
2012-06-15 14:16 ` [arm] Remove obsolete FPA support (5/n): Clean up predicates and constraints Richard Earnshaw
@ 2012-06-18 1:59 ` Gerald Pfeifer
2012-06-18 15:39 ` [arm] Remove obsolete FPA support (6/n): fix warnings Richard Earnshaw
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Gerald Pfeifer @ 2012-06-18 1:59 UTC (permalink / raw)
To: Richard Earnshaw; +Cc: gcc-patches
On Thu, 14 Jun 2012, Richard Earnshaw wrote:
> This patch removes the command line options that enabled generation of
> FPA and maverick instructions, along with their associated documentation.
>
> * arm.opt (mfp=2, mfp=3, mfpe, mfpe=2, mfpe=3): Delete options.
> * arm-fpus.def (fpa, fpe2, fpe3, maverick): Delete FPU types.
> * arm-tables.opt: Regenerated.
> * doc/invoke.texi: Remove references to deleted options.
gcc-4.8/changes.html, please? :-)
If you prefer to provide raw text describing the change, I can
take it from there.
Gerald
^ permalink raw reply [flat|nested] 8+ messages in thread
* [arm] Remove obsolete FPA support (6/n): fix warnings
2012-06-14 9:40 [arm] Remove obsolete FPA support (2/n): Remove command-line options Richard Earnshaw
` (3 preceding siblings ...)
2012-06-18 1:59 ` [arm] Remove obsolete FPA support (2/n): Remove command-line options Gerald Pfeifer
@ 2012-06-18 15:39 ` Richard Earnshaw
2012-06-19 14:16 ` [arm] Remove obsolete FPA support (7/n): Tidy up attributes Richard Earnshaw
2012-07-07 16:45 ` [arm] Remove obsolete FPA support (8/n): Cleanup addressing and register usage Richard Earnshaw
6 siblings, 0 replies; 8+ messages in thread
From: Richard Earnshaw @ 2012-06-18 15:39 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 681 bytes --]
[I composed this message on Friday, before I left for the weekend, but
somehow forgot to press send. The good news is that as a result I can
now confirm that this has fixed the outstanding bootstrap issue.]
This patch cleans up some build warnings that break native bootstrap.
One of the warnings wasn't related to my changes (the iwmmxt one), but
the rest are mine. Mea culpa!
* arm.c (note_invalid_constants): Don't return a result.
(arm_memory_load_p): Delete function.
(arm_const_double_rtx): Delete iterator variable i;
(fp_immediate_constant): Likewise.
(fp_const_from_val): Likewise.
* arm.c (arm_init_iwmmxt_builtins): Delete void_ftype_void.
R.
[-- Attachment #2: nofpa6.patch --]
[-- Type: text/plain, Size: 4718 bytes --]
Index: arm.c
===================================================================
--- arm.c (revision 188662)
+++ arm.c (working copy)
@@ -117,7 +117,7 @@ static void push_minipool_barrier (rtx,
static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
rtx);
static void arm_reorg (void);
-static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
+static void note_invalid_constants (rtx, HOST_WIDE_INT, int);
static unsigned long arm_compute_save_reg0_reg12_mask (void);
static unsigned long arm_compute_save_reg_mask (void);
static unsigned long arm_isr_value (tree);
@@ -166,7 +166,6 @@ static bool arm_rtx_costs (rtx, int, int
static int arm_address_cost (rtx, bool);
static int arm_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
static int arm_memory_move_cost (enum machine_mode, reg_class_t, bool);
-static bool arm_memory_load_p (rtx);
static void arm_init_builtins (void);
static void arm_init_iwmmxt_builtins (void);
static rtx safe_vector_operand (rtx, enum machine_mode);
@@ -8695,7 +8694,6 @@ int
arm_const_double_rtx (rtx x)
{
REAL_VALUE_TYPE r;
- int i;
if (!fp_consts_inited)
init_fp_table ();
@@ -9745,41 +9743,6 @@ arm_return_in_msb (const_tree valtype)
|| FIXED_POINT_TYPE_P (valtype)));
}
-/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
- Use by the Cirrus Maverick code which has to workaround
- a hardware bug triggered by such instructions. */
-static bool
-arm_memory_load_p (rtx insn)
-{
- rtx body, lhs, rhs;;
-
- if (insn == NULL_RTX || GET_CODE (insn) != INSN)
- return false;
-
- body = PATTERN (insn);
-
- if (GET_CODE (body) != SET)
- return false;
-
- lhs = XEXP (body, 0);
- rhs = XEXP (body, 1);
-
- lhs = REG_OR_SUBREG_RTX (lhs);
-
- /* If the destination is not a general purpose
- register we do not have to worry. */
- if (GET_CODE (lhs) != REG
- || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
- return false;
-
- /* As well as loads from memory we also have to react
- to loads of invalid constants which will be turned
- into loads from the minipool. */
- return (GET_CODE (rhs) == MEM
- || GET_CODE (rhs) == SYMBOL_REF
- || note_invalid_constants (insn, -1, false));
-}
-
/* Return TRUE if X references a SYMBOL_REF. */
int
symbol_mentioned_p (rtx x)
@@ -13245,13 +13208,10 @@ arm_const_double_by_immediates (rtx val)
/* Scan INSN and note any of its operands that need fixing.
If DO_PUSHES is false we do not actually push any of the fixups
- needed. The function returns TRUE if any fixups were needed/pushed.
- This is used by arm_memory_load_p() which needs to know about loads
- of constants that will be converted into minipool loads. */
-static bool
+ needed. */
+static void
note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
{
- bool result = false;
int opno;
extract_insn (insn);
@@ -13260,7 +13220,7 @@ note_invalid_constants (rtx insn, HOST_W
fatal_insn_not_found (insn);
if (recog_data.n_alternatives == 0)
- return false;
+ return;
/* Fill in recog_op_alt with information about the constraints of
this insn. */
@@ -13285,7 +13245,6 @@ note_invalid_constants (rtx insn, HOST_W
if (do_pushes)
push_minipool_fix (insn, address, recog_data.operand_loc[opno],
recog_data.operand_mode[opno], op);
- result = true;
}
else if (GET_CODE (op) == MEM
&& GET_CODE (XEXP (op, 0)) == SYMBOL_REF
@@ -13308,12 +13267,11 @@ note_invalid_constants (rtx insn, HOST_W
recog_data.operand_mode[opno], cop);
}
- result = true;
}
}
}
- return result;
+ return;
}
/* Convert instructions to their cc-clobbering variant if possible, since
@@ -13670,7 +13628,6 @@ const char *
fp_immediate_constant (rtx x)
{
REAL_VALUE_TYPE r;
- int i;
if (!fp_consts_inited)
init_fp_table ();
@@ -13685,8 +13642,6 @@ fp_immediate_constant (rtx x)
static const char *
fp_const_from_val (REAL_VALUE_TYPE *r)
{
- int i;
-
if (!fp_consts_inited)
init_fp_table ();
@@ -20494,10 +20449,6 @@ arm_init_iwmmxt_builtins (void)
long_long_unsigned_type_node,
integer_type_node, NULL_TREE);
- tree void_ftype_void
- = build_function_type_list (void_type_node,
- NULL_TREE);
-
tree void_ftype_int
= build_function_type_list (void_type_node,
integer_type_node, NULL_TREE);
^ permalink raw reply [flat|nested] 8+ messages in thread
* [arm] Remove obsolete FPA support (7/n): Tidy up attributes
2012-06-14 9:40 [arm] Remove obsolete FPA support (2/n): Remove command-line options Richard Earnshaw
` (4 preceding siblings ...)
2012-06-18 15:39 ` [arm] Remove obsolete FPA support (6/n): fix warnings Richard Earnshaw
@ 2012-06-19 14:16 ` Richard Earnshaw
2012-07-07 16:45 ` [arm] Remove obsolete FPA support (8/n): Cleanup addressing and register usage Richard Earnshaw
6 siblings, 0 replies; 8+ messages in thread
From: Richard Earnshaw @ 2012-06-19 14:16 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 658 bytes --]
This patch cleans up some more of the resulting fall-out from removing
the FPA and maverick co-processors. In particular it covers:
- Removing the redundant states from the type attributes
- Removing some now redundant UNSPEC values.
- Removing some state from the generic scheduler description that is now
no-longer needed.
Tested on arm-eabi and installed on trunk.
* arm.md (enum unspec): Delete UNSPEC_SIN and UNSPEC_COS.
(attr type): Remove fmul, ffmul, farith, ffarith, float_em
f_fpa_load, f_fpa_store, f_mem_r, r_mem_f.
(attr write_conflict, attr core_cycles): Update.
* arm-generic.md (r_mem_f_wbuf): Delete reservation.
R.
[-- Attachment #2: nofpa7.patch --]
[-- Type: text/plain, Size: 5506 bytes --]
Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md (revision 188771)
+++ config/arm/arm.md (working copy)
@@ -65,12 +65,6 @@ (define_constants
;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md
(define_c_enum "unspec" [
- UNSPEC_SIN ; `sin' operation (MODE_FLOAT):
- ; operand 0 is the result,
- ; operand 1 the parameter.
- UNPSEC_COS ; `cos' operation (MODE_FLOAT):
- ; operand 0 is the result,
- ; operand 1 the parameter.
UNSPEC_PUSH_MULT ; `push multiple' operation:
; operand 0 is the first register,
; subsequent registers are in parallel (use ...)
@@ -321,21 +315,11 @@ (define_attr "insn"
; float a floating point arithmetic operation (subject to expansion)
; fdivd DFmode floating point division
; fdivs SFmode floating point division
-; fmul Floating point multiply
-; ffmul Fast floating point multiply
-; farith Floating point arithmetic (4 cycle)
-; ffarith Fast floating point arithmetic (2 cycle)
-; float_em a floating point arithmetic operation that is normally emulated
-; even on a machine with an fpa.
-; f_fpa_load a floating point load from memory. Only for the FPA.
-; f_fpa_store a floating point store to memory. Only for the FPA.
; f_load[sd] A single/double load from memory. Used for VFP unit.
; f_store[sd] A single/double store to memory. Used for VFP unit.
; f_flag a transfer of co-processor flags to the CPSR
-; f_mem_r a transfer of a floating point register to a real reg via mem
-; r_mem_f the reverse of f_mem_r
-; f_2_r fast transfer float to arm (no memory needed)
-; r_2_f fast transfer arm to float
+; f_2_r transfer float to core (no memory needed)
+; r_2_f transfer core to float
; f_cvt convert floating<->integral
; branch a branch
; call a subroutine call
@@ -351,18 +335,59 @@ (define_attr "insn"
;
(define_attr "type"
- "alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,fmuls,fmuld,fmacs,fmacd,ffmul,farith,ffarith,f_flag,float_em,f_fpa_load,f_fpa_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,fconsts,fconstd,fadds,faddd,ffariths,ffarithd,fcmps,fcmpd,fcpys"
- (if_then_else
- (eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
- (const_string "mult")
- (const_string "alu")))
+ "alu,\
+ alu_shift,\
+ alu_shift_reg,\
+ mult,\
+ block,\
+ float,\
+ fdivd,\
+ fdivs,\
+ fmuls,\
+ fmuld,\
+ fmacs,\
+ fmacd,\
+ f_flag,\
+ f_loads,\
+ f_loadd,\
+ f_stores,\
+ f_stored,\
+ f_2_r,\
+ r_2_f,\
+ f_cvt,\
+ branch,\
+ call,\
+ load_byte,\
+ load1,\
+ load2,\
+ load3,\
+ load4,\
+ store1,\
+ store2,\
+ store3,\
+ store4,\
+ fconsts,\
+ fconstd,\
+ fadds,\
+ faddd,\
+ ffariths,\
+ ffarithd,\
+ fcmps,\
+ fcmpd,\
+ fcpys"
+ (if_then_else
+ (eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,\
+ umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
+ (const_string "mult")
+ (const_string "alu")))
; Is this an (integer side) multiply with a 64-bit result?
(define_attr "mul64" "no,yes"
- (if_then_else
- (eq_attr "insn" "smlalxy,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
- (const_string "yes")
- (const_string "no")))
+ (if_then_else
+ (eq_attr "insn"
+ "smlalxy,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
+ (const_string "yes")
+ (const_string "no")))
; wtype for WMMX insn scheduling purposes.
(define_attr "wtype"
@@ -486,7 +511,7 @@ (define_attr "model_wbuf" "no,yes" (cons
; to stall the processor. Used with model_wbuf above.
(define_attr "write_conflict" "no,yes"
(if_then_else (eq_attr "type"
- "block,float_em,f_fpa_load,f_fpa_store,f_mem_r,r_mem_f,call,load1")
+ "block,call,load1")
(const_string "yes")
(const_string "no")))
@@ -494,7 +519,7 @@ (define_attr "write_conflict" "no,yes"
; than one on the main cpu execution unit.
(define_attr "core_cycles" "single,multi"
(if_then_else (eq_attr "type"
- "alu,alu_shift,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith")
+ "alu,alu_shift,float,fdivd,fdivs")
(const_string "single")
(const_string "multi")))
Index: config/arm/arm-generic.md
===================================================================
--- config/arm/arm-generic.md (revision 188771)
+++ config/arm/arm-generic.md (working copy)
@@ -38,20 +38,12 @@ (define_cpu_unit "write_buf" "arm")
;
; The write_blockage unit models (partially), the fact that reads will stall
; until the write buffer empties.
-; The f_mem_r and r_mem_f could also block, but they are to the stack,
-; so we don't model them here
(define_cpu_unit "write_blockage" "arm")
;; Core
;
(define_cpu_unit "core" "arm")
-(define_insn_reservation "r_mem_f_wbuf" 5
- (and (eq_attr "generic_sched" "yes")
- (and (eq_attr "model_wbuf" "yes")
- (eq_attr "type" "r_mem_f")))
- "core+write_buf*3")
-
(define_insn_reservation "store_wbuf" 5
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "model_wbuf" "yes")
^ permalink raw reply [flat|nested] 8+ messages in thread
* [arm] Remove obsolete FPA support (8/n): Cleanup addressing and register usage
2012-06-14 9:40 [arm] Remove obsolete FPA support (2/n): Remove command-line options Richard Earnshaw
` (5 preceding siblings ...)
2012-06-19 14:16 ` [arm] Remove obsolete FPA support (7/n): Tidy up attributes Richard Earnshaw
@ 2012-07-07 16:45 ` Richard Earnshaw
6 siblings, 0 replies; 8+ messages in thread
From: Richard Earnshaw @ 2012-07-07 16:45 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 5037 bytes --]
This is the last significant patch for the core part of the compiler, it
removes the last significant remnants of the code that supports the FPA
and Maverick. There are a lot of interwoven definitions that makes it
relatively hard to do this piecemeal and it was easier to do this in one
fell swoop.
Since there was a significant amount of renumbering needed, I've also
taken the opportunity to clean up the code a bit. In particular I've:
- Re-ordered some of the register bit fields so that significant
allocations don't cross 32-bit boundaries (mostly cosmetic)
- Re-defined some of the register numbering macros so that they are
chained (makes future re-numberings simpler).
- switched the compiler to using "r10" instead of "sl" in assembly
language. SL is a hangover from the original APCS days, and even their
it only had a sensible meaning in some variants of the APCS.
Tested on arm-eabi and arm-linux (with and without VFP). I've also done
some basic testing on wmmx to ensure that nothing obvious is broken; but
I don't have any HW to do full tests in that configuration.
Applied to trunk.
R.
2012-07-07 Richard Earnshaw <rearnsha@arm.com>
* arm.h (TARGET_CPU_CPP_BUILTINS): Remove Maverick support.
(TARGET_FPA): Delete definition.
(TARGET_MAVERICK): Likewise.
(TARGET_FPA_EMU2): Likewise.
(arm_fp_model): Remove FPA and Maverick models.
(arm_arch_cirrus): Delete declaration.
(FLOAT_WORDS_BIG_ENDIAN): Delete definition.
(FIXED_REGISTERS): Remove FPA and Maverick support. Reorganize.
(CALL_USED_REGISTERS): Likewise.
(FIRST_FPA_REGNUM, LAST_FPA_REGNUM): Delete definition.
(FIRST_VFP_REGNUM): Renumbered.
(D7_VFP_REGNUM): Chain definition.
(LAST_LO_VFP_REGNUM): Likewise.
(FIRST_HI_VFP_REGNUM): Likewise.
(LAST_HI_VFP_REGNUM): Likewise.
(FIRST_IWMMXT_GR_REGNUM): Likewise.
(LAST_IWMMXT_GR_REGNUM): Likewise.
(FIRST_IWMMXT_REGNUM): Likewise.
(LAST_IWMMXT_REGNUM): Likewise.
(FRAME_POINTER_REGNUM): Renumbered.
(ARG_POINTER_REGNUM): Renumbered.
(FIRST_PSEUDO_REGISTER): Remove FPA and Maverick registers.
(FIRST_CIRRUS_FP_REGNUM, LAST_CIRRUS_FP_REGNUM): Delete definitions.
(HARD_REGNO_REGNUM): Remove FPA support.
(REG_ALLOC_ORDER): Remove FPA and Maverick registers. Reorganize.
(reg_class): Likewise.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(CANNOT_CHANGE_MODE_CLASS): Never true. Update comment.
(SECONDARY_INPUT_RELOAD_CLASS): Remove Maverick support.
(CLASS_MAX_NREGS): Remove FPA and Maverick support.
* aout.h (REGISTER_NAMES): Remove FPA and Maverick registers.
Reorganize. Use AAPCS preferred names.
(ADDITIONAL_REGISTER_NAMES): Remove aliases for Maverick. Update
comments.
(OVERLAPPING_REGISTER_NAMES): Update register numbering.
* arm.c (FL_CIRRUS): Delete definition.
(arm_arch_cirrus): Delete variable.
(arm_float_words_big_endian): Delete function.
(cirrus_memory_offset): Delete function.
(output_mov_long_double_fpa_from_arm): Delete function.
(output_mov_long_double_arm_from_fpa): Delete function.
(output_mov_double_fpa_from_arm): Delete function.
(output_mov_double_arm_from_fpa): Delete function.
(emit_sfm): Delete function.
(maybe_get_arm_condition_code): Update comment.
(arm_file_start): Always use softvfp for softfloat systems.
(thumb_core_reg_alloc_order): Adjust for updated register allocation.
(arm_option_override): Remove FPA and Maverick support. Always
default to vfp as the fallback FPU format.
(use_return_insn): Remove FPA support.
(arm_get_frame_offsets): Likewise.
(arm_save_coproc_regs): Likewise.
(arm_canonicalize_comparison): Remove Maverick support.
(arm_select_cc_mode): Likewise.
(arm_gen_compare_reg): Likewise.
(arm_print_operand): Likewise.
(arm_libcall_value_1): Remove FPA and Maverick support.
(arm_function_value_regno_p): Likewise.
(arm_apply_result_size): Likewise.
(arm_legitimate_index_p): Likewise.
(thumb2_legitimate_index_p): Likewise.
(legitimize_reload_address): Likewise.
(arm_register_move_cost): Likewise.
(arm_hard_regno_mode_ok): Likewise.
(arm_regno_class): Likewise.
(arm_dbx_register_number): Likewise.
(arm_emit_unwind_sequence): Likewise.
(arm_conditional_register_usage): Likewise.
* arm-protos.h (neg_const_double_rtx_ok_for_fpa): Remove declaration.
(cirrus_memory_offset): Likewise.
(output_move_long_double_fpa_from_arm): Likewise.
(output_move_long_double_arm_from_fpa): Likewise.
(output_move_double_fpa_from_arm): Likewise.
(output_move_double_arm_from_fpa): Likewise.
(arm_float_words_big_endian): Likewise.
* arm.md (CC_REGNUM): Renumbered.
(VFPCC_REGNUM): Moved here. Renumbered.
(FPA_F0_REGNUM, FPA_F7_REGNUM): Delete.
(attr fpu): Remove FPA and Maverick support.
* vfp.md (VFPCC_REGNUM): Delete. Moved to arm.md.
* arm-cores.def (ep9312): Remove Maverick support.
* arm-arches.def (ep9312): Delete architecture.
* arm-tables.opt: Regenerated.
* arm/linux-elf.h (FPUTYPE_DEFAULT): Set to vfp.
[-- Attachment #2: nofpa8.patch --]
[-- Type: text/plain, Size: 60546 bytes --]
diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h
index f8e7367..bc00080 100644
--- a/gcc/config/arm/aout.h
+++ b/gcc/config/arm/aout.h
@@ -51,30 +51,24 @@
(each of which is overlaid on two S registers), although there are no
actual single-precision registers which correspond to D16-D31. */
#ifndef REGISTER_NAMES
-#define REGISTER_NAMES \
-{ \
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
- "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", \
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
- "cc", "sfp", "afp", \
- "mv0", "mv1", "mv2", "mv3", \
- "mv4", "mv5", "mv6", "mv7", \
- "mv8", "mv9", "mv10", "mv11", \
- "mv12", "mv13", "mv14", "mv15", \
- "wcgr0", "wcgr1", "wcgr2", "wcgr3", \
- "wr0", "wr1", "wr2", "wr3", \
- "wr4", "wr5", "wr6", "wr7", \
- "wr8", "wr9", "wr10", "wr11", \
- "wr12", "wr13", "wr14", "wr15", \
- "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
- "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", \
- "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", \
- "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", \
- "d16", "?16", "d17", "?17", "d18", "?18", "d19", "?19", \
- "d20", "?20", "d21", "?21", "d22", "?22", "d23", "?23", \
- "d24", "?24", "d25", "?25", "d26", "?26", "d27", "?27", \
- "d28", "?28", "d29", "?29", "d30", "?30", "d31", "?31", \
- "vfpcc" \
+#define REGISTER_NAMES \
+{ \
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
+ "r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc", \
+ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
+ "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", \
+ "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", \
+ "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", \
+ "d16", "?16", "d17", "?17", "d18", "?18", "d19", "?19", \
+ "d20", "?20", "d21", "?21", "d22", "?22", "d23", "?23", \
+ "d24", "?24", "d25", "?25", "d26", "?26", "d27", "?27", \
+ "d28", "?28", "d29", "?29", "d30", "?30", "d31", "?31", \
+ "wr0", "wr1", "wr2", "wr3", \
+ "wr4", "wr5", "wr6", "wr7", \
+ "wr8", "wr9", "wr10", "wr11", \
+ "wr12", "wr13", "wr14", "wr15", \
+ "wcgr0", "wcgr1", "wcgr2", "wcgr3", \
+ "cc", "vfpcc", "sfp", "afp" \
}
#endif
@@ -91,117 +85,53 @@
{"v4", 7}, \
{"v5", 8}, \
{"v6", 9}, \
- {"rfp", 9}, /* Gcc used to call it this */ \
- {"sb", 9}, \
+ {"rfp", 9}, /* Historical. */ \
+ {"sb", 9}, /* Historical. */ \
{"v7", 10}, \
- {"r10", 10}, /* sl */ \
+ {"sl", 10}, /* Historical. */ \
{"r11", 11}, /* fp */ \
{"r12", 12}, /* ip */ \
{"r13", 13}, /* sp */ \
{"r14", 14}, /* lr */ \
- {"r15", 15}, /* pc */ \
- {"mvf0", 27}, \
- {"mvf1", 28}, \
- {"mvf2", 29}, \
- {"mvf3", 30}, \
- {"mvf4", 31}, \
- {"mvf5", 32}, \
- {"mvf6", 33}, \
- {"mvf7", 34}, \
- {"mvf8", 35}, \
- {"mvf9", 36}, \
- {"mvf10", 37}, \
- {"mvf11", 38}, \
- {"mvf12", 39}, \
- {"mvf13", 40}, \
- {"mvf14", 41}, \
- {"mvf15", 42}, \
- {"mvd0", 27}, \
- {"mvd1", 28}, \
- {"mvd2", 29}, \
- {"mvd3", 30}, \
- {"mvd4", 31}, \
- {"mvd5", 32}, \
- {"mvd6", 33}, \
- {"mvd7", 34}, \
- {"mvd8", 35}, \
- {"mvd9", 36}, \
- {"mvd10", 37}, \
- {"mvd11", 38}, \
- {"mvd12", 39}, \
- {"mvd13", 40}, \
- {"mvd14", 41}, \
- {"mvd15", 42}, \
- {"mvfx0", 27}, \
- {"mvfx1", 28}, \
- {"mvfx2", 29}, \
- {"mvfx3", 30}, \
- {"mvfx4", 31}, \
- {"mvfx5", 32}, \
- {"mvfx6", 33}, \
- {"mvfx7", 34}, \
- {"mvfx8", 35}, \
- {"mvfx9", 36}, \
- {"mvfx10", 37}, \
- {"mvfx11", 38}, \
- {"mvfx12", 39}, \
- {"mvfx13", 40}, \
- {"mvfx14", 41}, \
- {"mvfx15", 42}, \
- {"mvdx0", 27}, \
- {"mvdx1", 28}, \
- {"mvdx2", 29}, \
- {"mvdx3", 30}, \
- {"mvdx4", 31}, \
- {"mvdx5", 32}, \
- {"mvdx6", 33}, \
- {"mvdx7", 34}, \
- {"mvdx8", 35}, \
- {"mvdx9", 36}, \
- {"mvdx10", 37}, \
- {"mvdx11", 38}, \
- {"mvdx12", 39}, \
- {"mvdx13", 40}, \
- {"mvdx14", 41}, \
- {"mvdx15", 42} \
+ {"r15", 15} /* pc */ \
}
#endif
#ifndef OVERLAPPING_REGISTER_NAMES
#define OVERLAPPING_REGISTER_NAMES \
{ \
- {"d0", 63, 2}, \
- {"d1", 65, 2}, \
- {"d2", 67, 2}, \
- {"d3", 69, 2}, \
- {"d4", 71, 2}, \
- {"d5", 73, 2}, \
- {"d6", 75, 2}, \
- {"d7", 77, 2}, \
- {"d8", 79, 2}, \
- {"d9", 81, 2}, \
- {"d10", 83, 2}, \
- {"d11", 85, 2}, \
- {"d12", 87, 2}, \
- {"d13", 89, 2}, \
- {"d14", 91, 2}, \
- {"d15", 93, 2}, \
- {"q0", 63, 4}, \
- {"q1", 67, 4}, \
- {"q2", 71, 4}, \
- {"q3", 75, 4}, \
- {"q4", 79, 4}, \
- {"q5", 83, 4}, \
- {"q6", 87, 4}, \
- {"q7", 91, 4}, \
- {"q8", 95, 4}, \
- {"q9", 99, 4}, \
- {"q10", 103, 4}, \
- {"q11", 107, 4}, \
- {"q12", 111, 4}, \
- {"q13", 115, 4}, \
- {"q14", 119, 4}, \
- {"q15", 123, 4} \
+ {"d0", FIRST_VFP_REGNUM + 0, 2}, \
+ {"d1", FIRST_VFP_REGNUM + 2, 2}, \
+ {"d2", FIRST_VFP_REGNUM + 4, 2}, \
+ {"d3", FIRST_VFP_REGNUM + 6, 2}, \
+ {"d4", FIRST_VFP_REGNUM + 8, 2}, \
+ {"d5", FIRST_VFP_REGNUM + 10, 2}, \
+ {"d6", FIRST_VFP_REGNUM + 12, 2}, \
+ {"d7", FIRST_VFP_REGNUM + 14, 2}, \
+ {"d8", FIRST_VFP_REGNUM + 16, 2}, \
+ {"d9", FIRST_VFP_REGNUM + 18, 2}, \
+ {"d10", FIRST_VFP_REGNUM + 20, 2}, \
+ {"d11", FIRST_VFP_REGNUM + 22, 2}, \
+ {"d12", FIRST_VFP_REGNUM + 24, 2}, \
+ {"d13", FIRST_VFP_REGNUM + 26, 2}, \
+ {"d14", FIRST_VFP_REGNUM + 28, 2}, \
+ {"d15", FIRST_VFP_REGNUM + 30, 2}, \
+ {"q0", FIRST_VFP_REGNUM + 0, 4}, \
+ {"q1", FIRST_VFP_REGNUM + 4, 4}, \
+ {"q2", FIRST_VFP_REGNUM + 8, 4}, \
+ {"q3", FIRST_VFP_REGNUM + 12, 4}, \
+ {"q4", FIRST_VFP_REGNUM + 16, 4}, \
+ {"q5", FIRST_VFP_REGNUM + 20, 4}, \
+ {"q6", FIRST_VFP_REGNUM + 24, 4}, \
+ {"q7", FIRST_VFP_REGNUM + 28, 4}, \
+ {"q8", FIRST_VFP_REGNUM + 32, 4}, \
+ {"q9", FIRST_VFP_REGNUM + 36, 4}, \
+ {"q10", FIRST_VFP_REGNUM + 40, 4}, \
+ {"q11", FIRST_VFP_REGNUM + 44, 4}, \
+ {"q12", FIRST_VFP_REGNUM + 48, 4}, \
+ {"q13", FIRST_VFP_REGNUM + 52, 4}, \
+ {"q14", FIRST_VFP_REGNUM + 56, 4}, \
+ {"q15", FIRST_VFP_REGNUM + 60, 4} \
}
#endif
diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index fc62e51..f83639d 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -55,6 +55,5 @@ ARM_ARCH("armv7-a", cortexa8, 7A, FL_CO_PROC | FL_FOR_ARCH7A)
ARM_ARCH("armv7-r", cortexr4, 7R, FL_CO_PROC | FL_FOR_ARCH7R)
ARM_ARCH("armv7-m", cortexm3, 7M, FL_CO_PROC | FL_FOR_ARCH7M)
ARM_ARCH("armv7e-m", cortexm4, 7EM, FL_CO_PROC | FL_FOR_ARCH7EM)
-ARM_ARCH("ep9312", ep9312, 4T, FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4)
ARM_ARCH("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT)
ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2)
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 1407771..223e41f 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -89,7 +89,7 @@ ARM_CORE("arm920", arm920, 4T, FL_LDSCHED, fastm
ARM_CORE("arm920t", arm920t, 4T, FL_LDSCHED, fastmul)
ARM_CORE("arm922t", arm922t, 4T, FL_LDSCHED, fastmul)
ARM_CORE("arm940t", arm940t, 4T, FL_LDSCHED, fastmul)
-ARM_CORE("ep9312", ep9312, 4T, FL_LDSCHED | FL_CIRRUS, fastmul)
+ARM_CORE("ep9312", ep9312, 4T, FL_LDSCHED, fastmul)
/* V5T Architecture Processors */
ARM_CORE("arm10tdmi", arm10tdmi, 5T, FL_LDSCHED, fastmul)
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 76e1abd..78c68d1 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -66,7 +66,6 @@ extern int thumb1_legitimate_address_p (enum machine_mode, rtx, int);
extern bool ldm_stm_operation_p (rtx, bool, enum machine_mode mode,
bool, bool);
extern int arm_const_double_rtx (rtx);
-extern int neg_const_double_rtx_ok_for_fpa (rtx);
extern int vfp3_const_double_rtx (rtx);
extern int neon_immediate_valid_for_move (rtx, enum machine_mode, rtx *, int *);
extern int neon_immediate_valid_for_logic (rtx, enum machine_mode, int, rtx *,
@@ -94,7 +93,6 @@ extern enum reg_class coproc_secondary_reload_class (enum machine_mode, rtx,
bool);
extern bool arm_tls_referenced_p (rtx);
-extern int cirrus_memory_offset (rtx);
extern int arm_coproc_mem_operand (rtx, bool);
extern int neon_vector_mem_operand (rtx, int);
extern int neon_struct_mem_operand (rtx);
@@ -133,11 +131,7 @@ extern void arm_emit_call_insn (rtx, rtx);
extern const char *output_call (rtx *);
extern const char *output_call_mem (rtx *);
void arm_emit_movpair (rtx, rtx);
-extern const char *output_mov_long_double_fpa_from_arm (rtx *);
-extern const char *output_mov_long_double_arm_from_fpa (rtx *);
extern const char *output_mov_long_double_arm_from_arm (rtx *);
-extern const char *output_mov_double_fpa_from_arm (rtx *);
-extern const char *output_mov_double_arm_from_fpa (rtx *);
extern const char *output_move_double (rtx *, bool, int *count);
extern const char *output_move_quad (rtx *);
extern int arm_count_output_move_double_insns (rtx *);
@@ -178,8 +172,6 @@ extern int arm_apply_result_size (void);
#endif /* RTX_CODE */
-extern int arm_float_words_big_endian (void);
-
/* Thumb functions. */
extern void arm_init_expanders (void);
extern const char *thumb1_unexpanded_epilogue (void);
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index acdfbe9..5f93695 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -347,13 +347,10 @@ EnumValue
Enum(arm_arch) String(armv7e-m) Value(22)
EnumValue
-Enum(arm_arch) String(ep9312) Value(23)
+Enum(arm_arch) String(iwmmxt) Value(23)
EnumValue
-Enum(arm_arch) String(iwmmxt) Value(24)
-
-EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(25)
+Enum(arm_arch) String(iwmmxt2) Value(24)
Enum
Name(arm_fpu) Type(int)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 627b436..c94cca8 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -87,7 +87,6 @@ inline static int thumb1_index_register_rtx_p (rtx, int);
static bool arm_legitimate_address_p (enum machine_mode, rtx, bool);
static int thumb_far_jump_used_p (void);
static bool thumb_force_lr_save (void);
-static rtx emit_sfm (int, int);
static unsigned arm_size_return_regs (void);
static bool arm_assemble_integer (rtx, unsigned int, int);
static void arm_print_operand (FILE *, rtx, int);
@@ -662,7 +661,7 @@ static int thumb_call_reg_needed;
#define FL_STRONG (1 << 8) /* StrongARM */
#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
#define FL_XSCALE (1 << 10) /* XScale */
-#define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
+/* spare (1 << 11) */
#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
media instructions. */
#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
@@ -757,9 +756,6 @@ int arm_ld_sched = 0;
/* Nonzero if this chip is a StrongARM. */
int arm_tune_strongarm = 0;
-/* Nonzero if this chip is a Cirrus variant. */
-int arm_arch_cirrus = 0;
-
/* Nonzero if this chip supports Intel Wireless MMX technology. */
int arm_arch_iwmmxt = 0;
@@ -1708,7 +1704,6 @@ arm_option_override (void)
arm_arch7em = (insn_flags & FL_ARCH7EM) != 0;
arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
- arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
@@ -1768,10 +1763,7 @@ arm_option_override (void)
#ifdef FPUTYPE_DEFAULT
target_fpu_name = FPUTYPE_DEFAULT;
#else
- if (arm_arch_cirrus)
- target_fpu_name = "maverick";
- else
- target_fpu_name = "fpe2";
+ target_fpu_name = "vfp";
#endif
ok = opt_enum_arg_to_value (OPT_mfpu_, target_fpu_name, &arm_fpu_index,
@@ -1783,19 +1775,6 @@ arm_option_override (void)
switch (arm_fpu_desc->model)
{
- case ARM_FP_MODEL_FPA:
- if (arm_fpu_desc->rev == 2)
- arm_fpu_attr = FPU_FPE2;
- else if (arm_fpu_desc->rev == 3)
- arm_fpu_attr = FPU_FPE3;
- else
- arm_fpu_attr = FPU_FPA;
- break;
-
- case ARM_FP_MODEL_MAVERICK:
- arm_fpu_attr = FPU_MAVERICK;
- break;
-
case ARM_FP_MODEL_VFP:
arm_fpu_attr = FPU_VFP;
break;
@@ -1804,10 +1783,6 @@ arm_option_override (void)
gcc_unreachable();
}
- if (TARGET_AAPCS_BASED
- && (arm_fpu_desc->model == ARM_FP_MODEL_FPA))
- error ("FPA is unsupported in the AAPCS");
-
if (TARGET_AAPCS_BASED)
{
if (TARGET_CALLER_INTERWORKING)
@@ -1817,11 +1792,6 @@ arm_option_override (void)
error ("AAPCS does not support -mcallee-super-interworking");
}
- /* FPA and iWMMXt are incompatible because the insn encodings overlap.
- VFP and iWMMXt however can coexist. */
- if (TARGET_IWMMXT && TARGET_HARD_FLOAT && !TARGET_VFP)
- error ("iWMMXt and non-VFP floating point unit are incompatible");
-
/* iWMMXt and NEON are incompatible. */
if (TARGET_IWMMXT && TARGET_NEON)
error ("iWMMXt and NEON are incompatible");
@@ -1860,11 +1830,9 @@ arm_option_override (void)
arm_pcs_default = ARM_PCS_ATPCS;
}
- /* For arm2/3 there is no need to do any scheduling if there is only
- a floating point emulator, or we are doing software floating-point. */
- if ((TARGET_SOFT_FLOAT
- || (TARGET_FPA && arm_fpu_desc->rev))
- && (tune_flags & FL_MODE32) == 0)
+ /* For arm2/3 there is no need to do any scheduling if we are doing
+ software floating-point. */
+ if (TARGET_SOFT_FLOAT && (tune_flags & FL_MODE32) == 0)
flag_schedule_insns = flag_schedule_insns_after_reload = 0;
/* Use the cp15 method if it is available. */
@@ -2356,14 +2324,8 @@ use_return_insn (int iscond, rtx sibling)
if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
return 0;
- /* Can't be done if any of the FPA regs are pushed,
+ /* Can't be done if any of the VFP regs are pushed,
since this also requires an insn. */
- if (TARGET_HARD_FLOAT && TARGET_FPA)
- for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
- if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
- return 0;
-
- /* Likewise VFP regs. */
if (TARGET_HARD_FLOAT && TARGET_VFP)
for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
@@ -3466,11 +3428,6 @@ arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1)
{
rtx tem;
- /* To keep things simple, always use the Cirrus cfcmp64 if it is
- available. */
- if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK)
- return code;
-
if (code == GT || code == LE
|| (!TARGET_ARM && (code == GTU || code == LEU)))
{
@@ -3720,16 +3677,6 @@ arm_libcall_value_1 (enum machine_mode mode)
{
if (TARGET_AAPCS_BASED)
return aapcs_libcall_value (mode);
- else if (TARGET_32BIT
- && TARGET_HARD_FLOAT_ABI
- && TARGET_FPA
- && GET_MODE_CLASS (mode) == MODE_FLOAT)
- return gen_rtx_REG (mode, FIRST_FPA_REGNUM);
- else if (TARGET_32BIT
- && TARGET_HARD_FLOAT_ABI
- && TARGET_MAVERICK
- && GET_MODE_CLASS (mode) == MODE_FLOAT)
- return gen_rtx_REG (mode, FIRST_CIRRUS_FP_REGNUM);
else if (TARGET_IWMMXT_ABI
&& arm_vector_mode_supported_p (mode))
return gen_rtx_REG (mode, FIRST_IWMMXT_REGNUM);
@@ -3767,16 +3714,8 @@ arm_function_value_regno_p (const unsigned int regno)
&& TARGET_VFP
&& TARGET_HARD_FLOAT
&& regno == FIRST_VFP_REGNUM)
- || (TARGET_32BIT
- && TARGET_HARD_FLOAT_ABI
- && TARGET_MAVERICK
- && regno == FIRST_CIRRUS_FP_REGNUM)
|| (TARGET_IWMMXT_ABI
- && regno == FIRST_IWMMXT_REGNUM)
- || (TARGET_32BIT
- && TARGET_HARD_FLOAT_ABI
- && TARGET_FPA
- && regno == FIRST_FPA_REGNUM))
+ && regno == FIRST_IWMMXT_REGNUM))
return true;
return false;
@@ -3791,15 +3730,8 @@ arm_apply_result_size (void)
if (TARGET_32BIT)
{
- if (TARGET_HARD_FLOAT_ABI)
- {
- if (TARGET_VFP)
- size += 32;
- if (TARGET_FPA)
- size += 12;
- if (TARGET_MAVERICK)
- size += 8;
- }
+ if (TARGET_HARD_FLOAT_ABI && TARGET_VFP)
+ size += 32;
if (TARGET_IWMMXT_ABI)
size += 8;
}
@@ -3950,28 +3882,6 @@ arm_return_in_memory (const_tree type, const_tree fntype)
return true;
}
-/* Indicate whether or not words of a double are in big-endian order. */
-
-int
-arm_float_words_big_endian (void)
-{
- if (TARGET_MAVERICK)
- return 0;
-
- /* For FPA, float words are always big-endian. For VFP, floats words
- follow the memory system mode. */
-
- if (TARGET_FPA)
- {
- return 1;
- }
-
- if (TARGET_VFP)
- return (TARGET_BIG_END ? 1 : 0);
-
- return 1;
-}
-
const struct pcs_attribute_arg
{
const char *arg;
@@ -5851,9 +5761,8 @@ arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
/* Standard coprocessor addressing modes. */
if (TARGET_HARD_FLOAT
- && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
- && (mode == SFmode || mode == DFmode
- || (TARGET_MAVERICK && mode == DImode)))
+ && TARGET_VFP
+ && (mode == SFmode || mode == DFmode))
return (code == CONST_INT && INTVAL (index) < 1024
&& INTVAL (index) > -1024
&& (INTVAL (index) & 3) == 0);
@@ -5972,9 +5881,8 @@ thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
/* ??? Combine arm and thumb2 coprocessor addressing modes. */
/* Standard coprocessor addressing modes. */
if (TARGET_HARD_FLOAT
- && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
- && (mode == SFmode || mode == DFmode
- || (TARGET_MAVERICK && mode == DImode)))
+ && TARGET_VFP
+ && (mode == SFmode || mode == DFmode))
return (code == CONST_INT && INTVAL (index) < 1024
/* Thumb-2 allows only > -256 index range for it's core register
load/stores. Since we allow SF/DF in core registers, we have
@@ -6687,9 +6595,8 @@ arm_legitimize_reload_address (rtx *p,
/* Detect coprocessor load/stores. */
bool coproc_p = ((TARGET_HARD_FLOAT
- && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
- && (mode == SFmode || mode == DFmode
- || (mode == DImode && TARGET_MAVERICK)))
+ && TARGET_VFP
+ && (mode == SFmode || mode == DFmode))
|| (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode))
|| (TARGET_NEON
@@ -8545,7 +8452,6 @@ fa726te_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
/* Implement TARGET_REGISTER_MOVE_COST.
- Moves between FPA_REGS and GENERAL_REGS are two memory insns.
Moves between VFP_REGS and GENERAL_REGS are a single insn, but
it is typically more expensive than a single memory access. We set
the cost to less than two memory accesses so that floating
@@ -8557,20 +8463,14 @@ arm_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
{
if (TARGET_32BIT)
{
- if ((from == FPA_REGS && to != FPA_REGS)
- || (from != FPA_REGS && to == FPA_REGS))
- return 20;
- else if ((IS_VFP_CLASS (from) && !IS_VFP_CLASS (to))
- || (!IS_VFP_CLASS (from) && IS_VFP_CLASS (to)))
+ if ((IS_VFP_CLASS (from) && !IS_VFP_CLASS (to))
+ || (!IS_VFP_CLASS (from) && IS_VFP_CLASS (to)))
return 15;
else if ((from == IWMMXT_REGS && to != IWMMXT_REGS)
|| (from != IWMMXT_REGS && to == IWMMXT_REGS))
return 4;
else if (from == IWMMXT_GR_REGS || to == IWMMXT_GR_REGS)
return 20;
- else if ((from == CIRRUS_REGS && to != CIRRUS_REGS)
- || (from != CIRRUS_REGS && to == CIRRUS_REGS))
- return 20;
else
return 2;
}
@@ -8628,7 +8528,7 @@ arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
return cost;
}
- /* XXX This is not strictly true for the FPA. */
+ /* XXX Is this strictly true? */
if (REG_NOTE_KIND (link) == REG_DEP_ANTI
|| REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
return 0;
@@ -9477,43 +9377,6 @@ neon_element_bits (enum machine_mode mode)
\f
/* Predicates for `match_operand' and `match_operator'. */
-/* Return nonzero if OP is a valid Cirrus memory address pattern. */
-int
-cirrus_memory_offset (rtx op)
-{
- /* Reject eliminable registers. */
- if (! (reload_in_progress || reload_completed)
- && ( reg_mentioned_p (frame_pointer_rtx, op)
- || reg_mentioned_p (arg_pointer_rtx, op)
- || reg_mentioned_p (virtual_incoming_args_rtx, op)
- || reg_mentioned_p (virtual_outgoing_args_rtx, op)
- || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
- || reg_mentioned_p (virtual_stack_vars_rtx, op)))
- return 0;
-
- if (GET_CODE (op) == MEM)
- {
- rtx ind;
-
- ind = XEXP (op, 0);
-
- /* Match: (mem (reg)). */
- if (GET_CODE (ind) == REG)
- return 1;
-
- /* Match:
- (mem (plus (reg)
- (const))). */
- if (GET_CODE (ind) == PLUS
- && GET_CODE (XEXP (ind, 0)) == REG
- && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
- && GET_CODE (XEXP (ind, 1)) == CONST_INT)
- return 1;
- }
-
- return 0;
-}
-
/* Return TRUE if OP is a valid coprocessor memory address pattern.
WB is true if full writeback address modes are allowed and is false
if limited writeback address modes (POST_INC and PRE_DEC) are
@@ -11613,8 +11476,6 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
case LE:
case GT:
case GE:
- if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
- return CCFPmode;
return CCFPEmode;
default:
@@ -11719,11 +11580,6 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
if (GET_MODE (x) == DImode || GET_MODE (y) == DImode)
{
- /* To keep things simple, always use the Cirrus cfcmp64 if it is
- available. */
- if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK)
- return CCmode;
-
switch (op)
{
case EQ:
@@ -11791,7 +11647,6 @@ arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y, rtx scratch)
cc_reg = gen_rtx_REG (mode, CC_REGNUM);
if (dimode_comparison
- && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)
&& mode != CC_CZmode)
{
rtx clobber, set;
@@ -13934,47 +13789,6 @@ output_call_mem (rtx *operands)
}
-/* Output a move from arm registers to an fpa registers.
- OPERANDS[0] is an fpa register.
- OPERANDS[1] is the first registers of an arm register pair. */
-const char *
-output_mov_long_double_fpa_from_arm (rtx *operands)
-{
- int arm_reg0 = REGNO (operands[1]);
- rtx ops[3];
-
- gcc_assert (arm_reg0 != IP_REGNUM);
-
- ops[0] = gen_rtx_REG (SImode, arm_reg0);
- ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
- ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
-
- output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
- output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
-
- return "";
-}
-
-/* Output a move from an fpa register to arm registers.
- OPERANDS[0] is the first registers of an arm register pair.
- OPERANDS[1] is an fpa register. */
-const char *
-output_mov_long_double_arm_from_fpa (rtx *operands)
-{
- int arm_reg0 = REGNO (operands[0]);
- rtx ops[3];
-
- gcc_assert (arm_reg0 != IP_REGNUM);
-
- ops[0] = gen_rtx_REG (SImode, arm_reg0);
- ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
- ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
-
- output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
- output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
- return "";
-}
-
/* Output a move from arm registers to arm registers of a long double
OPERANDS[0] is the destination.
OPERANDS[1] is the source. */
@@ -14027,42 +13841,6 @@ arm_emit_movpair (rtx dest, rtx src)
emit_set_insn (dest, gen_rtx_LO_SUM (SImode, dest, src));
}
-/* Output a move from arm registers to an fpa registers.
- OPERANDS[0] is an fpa register.
- OPERANDS[1] is the first registers of an arm register pair. */
-const char *
-output_mov_double_fpa_from_arm (rtx *operands)
-{
- int arm_reg0 = REGNO (operands[1]);
- rtx ops[2];
-
- gcc_assert (arm_reg0 != IP_REGNUM);
-
- ops[0] = gen_rtx_REG (SImode, arm_reg0);
- ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
- output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops);
- output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
- return "";
-}
-
-/* Output a move from an fpa register to arm registers.
- OPERANDS[0] is the first registers of an arm register pair.
- OPERANDS[1] is an fpa register. */
-const char *
-output_mov_double_arm_from_fpa (rtx *operands)
-{
- int arm_reg0 = REGNO (operands[0]);
- rtx ops[2];
-
- gcc_assert (arm_reg0 != IP_REGNUM);
-
- ops[0] = gen_rtx_REG (SImode, arm_reg0);
- ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
- output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
- output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops);
- return "";
-}
-
/* Output a move between double words. It must be REG<-MEM
or MEM<-REG. */
const char *
@@ -16105,68 +15883,7 @@ arm_size_return_regs (void)
return GET_MODE_SIZE (mode);
}
-static rtx
-emit_sfm (int base_reg, int count)
-{
- rtx par;
- rtx dwarf;
- rtx tmp, reg;
- int i;
-
- par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
- dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
-
- reg = gen_rtx_REG (XFmode, base_reg++);
-
- XVECEXP (par, 0, 0)
- = gen_rtx_SET (VOIDmode,
- gen_frame_mem
- (BLKmode,
- gen_rtx_PRE_MODIFY (Pmode,
- stack_pointer_rtx,
- plus_constant
- (Pmode, stack_pointer_rtx,
- -12 * count))
- ),
- gen_rtx_UNSPEC (BLKmode,
- gen_rtvec (1, reg),
- UNSPEC_PUSH_MULT));
- tmp = gen_rtx_SET (VOIDmode,
- gen_frame_mem (XFmode, stack_pointer_rtx), reg);
- RTX_FRAME_RELATED_P (tmp) = 1;
- XVECEXP (dwarf, 0, 1) = tmp;
-
- for (i = 1; i < count; i++)
- {
- reg = gen_rtx_REG (XFmode, base_reg++);
- XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
-
- tmp = gen_rtx_SET (VOIDmode,
- gen_frame_mem (XFmode,
- plus_constant (Pmode,
- stack_pointer_rtx,
- i * 12)),
- reg);
- RTX_FRAME_RELATED_P (tmp) = 1;
- XVECEXP (dwarf, 0, i + 1) = tmp;
- }
-
- tmp = gen_rtx_SET (VOIDmode,
- stack_pointer_rtx,
- plus_constant (Pmode, stack_pointer_rtx, -12 * count));
-
- RTX_FRAME_RELATED_P (tmp) = 1;
- XVECEXP (dwarf, 0, 0) = tmp;
-
- par = emit_insn (par);
- add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf);
-
- return par;
-}
-
-
/* Return true if the current function needs to save/restore LR. */
-
static bool
thumb_force_lr_save (void)
{
@@ -16179,7 +15896,6 @@ thumb_force_lr_save (void)
/* Return true if r3 is used by any of the tail call insns in the
current function. */
-
static bool
any_sibcall_uses_r3 (void)
{
@@ -16317,17 +16033,10 @@ arm_get_frame_offsets (void)
}
func_type = arm_current_func_type ();
- if (! IS_VOLATILE (func_type))
- {
- /* Space for saved FPA registers. */
- for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
- if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
- saved += 12;
-
- /* Space for saved VFP registers. */
- if (TARGET_HARD_FLOAT && TARGET_VFP)
- saved += arm_get_vfp_saved_size ();
- }
+ /* Space for saved VFP registers. */
+ if (! IS_VOLATILE (func_type)
+ && TARGET_HARD_FLOAT && TARGET_VFP)
+ saved += arm_get_vfp_saved_size ();
}
else /* TARGET_THUMB1 */
{
@@ -16523,55 +16232,6 @@ arm_save_coproc_regs(void)
saved_size += 8;
}
- /* Save any floating point call-saved registers used by this
- function. */
- if (TARGET_FPA_EMU2)
- {
- for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
- if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
- {
- insn = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx);
- insn = gen_rtx_MEM (XFmode, insn);
- insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg));
- RTX_FRAME_RELATED_P (insn) = 1;
- saved_size += 12;
- }
- }
- else
- {
- start_reg = LAST_FPA_REGNUM;
-
- for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
- {
- if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
- {
- if (start_reg - reg == 3)
- {
- insn = emit_sfm (reg, 4);
- RTX_FRAME_RELATED_P (insn) = 1;
- saved_size += 48;
- start_reg = reg - 1;
- }
- }
- else
- {
- if (start_reg != reg)
- {
- insn = emit_sfm (reg + 1, start_reg - reg);
- RTX_FRAME_RELATED_P (insn) = 1;
- saved_size += (start_reg - reg) * 12;
- }
- start_reg = reg - 1;
- }
- }
-
- if (start_reg != reg)
- {
- insn = emit_sfm (reg + 1, start_reg - reg);
- saved_size += (start_reg - reg) * 12;
- RTX_FRAME_RELATED_P (insn) = 1;
- }
- }
if (TARGET_HARD_FLOAT && TARGET_VFP)
{
start_reg = FIRST_VFP_REGNUM;
@@ -17128,16 +16788,6 @@ arm_print_operand (FILE *stream, rtx x, int code)
fprintf (stream, "%s", arithmetic_instr (x, 1));
return;
- /* Truncate Cirrus shift counts. */
- case 's':
- if (GET_CODE (x) == CONST_INT)
- {
- fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
- return;
- }
- arm_print_operand (stream, x, 0);
- return;
-
case 'I':
fprintf (stream, "%s", arithmetic_instr (x, 0));
return;
@@ -17324,44 +16974,15 @@ arm_print_operand (FILE *stream, rtx x, int code)
stream);
return;
- /* Cirrus registers can be accessed in a variety of ways:
- single floating point (f)
- double floating point (d)
- 32bit integer (fx)
- 64bit integer (dx). */
- case 'W': /* Cirrus register in F mode. */
- case 'X': /* Cirrus register in D mode. */
- case 'Y': /* Cirrus register in FX mode. */
- case 'Z': /* Cirrus register in DX mode. */
- gcc_assert (GET_CODE (x) == REG
- && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
-
- fprintf (stream, "mv%s%s",
- code == 'W' ? "f"
- : code == 'X' ? "d"
- : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
-
- return;
-
- /* Print cirrus register in the mode specified by the register's mode. */
+ case 's':
case 'V':
- {
- int mode = GET_MODE (x);
-
- if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
- {
- output_operand_lossage ("invalid operand for code '%c'", code);
- return;
- }
-
- fprintf (stream, "mv%s%s",
- mode == DFmode ? "d"
- : mode == SImode ? "fx"
- : mode == DImode ? "dx"
- : "f", reg_names[REGNO (x)] + 2);
-
- return;
- }
+ case 'W':
+ case 'X':
+ case 'Y':
+ case 'Z':
+ /* Former Maverick support, removed after GCC-4.7. */
+ output_operand_lossage ("obsolete Maverick format code '%c'", code);
+ return;
case 'U':
if (GET_CODE (x) != REG
@@ -18046,9 +17667,7 @@ maybe_get_arm_condition_code (rtx comparison)
case CCFPEmode:
case CCFPmode:
- /* These encodings assume that AC=1 in the FPA system control
- byte. This allows us to handle all cases except UNEQ and
- LTGT. */
+ /* We can handle all cases except UNEQ and LTGT. */
switch (comp_code)
{
case GE: return ARM_GE;
@@ -18548,15 +18167,6 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
start of an even numbered register pair. */
return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
- if (TARGET_HARD_FLOAT && TARGET_MAVERICK
- && IS_CIRRUS_REGNUM (regno))
- /* We have outlawed SI values in Cirrus registers because they
- reside in the lower 32 bits, but SF values reside in the
- upper 32 bits. This causes gcc all sorts of grief. We can't
- even split the registers into pairs because Cirrus SI values
- get sign extended to 64bits-- aldyh. */
- return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
-
if (TARGET_HARD_FLOAT && TARGET_VFP
&& IS_VFP_REGNUM (regno))
{
@@ -18606,12 +18216,7 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
/* We only allow integers in the fake hard registers. */
return GET_MODE_CLASS (mode) == MODE_INT;
- /* The only registers left are the FPA registers
- which we only allow to hold FP values. */
- return (TARGET_HARD_FLOAT && TARGET_FPA
- && GET_MODE_CLASS (mode) == MODE_FLOAT
- && regno >= FIRST_FPA_REGNUM
- && regno <= LAST_FPA_REGNUM);
+ return FALSE;
}
/* Implement MODES_TIEABLE_P. */
@@ -18665,9 +18270,6 @@ arm_regno_class (int regno)
if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
return TARGET_THUMB2 ? CC_REG : NO_REGS;
- if (IS_CIRRUS_REGNUM (regno))
- return CIRRUS_REGS;
-
if (IS_VFP_REGNUM (regno))
{
if (regno <= D7_VFP_REGNUM)
@@ -18684,7 +18286,7 @@ arm_regno_class (int regno)
if (IS_IWMMXT_GR_REGNUM (regno))
return IWMMXT_GR_REGS;
- return FPA_REGS;
+ return NO_REGS;
}
/* Handle a special case when computing the offset
@@ -23600,10 +23202,7 @@ arm_file_start (void)
if (TARGET_SOFT_FLOAT)
{
- if (TARGET_VFP)
- fpu_name = "softvfp";
- else
- fpu_name = "softfpa";
+ fpu_name = "softvfp";
}
else
{
@@ -24502,11 +24101,6 @@ arm_dbx_register_number (unsigned int regno)
if (regno < 16)
return regno;
- /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
- compatibility. The EABI defines them as registers 96-103. */
- if (IS_FPA_REGNUM (regno))
- return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
-
if (IS_VFP_REGNUM (regno))
{
/* See comment in arm_dwarf_register_span. */
@@ -24608,12 +24202,6 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
reg_size = 8;
fprintf (asm_out_file, "\t.vsave {");
}
- else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
- {
- /* FPA registers are done differently. */
- asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
- return;
- }
else
/* Unknown register type. */
abort ();
@@ -25310,7 +24898,7 @@ arm_mangle_type (const_tree type)
static const int thumb_core_reg_alloc_order[] =
{
3, 2, 1, 0, 4, 5, 6, 7,
- 14, 12, 8, 9, 10, 11, 13, 15
+ 14, 12, 8, 9, 10, 11
};
/* Adjust register allocation order when compiling for Thumb. */
@@ -25393,13 +24981,6 @@ arm_conditional_register_usage (void)
{
int regno;
- if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA)
- {
- for (regno = FIRST_FPA_REGNUM;
- regno <= LAST_FPA_REGNUM; ++regno)
- fixed_regs[regno] = call_used_regs[regno] = 1;
- }
-
if (TARGET_THUMB1 && optimize_size)
{
/* When optimizing for size on Thumb-1, it's better not
@@ -25416,32 +24997,17 @@ arm_conditional_register_usage (void)
if (TARGET_THUMB1)
fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1;
- if (TARGET_32BIT && TARGET_HARD_FLOAT)
+ if (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP)
{
- if (TARGET_MAVERICK)
- {
- for (regno = FIRST_FPA_REGNUM;
- regno <= LAST_FPA_REGNUM; ++ regno)
- fixed_regs[regno] = call_used_regs[regno] = 1;
- for (regno = FIRST_CIRRUS_FP_REGNUM;
- regno <= LAST_CIRRUS_FP_REGNUM; ++ regno)
- {
- fixed_regs[regno] = 0;
- call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4;
- }
- }
- if (TARGET_VFP)
+ /* VFPv3 registers are disabled when earlier VFP
+ versions are selected due to the definition of
+ LAST_VFP_REGNUM. */
+ for (regno = FIRST_VFP_REGNUM;
+ regno <= LAST_VFP_REGNUM; ++ regno)
{
- /* VFPv3 registers are disabled when earlier VFP
- versions are selected due to the definition of
- LAST_VFP_REGNUM. */
- for (regno = FIRST_VFP_REGNUM;
- regno <= LAST_VFP_REGNUM; ++ regno)
- {
- fixed_regs[regno] = 0;
- call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16
- || regno >= FIRST_VFP_REGNUM + 32;
- }
+ fixed_regs[regno] = 0;
+ call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16
+ || regno >= FIRST_VFP_REGNUM + 32;
}
}
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index c51bce9..4d96c28 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -91,8 +91,6 @@ extern char arm_arch_name[];
builtin_assert ("machine=arm"); \
\
builtin_define (arm_arch_name); \
- if (arm_arch_cirrus) \
- builtin_define ("__MAVERICK__"); \
if (arm_arch_xscale) \
builtin_define ("__XSCALE__"); \
if (arm_arch_iwmmxt) \
@@ -192,8 +190,6 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
/* Use hardware floating point calling convention. */
#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
-#define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA)
-#define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
#define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
#define TARGET_IWMMXT (arm_arch_iwmmxt)
#define TARGET_IWMMXT2 (arm_arch_iwmmxt2)
@@ -221,8 +217,6 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
#define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
/* Thumb-1 only. */
#define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
-/* FPA emulator without LFM. */
-#define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
/* The following two macros concern the ability to execute coprocessor
instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
@@ -326,10 +320,6 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
enum arm_fp_model
{
ARM_FP_MODEL_UNKNOWN,
- /* FPA model (Hardware or software). */
- ARM_FP_MODEL_FPA,
- /* Cirrus Maverick floating point model. */
- ARM_FP_MODEL_MAVERICK,
/* VFP floating point model. */
ARM_FP_MODEL_VFP
};
@@ -408,9 +398,6 @@ extern int thumb1_code;
/* Nonzero if this chip is a StrongARM. */
extern int arm_tune_strongarm;
-/* Nonzero if this chip is a Cirrus variant. */
-extern int arm_arch_cirrus;
-
/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
extern int arm_arch_iwmmxt;
@@ -511,11 +498,6 @@ extern int arm_arch_thumb_hwdiv;
This is always false, even when in big-endian mode. */
#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
-/* Define this if most significant word of doubles is the lowest numbered.
- The rules are different based on whether or not we use FPA-format,
- VFP-format or some other floating point co-processor's format doubles. */
-#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
-
#define UNITS_PER_WORD 4
/* True if natural alignment is used for doubleword types. */
@@ -634,7 +616,7 @@ extern int arm_arch_thumb_hwdiv;
\f
/* Standard register usage. */
-/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
+/* Register allocation in ARM Procedure Call Standard
(S - saved over call).
r0 * argument word/integer result
@@ -650,11 +632,6 @@ extern int arm_arch_thumb_hwdiv;
r14 (lr) link address/workspace
r15 F (pc) program counter
- f0 floating point result
- f1-f3 floating point scratch
-
- f4-f7 S floating point variable
-
cc This is NOT a real register, but is used internally
to represent things that use or set the condition
codes.
@@ -668,11 +645,6 @@ extern int arm_arch_thumb_hwdiv;
*: See TARGET_CONDITIONAL_REGISTER_USAGE */
-/*
- mvf0 Cirrus floating point result
- mvf1-mvf3 Cirrus floating point scratch
- mvf4-mvf15 S Cirrus floating point variable. */
-
/* s0-s15 VFP scratch (aka d0-d7).
s16-s31 S VFP variable (aka d8-d15).
vfpcc Not a real register. Represents the VFP condition
@@ -694,34 +666,30 @@ extern int arm_arch_thumb_hwdiv;
[| saved r2 value |]
[| saved r1 value |]
[| saved r0 value |]
- [| saved f7 value |] three words
- [| saved f6 value |] three words
- [| saved f5 value |] three words
- [| saved f4 value |] three words
r0-r3 are not normally saved in a C function. */
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator. */
-#define FIXED_REGISTERS \
-{ \
- 0,0,0,0,0,0,0,0, \
- 0,0,0,0,0,1,0,1, \
- 0,0,0,0,0,0,0,0, \
- 1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1 \
+#define FIXED_REGISTERS \
+{ \
+ /* Core regs. */ \
+ 0,0,0,0,0,0,0,0, \
+ 0,0,0,0,0,1,0,1, \
+ /* VFP regs. */ \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ /* IWMMXT regs. */ \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1, \
+ /* Specials. */ \
+ 1,1,1,1 \
}
/* 1 for registers not available across function calls.
@@ -732,26 +700,26 @@ extern int arm_arch_thumb_hwdiv;
Aside from that, you can include as many other registers as you like.
The CC is not preserved over function calls on the ARM 6, so it is
easier to assume this for all. SFP is preserved, since FP is. */
-#define CALL_USED_REGISTERS \
-{ \
- 1,1,1,1,0,0,0,0, \
- 0,0,0,0,1,1,1,1, \
- 1,1,1,1,0,0,0,0, \
- 1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1, \
- 1 \
+#define CALL_USED_REGISTERS \
+{ \
+ /* Core regs. */ \
+ 1,1,1,1,0,0,0,0, \
+ 0,0,0,0,1,1,1,1, \
+ /* VFP Regs. */ \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ /* IWMMXT regs. */ \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1, \
+ /* Specials. */ \
+ 1,1,1,1 \
}
#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
@@ -868,34 +836,24 @@ extern int arm_arch_thumb_hwdiv;
/* Register to use for pushing function arguments. */
#define STACK_POINTER_REGNUM SP_REGNUM
-/* ARM floating pointer registers. */
-#define FIRST_FPA_REGNUM 16
-#define LAST_FPA_REGNUM 23
-#define IS_FPA_REGNUM(REGNUM) \
- (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
+#define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1)
+#define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15)
+#define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1)
+#define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3)
-#define FIRST_IWMMXT_GR_REGNUM 43
-#define LAST_IWMMXT_GR_REGNUM 46
-#define FIRST_IWMMXT_REGNUM 47
-#define LAST_IWMMXT_REGNUM 62
#define IS_IWMMXT_REGNUM(REGNUM) \
(((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
#define IS_IWMMXT_GR_REGNUM(REGNUM) \
(((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM 25
+#define FRAME_POINTER_REGNUM 102
/* Base register for access to arguments of the function. */
-#define ARG_POINTER_REGNUM 26
+#define ARG_POINTER_REGNUM 103
-#define FIRST_CIRRUS_FP_REGNUM 27
-#define LAST_CIRRUS_FP_REGNUM 42
-#define IS_CIRRUS_REGNUM(REGNUM) \
- (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
-
-#define FIRST_VFP_REGNUM 63
-#define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
+#define FIRST_VFP_REGNUM 16
+#define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15)
#define LAST_VFP_REGNUM \
(TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
@@ -908,9 +866,9 @@ extern int arm_arch_thumb_hwdiv;
in various parts of the backend, we implement as "fake" single-precision
registers (which would be S32-S63, but cannot be used in that way). The
following macros define these ranges of registers. */
-#define LAST_LO_VFP_REGNUM 94
-#define FIRST_HI_VFP_REGNUM 95
-#define LAST_HI_VFP_REGNUM 126
+#define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31)
+#define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1)
+#define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31)
#define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
((REGNUM) <= LAST_LO_VFP_REGNUM)
@@ -931,11 +889,10 @@ extern int arm_arch_thumb_hwdiv;
((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
&& (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
-/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
-/* + 16 Cirrus registers take us up to 43. */
+/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */
/* Intel Wireless MMX Technology registers add 16 + 4 more. */
-/* VFP (VFP3) adds 32 (64) + 1 more. */
-#define FIRST_PSEUDO_REGISTER 128
+/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
+#define FIRST_PSEUDO_REGISTER 104
#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
@@ -955,11 +912,10 @@ extern int arm_arch_thumb_hwdiv;
This is ordinarily the length in words of a value of mode MODE
but can be less for certain modes in special long registers.
- On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
- mode. */
+ On the ARM core regs are UNITS_PER_WORD bits wide. */
#define HARD_REGNO_NREGS(REGNO, MODE) \
((TARGET_32BIT \
- && REGNO >= FIRST_FPA_REGNUM \
+ && REGNO > PC_REGNUM \
&& REGNO != FRAME_POINTER_REGNUM \
&& REGNO != ARG_POINTER_REGNUM) \
&& !IS_VFP_REGNUM (REGNO) \
@@ -1003,26 +959,44 @@ extern int arm_regs_in_sequence[];
pressure when both single- and double-precision registers are used in a
function. */
+#define VREG(X) (FIRST_VFP_REGNUM + (X))
+#define WREG(X) (FIRST_IWMMXT_REGNUM + (X))
+#define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X))
+
#define REG_ALLOC_ORDER \
{ \
- 3, 2, 1, 0, 12, 14, 4, 5, \
- 6, 7, 8, 10, 9, 11, 13, 15, \
- 16, 17, 18, 19, 20, 21, 22, 23, \
- 27, 28, 29, 30, 31, 32, 33, 34, \
- 35, 36, 37, 38, 39, 40, 41, 42, \
- 43, 44, 45, 46, 47, 48, 49, 50, \
- 51, 52, 53, 54, 55, 56, 57, 58, \
- 59, 60, 61, 62, \
- 24, 25, 26, \
- 95, 96, 97, 98, 99, 100, 101, 102, \
- 103, 104, 105, 106, 107, 108, 109, 110, \
- 111, 112, 113, 114, 115, 116, 117, 118, \
- 119, 120, 121, 122, 123, 124, 125, 126, \
- 78, 77, 76, 75, 74, 73, 72, 71, \
- 70, 69, 68, 67, 66, 65, 64, 63, \
- 79, 80, 81, 82, 83, 84, 85, 86, \
- 87, 88, 89, 90, 91, 92, 93, 94, \
- 127 \
+ /* General registers. */ \
+ 3, 2, 1, 0, 12, 14, 4, 5, \
+ 6, 7, 8, 9, 10, 11, \
+ /* High VFP registers. */ \
+ VREG(32), VREG(33), VREG(34), VREG(35), \
+ VREG(36), VREG(37), VREG(38), VREG(39), \
+ VREG(40), VREG(41), VREG(42), VREG(43), \
+ VREG(44), VREG(45), VREG(46), VREG(47), \
+ VREG(48), VREG(49), VREG(50), VREG(51), \
+ VREG(52), VREG(53), VREG(54), VREG(55), \
+ VREG(56), VREG(57), VREG(58), VREG(59), \
+ VREG(60), VREG(61), VREG(62), VREG(63), \
+ /* VFP argument registers. */ \
+ VREG(15), VREG(14), VREG(13), VREG(12), \
+ VREG(11), VREG(10), VREG(9), VREG(8), \
+ VREG(7), VREG(6), VREG(5), VREG(4), \
+ VREG(3), VREG(2), VREG(1), VREG(0), \
+ /* VFP call-saved registers. */ \
+ VREG(16), VREG(17), VREG(18), VREG(19), \
+ VREG(20), VREG(21), VREG(22), VREG(23), \
+ VREG(24), VREG(25), VREG(26), VREG(27), \
+ VREG(28), VREG(29), VREG(30), VREG(31), \
+ /* IWMMX registers. */ \
+ WREG(0), WREG(1), WREG(2), WREG(3), \
+ WREG(4), WREG(5), WREG(6), WREG(7), \
+ WREG(8), WREG(9), WREG(10), WREG(11), \
+ WREG(12), WREG(13), WREG(14), WREG(15), \
+ WGREG(0), WGREG(1), WGREG(2), WGREG(3), \
+ /* Registers not for general use. */ \
+ CC_REGNUM, VFPCC_REGNUM, \
+ FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
+ SP_REGNUM, PC_REGNUM \
}
/* Use different register alloc ordering for Thumb. */
@@ -1041,27 +1015,26 @@ extern int arm_regs_in_sequence[];
\f
/* Register and constant classes. */
-/* Register classes: used to be simple, just all ARM regs or all FPA regs
- Now that the Thumb is involved it has become more complicated. */
+/* Register classes. */
enum reg_class
{
NO_REGS,
- FPA_REGS,
- CIRRUS_REGS,
+ LO_REGS,
+ STACK_REG,
+ BASE_REGS,
+ HI_REGS,
+ GENERAL_REGS,
+ CORE_REGS,
VFP_D0_D7_REGS,
VFP_LO_REGS,
VFP_HI_REGS,
VFP_REGS,
- IWMMXT_GR_REGS,
IWMMXT_REGS,
- LO_REGS,
- STACK_REG,
- BASE_REGS,
- HI_REGS,
+ IWMMXT_GR_REGS,
CC_REG,
VFPCC_REG,
- GENERAL_REGS,
- CORE_REGS,
+ SFP_REG,
+ AFP_REG,
ALL_REGS,
LIM_REG_CLASSES
};
@@ -1072,22 +1045,20 @@ enum reg_class
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
- "FPA_REGS", \
- "CIRRUS_REGS", \
+ "LO_REGS", \
+ "STACK_REG", \
+ "BASE_REGS", \
+ "HI_REGS", \
+ "GENERAL_REGS", \
+ "CORE_REGS", \
"VFP_D0_D7_REGS", \
"VFP_LO_REGS", \
"VFP_HI_REGS", \
"VFP_REGS", \
- "IWMMXT_GR_REGS", \
"IWMMXT_REGS", \
- "LO_REGS", \
- "STACK_REG", \
- "BASE_REGS", \
- "HI_REGS", \
+ "IWMMXT_GR_REGS", \
"CC_REG", \
"VFPCC_REG", \
- "GENERAL_REGS", \
- "CORE_REGS", \
"ALL_REGS", \
}
@@ -1097,23 +1068,23 @@ enum reg_class
#define REG_CLASS_CONTENTS \
{ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
- { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
- { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
- { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
- { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
- { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
- { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
- { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
- { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
{ 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
{ 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
{ 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
- { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
- { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
- { 0x0000DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
- { 0x0000FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
- { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
+ { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
+ { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
+ { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
+ { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \
+ { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \
+ { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \
+ { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \
+ { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
+ { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000 } /* ALL_REGS */ \
}
/* Any of the VFP register classes. */
@@ -1127,14 +1098,11 @@ enum reg_class
or could index an array. */
#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
-/* FPA registers can't do subreg as all values are reformatted to internal
- precision. In VFPv1, VFP registers could only be accessed in the mode
- they were set, so subregs would be invalid there too. However, we don't
- support VFPv1 at the moment, and the restriction was lifted in VFPv2. */
-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
- (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
- ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
- : 0)
+/* In VFPv1, VFP registers could only be accessed in the mode they
+ were set, so subregs would be invalid there. However, we don't
+ support VFPv1 at the moment, and the restriction was lifted in
+ VFPv2. */
+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) 0
/* The class value for index registers, and the one for base regs. */
#define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
@@ -1196,21 +1164,16 @@ enum reg_class
? coproc_secondary_reload_class (MODE, X, FALSE) : \
(TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
coproc_secondary_reload_class (MODE, X, TRUE) : \
- /* Cannot load constants into Cirrus registers. */ \
- (TARGET_MAVERICK && TARGET_HARD_FLOAT \
- && (CLASS) == CIRRUS_REGS \
- && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
+ (TARGET_32BIT ? \
+ (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
+ && CONSTANT_P (X)) \
? GENERAL_REGS : \
- (TARGET_32BIT ? \
- (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
- && CONSTANT_P (X)) \
- ? GENERAL_REGS : \
- (((MODE) == HImode && ! arm_arch4 \
- && (GET_CODE (X) == MEM \
- || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
- && true_regnum (X) == -1))) \
- ? GENERAL_REGS : NO_REGS) \
- : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
+ (((MODE) == HImode && ! arm_arch4 \
+ && (GET_CODE (X) == MEM \
+ || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
+ && true_regnum (X) == -1))) \
+ ? GENERAL_REGS : NO_REGS) \
+ : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
/* Try a machine-dependent way of reloading an illegitimate address
operand. If we find one, push the reload and jump to WIN. This
@@ -1254,9 +1217,10 @@ do { \
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS.
- ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
+ ARM regs are UNITS_PER_WORD bits.
+ FIXME: Is this true for iWMMX? */
#define CLASS_MAX_NREGS(CLASS, MODE) \
- (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
+ (ARM_NUM_REGS (MODE))
/* If defined, gives a class of registers that cannot be used as the
operand of a SUBREG that changes the mode of the object illegally. */
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 0654564..394ab9a 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -28,18 +28,17 @@
;;---------------------------------------------------------------------------
;; Constants
-;; Register numbers
+;; Register numbers -- All machine registers should be defined here
(define_constants
- [(R0_REGNUM 0) ; First CORE register
- (R1_REGNUM 1) ; Second CORE register
- (IP_REGNUM 12) ; Scratch register
- (SP_REGNUM 13) ; Stack pointer
- (LR_REGNUM 14) ; Return address register
- (PC_REGNUM 15) ; Program counter
- (CC_REGNUM 24) ; Condition code pseudo register
- (LAST_ARM_REGNUM 15) ;
- (FPA_F0_REGNUM 16) ; FIRST_FPA_REGNUM
- (FPA_F7_REGNUM 23) ; LAST_FPA_REGNUM
+ [(R0_REGNUM 0) ; First CORE register
+ (R1_REGNUM 1) ; Second CORE register
+ (IP_REGNUM 12) ; Scratch register
+ (SP_REGNUM 13) ; Stack pointer
+ (LR_REGNUM 14) ; Return address register
+ (PC_REGNUM 15) ; Program counter
+ (LAST_ARM_REGNUM 15) ;
+ (CC_REGNUM 100) ; Condition code pseudo register
+ (VFPCC_REGNUM 101) ; VFP Condition code pseudo register
]
)
;; 3rd operand to select_dominance_cc_mode
@@ -178,7 +177,7 @@
; Floating Point Unit. If we only have floating point emulation, then there
; is no point in scheduling the floating point insns. (Well, for best
; performance we should try and group them together).
-(define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp"
+(define_attr "fpu" "none,vfp"
(const (symbol_ref "arm_fpu_attr")))
; LENGTH of an instruction (in bytes)
diff --git a/gcc/config/arm/linux-elf.h b/gcc/config/arm/linux-elf.h
index 270e12b..82b4bfc 100644
--- a/gcc/config/arm/linux-elf.h
+++ b/gcc/config/arm/linux-elf.h
@@ -92,9 +92,8 @@
} \
while (0)
-/* NWFPE always understands FPA instructions. */
#undef FPUTYPE_DEFAULT
-#define FPUTYPE_DEFAULT "fpe3"
+#define FPUTYPE_DEFAULT "vfp"
/* Call the function profiler with a given profile label. */
#undef ARM_FUNCTION_PROFILER
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 2061414..e8a4a48 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -19,11 +19,6 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>. */
-;; Additional register numbers
-(define_constants
- [(VFPCC_REGNUM 127)]
-)
-
;; The VFP "type" attributes differ from those used in the FPA model.
;; fcpys Single precision cpy.
;; ffariths Single precision abs, neg.
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2012-07-07 16:45 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-06-14 9:40 [arm] Remove obsolete FPA support (2/n): Remove command-line options Richard Earnshaw
2012-06-14 14:43 ` [arm] Remove obsolete FPA support (3/n): Remove FPA patterns from MD files Richard Earnshaw
2012-06-14 16:54 ` [arm] Remove obsolete FPA support (4/n): Remove Maverick " Richard Earnshaw
2012-06-15 14:16 ` [arm] Remove obsolete FPA support (5/n): Clean up predicates and constraints Richard Earnshaw
2012-06-18 1:59 ` [arm] Remove obsolete FPA support (2/n): Remove command-line options Gerald Pfeifer
2012-06-18 15:39 ` [arm] Remove obsolete FPA support (6/n): fix warnings Richard Earnshaw
2012-06-19 14:16 ` [arm] Remove obsolete FPA support (7/n): Tidy up attributes Richard Earnshaw
2012-07-07 16:45 ` [arm] Remove obsolete FPA support (8/n): Cleanup addressing and register usage Richard Earnshaw
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