From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 9F33C3858D1E for ; Wed, 9 Nov 2022 07:46:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9F33C3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.20.4.52]) by gateway (Coremail) with SMTP id _____8BxLLbGWmtjs38FAA--.5997S3; Wed, 09 Nov 2022 15:46:15 +0800 (CST) Received: from [10.20.4.52] (unknown [10.20.4.52]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Axf+DEWmtjWG0PAA--.42948S2; Wed, 09 Nov 2022 15:46:12 +0800 (CST) Subject: Re: [PATCH 2/4] LoongArch: Add ftint{,rm,rp}.{w,l}.{s,d} instructions To: Xi Ruoyao , gcc-patches@gcc.gnu.org Cc: Wang Xuerui , Chenghua Xu , Xiaolin Tang References: <20221109072147.789090-1-xry111@xry111.site> <20221109072147.789090-3-xry111@xry111.site> From: Lulu Cheng Message-ID: <4c43dfab-7562-8d7a-5186-e2c1b7f181a9@loongson.cn> Date: Wed, 9 Nov 2022 15:46:12 +0800 User-Agent: Mozilla/5.0 (X11; Linux mips64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20221109072147.789090-3-xry111@xry111.site> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-CM-TRANSID:AQAAf8Axf+DEWmtjWG0PAA--.42948S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBjvJXoW3Gr4kXr1rXw1UKr13Xr47Arb_yoW7CrWxpa 9rCFn8Kr4rJws7Gw1Fva45ArnIvwsrGrW3uFZxGryUCwsrtr97trW0krW3WFWUW345JryS vr1rCa43WFWjy3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bI8YFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_JrI_Jryl8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4 x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvEwIxGrwCYjI0SjxkI62AI1cAE67vIY487Mx AIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_ Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwI xGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8 JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcV C2z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxU7XTmDUUUU X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,NICE_REPLY_A,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: There is a paragraph in the explanation information for the compile parameter '-fno-fp-int-builtin-inexact' in the gcc.pdf document:     "Do not allow the built-in functions ceil, floor, round and trunc, and their　float and long double variants,     to generate code that raises the “inexact”　floating-point exception for noninteger arguments.     ISO C99 and C11 allow　these functions to raise the “inexact” exception, but ISO/IEC TS 18661-1:2014,     the C bindings to IEEE 754-2008, as integrated into ISO C2X, does not allow　these functions to do so." So I think the implementation of these functions needs to be confirmed again. Or am I misinterpreting this description?:-[ 在 2022/11/9 下午3:21, Xi Ruoyao 写道: > This allows to optimize the following builtins if -fno-math-errno: > > - __builtin_lrint{,f} > - __builtin_lfloor{,f} > - __builtin_lceil{,f} > > Inspired by > https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605287.html. > > ANYFI is added so the compiler won't try ftint.l.s if -mfpu=32. If we > simply used GPR here an ICE would be triggered with __builtin_lrintf > and -mfpu=32. > > Note that the .w.{s,d} variants are not tested because we don't support > ILP32 for now. > > gcc/ChangeLog: > > * config/loongarch/loongarch.md (UNSPEC_FTINT): New unspec. > (UNSPEC_FTINTRM): Likewise. > (UNSPEC_FTINTRP): Likewise. > (LRINT): New define_int_iterator. > (lrint_pattern): New define_int_attr. > (lrint_submenmonic): Likewise. > (ANYFI): New define_mode_iterator. > (lrint): New instruction template. > > gcc/testsuite/ChangeLog: > > * gcc.target/loongarch/ftint.c: New test. > --- > gcc/config/loongarch/loongarch.md | 28 ++++++++++++++ > gcc/testsuite/gcc.target/loongarch/ftint.c | 44 ++++++++++++++++++++++ > 2 files changed, 72 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/loongarch/ftint.c > > diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md > index a14ab14ac24..35cef272060 100644 > --- a/gcc/config/loongarch/loongarch.md > +++ b/gcc/config/loongarch/loongarch.md > @@ -38,6 +38,9 @@ (define_c_enum "unspec" [ > UNSPEC_FMAX > UNSPEC_FMIN > UNSPEC_FCOPYSIGN > + UNSPEC_FTINT > + UNSPEC_FTINTRM > + UNSPEC_FTINTRP > > ;; Override return address for exception handling. > UNSPEC_EH_RETURN > @@ -374,6 +377,11 @@ (define_mode_iterator QHWD [QI HI SI (DI "TARGET_64BIT")]) > (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT") > (DF "TARGET_DOUBLE_FLOAT")]) > > +;; Iterator for fixed-point modes which can be hold by a hardware > +;; floating-point register. > +(define_mode_iterator ANYFI [(SI "TARGET_HARD_FLOAT") > + (DI "TARGET_DOUBLE_FLOAT")]) > + > ;; A mode for which moves involving FPRs may need to be split. > (define_mode_iterator SPLITF > [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") > @@ -515,6 +523,16 @@ (define_code_attr fcond [(unordered "cun") > (define_code_attr sel [(eq "masknez") (ne "maskeqz")]) > (define_code_attr selinv [(eq "maskeqz") (ne "masknez")]) > > +;; Iterator and attributes for floating-point to fixed-point conversion > +;; instructions. > +(define_int_iterator LRINT [UNSPEC_FTINT UNSPEC_FTINTRM UNSPEC_FTINTRP]) > +(define_int_attr lrint_pattern [(UNSPEC_FTINT "lrint") > + (UNSPEC_FTINTRM "lfloor") > + (UNSPEC_FTINTRP "lceil")]) > +(define_int_attr lrint_submenmonic [(UNSPEC_FTINT "") > + (UNSPEC_FTINTRM "rm") > + (UNSPEC_FTINTRP "rp")]) > + > ;; > ;; .................... > ;; > @@ -2022,6 +2040,16 @@ (define_insn "rint2" > [(set_attr "type" "fcvt") > (set_attr "mode" "")]) > > +;; Convert floating-point numbers to integers > +(define_insn "2" > + [(set (match_operand:ANYFI 0 "register_operand" "=f") > + (unspec:ANYFI [(match_operand:ANYF 1 "register_operand" "f")] > + LRINT))] > + "TARGET_HARD_FLOAT" > + "ftint.. %0,%1" > + [(set_attr "type" "fcvt") > + (set_attr "mode" "")]) > + > ;; Load the low word of operand 0 with operand 1. > (define_insn "load_low" > [(set (match_operand:SPLITF 0 "register_operand" "=f,f") > diff --git a/gcc/testsuite/gcc.target/loongarch/ftint.c b/gcc/testsuite/gcc.target/loongarch/ftint.c > new file mode 100644 > index 00000000000..9c3c3a8a756 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/loongarch/ftint.c > @@ -0,0 +1,44 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mabi=lp64d -mdouble-float -fno-math-errno" } */ > +/* { dg-final { scan-assembler "ftint\\.l\\.s" } } */ > +/* { dg-final { scan-assembler "ftint\\.l\\.d" } } */ > +/* { dg-final { scan-assembler "ftintrm\\.l\\.s" } } */ > +/* { dg-final { scan-assembler "ftintrm\\.l\\.d" } } */ > +/* { dg-final { scan-assembler "ftintrp\\.l\\.s" } } */ > +/* { dg-final { scan-assembler "ftintrp\\.l\\.d" } } */ > + > +long > +my_lrint (double a) > +{ > + return __builtin_lrint (a); > +} > + > +long > +my_lrintf (float a) > +{ > + return __builtin_lrintf (a); > +} > + > +long > +my_lfloor (double a) > +{ > + return __builtin_lfloor (a); > +} > + > +long > +my_lfloorf (float a) > +{ > + return __builtin_lfloorf (a); > +} > + > +long > +my_lceil (double a) > +{ > + return __builtin_lceil (a); > +} > + > +long > +my_lceilf (float a) > +{ > + return __builtin_lceilf (a); > +}