From: Sudakshina Das <Sudi.Das@arm.com>
To: Srinath Parvathaneni <Srinath.Parvathaneni@arm.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Cc: nd <nd@arm.com>, Richard Earnshaw <Richard.Earnshaw@arm.com>,
James Greenhalgh <James.Greenhalgh@arm.com>
Subject: Re: [PATCH 1/2][GCC][AArch64] Implement hint intrinsics for AArch64
Date: Fri, 11 Jan 2019 18:22:00 -0000 [thread overview]
Message-ID: <4c8cf93a-b129-fb7d-7871-514f8ce0c0ef@arm.com> (raw)
In-Reply-To: <3b938af0-7978-2646-80d9-b39ed2d04ba1@arm.com>
Hi Srinath
On 10/01/19 19:20, Srinath Parvathaneni wrote:
> Hi All,
>
> This patch implements the ACLE hint intrinsics (nop, yield, wfe, wfi,
> sev and sevl), for AArch64.
>
> The instructions are documented in the ArmARM[1] and the intrinsics
> specification will be
> published on the Arm website [2].
>
> [1]
> https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
> [2]
> http://infocenter.arm.com/help/topic/com.arm.doc.ihi0053c/IHI0053C_acle_2_0.pdf
>
> Bootstrapped on aarch64-none-linux-gnu and regression tested on
> aarch64-none-elf with no regressions.
>
> Ok for trunk? If ok, could someone commit the patch on my behalf, I
> don't have commit rights.
>
> Thanks,
> Srinath
>
> gcc/ChangeLog:
>
> 2019-01-10 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
>
> * config/aarch64/aarch64.md (yield): New pattern name.
> (wfe): Likewise.
> (wfi): Likewise.
> (sev): Likewise.
> (sevl): Likewise.
> (UNSPECV_YIELD): New volatile unspec.
> (UNSPECV_WFE): Likewise.
> (UNSPECV_WFI): Likewise.
> (UNSPECV_SEV): Likewise.
> (UNSPECV_SEVL): Likewise.
> * config/aarch64/aarch64-builtins.c (aarch64_builtins):
> AARCH64_SYSHINTOP_BUILTIN_NOP: New builtin.
> AARCH64_SYSHINTOP_BUILTIN_YIELD: Likewise.
> AARCH64_SYSHINTOP_BUILTIN_WFE: Likewise.
> AARCH64_SYSHINTOP_BUILTIN_WFI: Likewise.
> AARCH64_SYSHINTOP_BUILTIN_SEV: Likewise.
> AARCH64_SYSHINTOP_BUILTIN_SEVL: Likewise.
> (aarch64_init_syshintop_builtins): New function.
> (aarch64_init_builtins): New call statement.
> (aarch64_expand_builtin): New case.
> * config/aarch64/arm_acle.h (__nop ): New inline function.
> (__yield): Likewise.
> (__sev): Likewise.
> (__sevl): Likewise.
> (__wfi): Likewise.
> (__wfe): Likewise.
>
> gcc/testsuite/ChangeLog:
>
> 2019-01-10 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
>
> * gcc.target/aarch64/acle/hint-1.c: New test.
> * gcc.target/aarch64/acle/hint-2.c: Likewise.
>
>
Thank you for doing this and I am not a maintainer. I have some comments
bellow:
diff --git a/gcc/config/aarch64/aarch64-builtins.c
b/gcc/config/aarch64/aarch64-builtins.c
index
8cced94567008e28b1761ec8771589a3925f2904..d5424f98df1f5c8f206cbded097bdd2dfcd1ca8e
100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -399,6 +399,13 @@ enum aarch64_builtins
AARCH64_PAUTH_BUILTIN_AUTIA1716,
AARCH64_PAUTH_BUILTIN_PACIA1716,
AARCH64_PAUTH_BUILTIN_XPACLRI,
+ /* System Hint Operation Builtins for AArch64. */
+ AARCH64_SYSHINTOP_BUILTIN_NOP,
+ AARCH64_SYSHINTOP_BUILTIN_YIELD,
+ AARCH64_SYSHINTOP_BUILTIN_WFE,
+ AARCH64_SYSHINTOP_BUILTIN_WFI,
+ AARCH64_SYSHINTOP_BUILTIN_SEV,
+ AARCH64_SYSHINTOP_BUILTIN_SEVL,
AARCH64_BUILTIN_MAX
};
Is there any reason for the naming? They don't seem to be part of any
extensions? IMHO AARCH64_BUILTIN_NOP, etc looks cleaner and follows
other builtins which are not part of any extensions.
...
@@ -1395,6 +1436,29 @@ aarch64_expand_builtin (tree exp,
}
return target;
+ case AARCH64_SYSHINTOP_BUILTIN_NOP:
+ emit_insn (GEN_FCN (CODE_FOR_nop) ());
+ return gen_reg_rtx (VOIDmode);
+
Needs a newline before the new case.
...
+(define_insn "yield"
+ [(unspec_volatile [(const_int 0)] UNSPECV_YIELD)]
+ ""
+ "yield"
+ [(set_attr "type" "coproc")]
+)
I don't believe setting the type to coproc in AArch64 is correct.
Likewise for the other instructions.
...
+/* Test the nop ACLE hint intrinsic */
+/* { dg-do compile } */
+/* { dg-additional-options "-O0" } */
+/* { dg-options "-march=armv8-a" } */
+
+#include "arm_acle.h"
+
+void
+test_hint (void)
+{
+ __nop ();
+}
+
+/* { dg-final { scan-assembler-times "\tnop" 3 } } */
Just curious, why are there 3 nops here?
Thanks
Sudi
>
>
>
>
next prev parent reply other threads:[~2019-01-11 18:22 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-10 19:20 Srinath Parvathaneni
2019-01-11 18:22 ` Sudakshina Das [this message]
2022-11-01 20:04 ` Andrew Pinski
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