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From: Jeff Law <jeffreyalaw@gmail.com>
To: Richard Biener <richard.guenther@gmail.com>
Cc: Vineet Gupta <vineetg@rivosinc.com>,
	gcc-patches@gcc.gnu.org, kito.cheng@gmail.com,
	Palmer Dabbelt <palmer@rivosinc.com>,
	gnu-toolchain@rivosinc.com, Robin Dapp <rdapp.gcc@gmail.com>
Subject: Re: scheduler queue flush (was Re: [gcc-15 0/3] RISC-V improve stack/array access by constant mat tweak)
Date: Fri, 22 Mar 2024 06:29:36 -0600	[thread overview]
Message-ID: <4c91a6fe-a106-450c-b540-16cc46bff23d@gmail.com> (raw)
In-Reply-To: <CAFiYyc1y_Lan1iw=xUsuWHaXsL2LyYHYsjH=ZrQ1942LfcAKnQ@mail.gmail.com>



On 3/22/24 2:47 AM, Richard Biener wrote:
> On Thu, Mar 21, 2024 at 8:56 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>>
>>
>>
>> On 3/21/24 11:19 AM, Vineet Gupta wrote:
>>
>>>>
>>>> So if we go back to Robin's observation that scheduling dramatically
>>>> increases the instruction count, perhaps we try a run with
>>>> -fno-schedule-insns -fno-schedule-insns2 and see how the instruction
>>>> counts compare.
>>>
>>> Oh yeah ! Robin hinted to this in Tues patchworks meeting too
>>>
>>> default           : 2,565,319,368,591
>>> 128       : 2,509,741,035,068
>>> 256       : 2,527,817,813,612
>>> no-sched{,2}: 1,295,520,567,376
>> Now we're getting somewhere.  That's in line with expectations.
>>
>> I would strongly suspect it's -fno-schedule-insns rather than
>> -fno-schedule-insns2.  The former turns off scheduling before register
>> allocation, the second turns it off after register allocation.  So if
>> our theory about spilling is correct, then it must be the first since
>> the second won't affect register allocation.   While I can speculate
>> about other potential scheduler impacts, spilling due to sched1's
>> actions is by far the most likely.
> 
> Another option is to enable -fsched-pressure which should help with
> this issue.
In theory we're already using that by default -- it's part of what makes 
me so curious to understand what's going on.

jeff


  reply	other threads:[~2024-03-22 12:29 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-16 17:35 [gcc-15 0/3] RISC-V improve stack/array access by constant mat tweak Vineet Gupta
2024-03-16 17:35 ` [gcc-15 1/3] RISC-V: avoid LUI based const materialization ... [part of PR/106265] Vineet Gupta
2024-03-16 20:28   ` Jeff Law
2024-03-19  0:07     ` Vineet Gupta
2024-03-23  5:59       ` Jeff Law
2024-03-16 17:35 ` [gcc-15 2/3] RISC-V: avoid LUI based const mat: keep stack offsets aligned Vineet Gupta
2024-03-16 20:21   ` Jeff Law
2024-03-19  0:27     ` Vineet Gupta
2024-03-19  6:48       ` Andrew Waterman
2024-03-19 13:10         ` Jeff Law
2024-03-19 20:05           ` Vineet Gupta
2024-03-19 20:58             ` Andrew Waterman
2024-03-19 21:17             ` Palmer Dabbelt
2024-03-20 18:57             ` Jeff Law
2024-03-23  6:05             ` Jeff Law
2024-03-16 17:35 ` [gcc-15 3/3] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] Vineet Gupta
2024-03-16 20:27   ` Jeff Law
2024-03-19  4:41 ` [gcc-15 0/3] RISC-V improve stack/array access by constant mat tweak Jeff Law
2024-03-21  0:45   ` Vineet Gupta
2024-03-21 14:36   ` scheduler queue flush (was Re: [gcc-15 0/3] RISC-V improve stack/array access by constant mat tweak) Vineet Gupta
2024-03-21 14:45     ` Jeff Law
2024-03-21 17:19       ` Vineet Gupta
2024-03-21 19:56         ` Jeff Law
2024-03-22  0:34           ` scheduler queue flush Vineet Gupta
2024-03-22  8:47           ` scheduler queue flush (was Re: [gcc-15 0/3] RISC-V improve stack/array access by constant mat tweak) Richard Biener
2024-03-22 12:29             ` Jeff Law [this message]
2024-03-22 16:56               ` Vineet Gupta
2024-03-25  3:05         ` Jeff Law

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