From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 2E9C83858C62 for ; Thu, 23 Nov 2023 08:42:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2E9C83858C62 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2E9C83858C62 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700728957; cv=none; b=OMBdl5WSRyOT0oDbiTpwiLbPy2w/PtSmCOYHXZkTngDWzw0srkHH3alsIwlacql5GMKIn2MZTBKj5hs5DLtn+ym9ACW0v5Bw1r7KWYK+YF8nej8mChycUvJRtNF7Stamzofj2riMI1DRLlzlEVj2aQV7MdCXdKmsb6l7vQSwf3A= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700728957; c=relaxed/simple; bh=I1CI0f62C6TOdehPvfoeKNVapdkrIJ2PZ9UUndFzg7s=; h=Subject:To:From:Message-ID:Date:MIME-Version; b=IuO6rLUGz070d6iz6Nc60L6peffx9Rg1H4idrEzWWcA5HpPZFJ1+kzE9t+FqcRfTqGJKZfVfsiseG54QmT318THU7NhAn+BmAcX2xfQJiSSw77MGrYDctbrpikF5cDCZ05j3h8Qg3VeD456N05rJqm3eyZ737x24nkHTohnackQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8BxbOp0EF9lFTo8AA--.26280S3; Thu, 23 Nov 2023 16:42:28 +0800 (CST) Received: from [10.20.4.107] (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxfNxvEF9lKoJKAA--.33593S3; Thu, 23 Nov 2023 16:42:23 +0800 (CST) Subject: Re: [PATCH v3 3/5] LoongArch: Use standard pattern name and RTX code for LSX/LASX rotate shift To: Xi Ruoyao , gcc-patches@gcc.gnu.org Cc: i@xen0n.name, xuchenghua@loongson.cn References: <20231120004728.205167-1-xry111@xry111.site> <20231120004728.205167-4-xry111@xry111.site> From: chenglulu Message-ID: <4ccc7215-c4f7-0329-a5ae-f55c9f90b6d0@loongson.cn> Date: Thu, 23 Nov 2023 16:42:23 +0800 User-Agent: Mozilla/5.0 (X11; Linux loongarch64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20231120004728.205167-4-xry111@xry111.site> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-CM-TRANSID:AQAAf8CxfNxvEF9lKoJKAA--.33593S3 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW3Kr43WF1DKF4kCFyDCryDArc_yoWDtw15pr ZrWa4kArWUXF9Fgw1vyay5Xr45tr17Gw4Uua92vwnFyF4qq347Ary0kFZ3XFy7Ww1rCrn7 W3yrWa15ZrZruwcCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUvIb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv 67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41lc7I2V7IY0VAS07 AlzVAYIcxG8wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02 F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw 1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7Cj xVAFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r 4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07jO uc_UUUUU= X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,MIME_CHARSET_FARAWAY,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM. Thanks. ÔÚ 2023/11/20 ÉÏÎç8:47, Xi Ruoyao дµÀ: > Remove unnecessary UNSPECs and make the [x]vrotr[i] instructions useful > with GNU vectors and auto vectorization. > > gcc/ChangeLog: > > * config/loongarch/lsx.md (bitimm): Move to ... > (UNSPEC_LSX_VROTR): Remove. > (lsx_vrotr_): Remove. > (lsx_vrotri_): Remove. > * config/loongarch/lasx.md (UNSPEC_LASX_XVROTR): Remove. > (lsx_vrotr_): Remove. > (lsx_vrotri_): Remove. > * config/loongarch/simd.md (bitimm): ... here. Expand it to > cover LASX modes. > (vrotr3): New define_insn. > (vrotri3): New define_insn. > * config/loongarch/loongarch-builtins.cc: > (CODE_FOR_lsx_vrotr_b): Use standard pattern name. > (CODE_FOR_lsx_vrotr_h): Likewise. > (CODE_FOR_lsx_vrotr_w): Likewise. > (CODE_FOR_lsx_vrotr_d): Likewise. > (CODE_FOR_lasx_xvrotr_b): Likewise. > (CODE_FOR_lasx_xvrotr_h): Likewise. > (CODE_FOR_lasx_xvrotr_w): Likewise. > (CODE_FOR_lasx_xvrotr_d): Likewise. > (CODE_FOR_lsx_vrotri_b): Define to standard pattern name. > (CODE_FOR_lsx_vrotri_h): Likewise. > (CODE_FOR_lsx_vrotri_w): Likewise. > (CODE_FOR_lsx_vrotri_d): Likewise. > (CODE_FOR_lasx_xvrotri_b): Likewise. > (CODE_FOR_lasx_xvrotri_h): Likewise. > (CODE_FOR_lasx_xvrotri_w): Likewise. > (CODE_FOR_lasx_xvrotri_d): Likewise. > > gcc/testsuite/ChangeLog: > > * gcc.target/loongarch/vect-rotr.c: New test. > --- > gcc/config/loongarch/lasx.md | 22 ------------ > gcc/config/loongarch/loongarch-builtins.cc | 16 +++++++++ > gcc/config/loongarch/lsx.md | 28 --------------- > gcc/config/loongarch/simd.md | 29 +++++++++++++++ > .../gcc.target/loongarch/vect-rotr.c | 36 +++++++++++++++++++ > 5 files changed, 81 insertions(+), 50 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/loongarch/vect-rotr.c > > diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md > index 023a023b44e..116b30c0774 100644 > --- a/gcc/config/loongarch/lasx.md > +++ b/gcc/config/loongarch/lasx.md > @@ -138,7 +138,6 @@ (define_c_enum "unspec" [ > UNSPEC_LASX_XVHSUBW_Q_D > UNSPEC_LASX_XVHADDW_QU_DU > UNSPEC_LASX_XVHSUBW_QU_DU > - UNSPEC_LASX_XVROTR > UNSPEC_LASX_XVADD_Q > UNSPEC_LASX_XVSUB_Q > UNSPEC_LASX_XVREPLVE > @@ -4232,18 +4231,6 @@ (define_insn "lasx_xvhsubw_qu_du" > [(set_attr "type" "simd_int_arith") > (set_attr "mode" "V4DI")]) > > -;;XVROTR.B XVROTR.H XVROTR.W XVROTR.D > -;;TODO-478 > -(define_insn "lasx_xvrotr_" > - [(set (match_operand:ILASX 0 "register_operand" "=f") > - (unspec:ILASX [(match_operand:ILASX 1 "register_operand" "f") > - (match_operand:ILASX 2 "register_operand" "f")] > - UNSPEC_LASX_XVROTR))] > - "ISA_HAS_LASX" > - "xvrotr.\t%u0,%u1,%u2" > - [(set_attr "type" "simd_int_arith") > - (set_attr "mode" "")]) > - > ;;XVADD.Q > ;;TODO2 > (define_insn "lasx_xvadd_q" > @@ -4426,15 +4413,6 @@ (define_insn "lasx_xvexth_qu_du" > [(set_attr "type" "simd_fcvt") > (set_attr "mode" "V4DI")]) > > -(define_insn "lasx_xvrotri_" > - [(set (match_operand:ILASX 0 "register_operand" "=f") > - (rotatert:ILASX (match_operand:ILASX 1 "register_operand" "f") > - (match_operand 2 "const__operand" "")))] > - "ISA_HAS_LASX" > - "xvrotri.\t%u0,%u1,%2" > - [(set_attr "type" "simd_shf") > - (set_attr "mode" "")]) > - > (define_insn "lasx_xvextl_q_d" > [(set (match_operand:V4DI 0 "register_operand" "=f") > (unspec:V4DI [(match_operand:V4DI 1 "register_operand" "f")] > diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc > index a6fcc1c731e..5d037ab7f10 100644 > --- a/gcc/config/loongarch/loongarch-builtins.cc > +++ b/gcc/config/loongarch/loongarch-builtins.cc > @@ -369,6 +369,14 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) > #define CODE_FOR_lsx_vsrli_h CODE_FOR_vlshrv8hi3 > #define CODE_FOR_lsx_vsrli_w CODE_FOR_vlshrv4si3 > #define CODE_FOR_lsx_vsrli_d CODE_FOR_vlshrv2di3 > +#define CODE_FOR_lsx_vrotr_b CODE_FOR_vrotrv16qi3 > +#define CODE_FOR_lsx_vrotr_h CODE_FOR_vrotrv8hi3 > +#define CODE_FOR_lsx_vrotr_w CODE_FOR_vrotrv4si3 > +#define CODE_FOR_lsx_vrotr_d CODE_FOR_vrotrv2di3 > +#define CODE_FOR_lsx_vrotri_b CODE_FOR_rotrv16qi3 > +#define CODE_FOR_lsx_vrotri_h CODE_FOR_rotrv8hi3 > +#define CODE_FOR_lsx_vrotri_w CODE_FOR_rotrv4si3 > +#define CODE_FOR_lsx_vrotri_d CODE_FOR_rotrv2di3 > #define CODE_FOR_lsx_vsub_b CODE_FOR_subv16qi3 > #define CODE_FOR_lsx_vsub_h CODE_FOR_subv8hi3 > #define CODE_FOR_lsx_vsub_w CODE_FOR_subv4si3 > @@ -634,6 +642,14 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) > #define CODE_FOR_lasx_xvsrli_h CODE_FOR_vlshrv16hi3 > #define CODE_FOR_lasx_xvsrli_w CODE_FOR_vlshrv8si3 > #define CODE_FOR_lasx_xvsrli_d CODE_FOR_vlshrv4di3 > +#define CODE_FOR_lasx_xvrotr_b CODE_FOR_vrotrv32qi3 > +#define CODE_FOR_lasx_xvrotr_h CODE_FOR_vrotrv16hi3 > +#define CODE_FOR_lasx_xvrotr_w CODE_FOR_vrotrv8si3 > +#define CODE_FOR_lasx_xvrotr_d CODE_FOR_vrotrv4di3 > +#define CODE_FOR_lasx_xvrotri_b CODE_FOR_rotrv32qi3 > +#define CODE_FOR_lasx_xvrotri_h CODE_FOR_rotrv16hi3 > +#define CODE_FOR_lasx_xvrotri_w CODE_FOR_rotrv8si3 > +#define CODE_FOR_lasx_xvrotri_d CODE_FOR_rotrv4di3 > #define CODE_FOR_lasx_xvsub_b CODE_FOR_subv32qi3 > #define CODE_FOR_lasx_xvsub_h CODE_FOR_subv16hi3 > #define CODE_FOR_lasx_xvsub_w CODE_FOR_subv8si3 > diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md > index 537afaf9625..23239993404 100644 > --- a/gcc/config/loongarch/lsx.md > +++ b/gcc/config/loongarch/lsx.md > @@ -141,7 +141,6 @@ (define_c_enum "unspec" [ > UNSPEC_LSX_VMADDWOD > UNSPEC_LSX_VMADDWOD2 > UNSPEC_LSX_VMADDWOD3 > - UNSPEC_LSX_VROTR > UNSPEC_LSX_VADD_Q > UNSPEC_LSX_VSUB_Q > UNSPEC_LSX_VEXTH_Q_D > @@ -363,14 +362,6 @@ (define_mode_attr bitmask > (V8HI "exp_8") > (V16QI "exp_16")]) > > -;; This attribute is used to form an immediate operand constraint using > -;; "const__operand". > -(define_mode_attr bitimm > - [(V16QI "uimm3") > - (V8HI "uimm4") > - (V4SI "uimm5") > - (V2DI "uimm6")]) > - > (define_expand "vec_init" > [(match_operand:LSX 0 "register_operand") > (match_operand:LSX 1 "")] > @@ -4152,16 +4143,6 @@ (define_insn "lsx_vmaddwod_q_du_d" > [(set_attr "type" "simd_int_arith") > (set_attr "mode" "V2DI")]) > > -(define_insn "lsx_vrotr_" > - [(set (match_operand:ILSX 0 "register_operand" "=f") > - (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f") > - (match_operand:ILSX 2 "register_operand" "f")] > - UNSPEC_LSX_VROTR))] > - "ISA_HAS_LSX" > - "vrotr.\t%w0,%w1,%w2" > - [(set_attr "type" "simd_int_arith") > - (set_attr "mode" "")]) > - > (define_insn "lsx_vadd_q" > [(set (match_operand:V2DI 0 "register_operand" "=f") > (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f") > @@ -4255,15 +4236,6 @@ (define_insn "lsx_vexth_qu_du" > [(set_attr "type" "simd_fcvt") > (set_attr "mode" "V2DI")]) > > -(define_insn "lsx_vrotri_" > - [(set (match_operand:ILSX 0 "register_operand" "=f") > - (rotatert:ILSX (match_operand:ILSX 1 "register_operand" "f") > - (match_operand 2 "const__operand" "")))] > - "ISA_HAS_LSX" > - "vrotri.\t%w0,%w1,%2" > - [(set_attr "type" "simd_shf") > - (set_attr "mode" "")]) > - > (define_insn "lsx_vextl_q_d" > [(set (match_operand:V2DI 0 "register_operand" "=f") > (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")] > diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md > index 79324183233..6937477e3df 100644 > --- a/gcc/config/loongarch/simd.md > +++ b/gcc/config/loongarch/simd.md > @@ -72,6 +72,13 @@ (define_mode_attr elmbits [(V2DI "64") (V4DI "64") > (V8HI "16") (V16HI "16") > (V16QI "8") (V32QI "8")]) > > +;; This attribute is used to form an immediate operand constraint using > +;; "const__operand". > +(define_mode_attr bitimm [(V16QI "uimm3") (V32QI "uimm3") > + (V8HI "uimm4") (V16HI "uimm4") > + (V4SI "uimm5") (V8SI "uimm5") > + (V2DI "uimm6") (V4DI "uimm6")]) > + > ;; ======================================================================= > ;; For many LASX instructions, the only difference of it from the LSX > ;; counterpart is the length of vector operands. Describe these LSX/LASX > @@ -203,6 +210,28 @@ (define_insn "mul3_highpart" > [(set_attr "type" "simd_int_arith") > (set_attr "mode" "")]) > > +;; vrotr.{b/h/w/d} > + > +(define_insn "vrotr3" > + [(set (match_operand:IVEC 0 "register_operand" "=f") > + (rotatert:IVEC (match_operand:IVEC 1 "register_operand" "f") > + (match_operand:IVEC 2 "register_operand" "f")))] > + "" > + "vrotr.\t%0,%1,%2" > + [(set_attr "type" "simd_int_arith") > + (set_attr "mode" "")]) > + > +;; vrotri.{b/h/w/d} > + > +(define_insn "rotr3" > + [(set (match_operand:IVEC 0 "register_operand" "=f") > + (rotatert:IVEC (match_operand:IVEC 1 "register_operand" "f") > + (match_operand:SI 2 "const__operand")))] > + "" > + "vrotri.\t%0,%1,%2"; > + [(set_attr "type" "simd_int_arith") > + (set_attr "mode" "")]) > + > ; The LoongArch SX Instructions. > (include "lsx.md") > > diff --git a/gcc/testsuite/gcc.target/loongarch/vect-rotr.c b/gcc/testsuite/gcc.target/loongarch/vect-rotr.c > new file mode 100644 > index 00000000000..733c36334ce > --- /dev/null > +++ b/gcc/testsuite/gcc.target/loongarch/vect-rotr.c > @@ -0,0 +1,36 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mlasx" } */ > +/* { dg-final { scan-assembler "\tvrotr\.w\t" } } */ > +/* { dg-final { scan-assembler "\txvrotr\.w\t" } } */ > +/* { dg-final { scan-assembler "\tvrotri\.w\t\[^\n\]*7\n" } } */ > +/* { dg-final { scan-assembler "\txvrotri\.w\t\[^\n\]*7\n" } } */ > + > +unsigned int a[8], b[8]; > + > +void > +test1 (void) > +{ > + for (int i = 0; i < 4; i++) > + a[i] = a[i] >> b[i] | a[i] << (32 - b[i]); > +} > + > +void > +test2 (void) > +{ > + for (int i = 0; i < 8; i++) > + a[i] = a[i] >> b[i] | a[i] << (32 - b[i]); > +} > + > +void > +test3 (void) > +{ > + for (int i = 0; i < 4; i++) > + a[i] = a[i] >> 7 | a[i] << 25; > +} > + > +void > +test4 (void) > +{ > + for (int i = 0; i < 8; i++) > + a[i] = a[i] >> 7 | a[i] << 25; > +}