From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [IPv6:2001:470:683e::1]) by sourceware.org (Postfix) with ESMTPS id 85FE13858D28 for ; Thu, 7 Jul 2022 02:29:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 85FE13858D28 Received: from [IPv6:240e:358:1139:6500:dc73:854d:832e:4] (unknown [IPv6:240e:358:1139:6500:dc73:854d:832e:4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id F0A28669E2; Wed, 6 Jul 2022 22:29:38 -0400 (EDT) Message-ID: <4d5d246ff682d35fe89344410f7e733fb3e22947.camel@xry111.site> Subject: [PATCH 2/2] loongarch: avoid unnecessary sign-extend after 32-bit division From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: Lulu Cheng , Chenghua Xu , Wang Xuerui Date: Thu, 07 Jul 2022 10:29:33 +0800 In-Reply-To: <535ed6eaa19df38309a773f9bf2542c65f715b6b.camel@xry111.site> References: <535ed6eaa19df38309a773f9bf2542c65f715b6b.camel@xry111.site> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.3 MIME-Version: 1.0 X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FROM_SUSPICIOUS_NTLD, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_PDS_OTHER_BAD_TLD, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jul 2022 02:29:46 -0000 Like add.w/sub.w/mul.w, div.w/mod.w/div.wu/mod.wu also sign-extend the output on LA64. But, LoongArch v1.00 mandates that the inputs of 32-bit division to be sign-extended so we have to expand 32-bit division into RTL sequences. We defined div.w/mod.w/div.wu/mod.wu as a (DI, DI) -> SI instruction. This definition does not indicate the fact that these instructions will store the result as sign-extended value in a 64-bit GR. Then the compiler would emit unnecessary sign-extend operations. For example: int div(int a, int b) { return a / b; } was compiled to: div.w $r4, $r4, $r5 slli.w $r4, $r4, 0 # this is unnecessary jr $r1 To remove this unnecessary operation, we change the division instructions to (DI, DI) -> DI and describe the sign-extend behavior explicitly in the RTL template. In the expander for 32-bit division we then use simplify_gen_subreg to extract the lower 32 bits. gcc/ChangeLog: * config/loongarch/loongarch.md (di3_fake): Describe the sign-extend of result in the RTL template. (3): Adjust for di3_fake change. gcc/testsuite/ChangeLog: * gcc.target/loongarch/div-4.c: New test. --- gcc/config/loongarch/loongarch.md | 12 ++++++++---- gcc/testsuite/gcc.target/loongarch/div-4.c | 9 +++++++++ 2 files changed, 17 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/div-4.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loong= arch.md index b002eb2ac22..0202f73efae 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -752,6 +752,7 @@ (define_expand "3" { rtx reg1 =3D gen_reg_rtx (DImode); rtx reg2 =3D gen_reg_rtx (DImode); + rtx rd =3D gen_reg_rtx (DImode); =20 operands[1] =3D gen_rtx_SIGN_EXTEND (word_mode, operands[1]); operands[2] =3D gen_rtx_SIGN_EXTEND (word_mode, operands[2]); @@ -759,7 +760,9 @@ (define_expand "3" emit_insn (gen_rtx_SET (reg1, operands[1])); emit_insn (gen_rtx_SET (reg2, operands[2])); =20 - emit_insn (gen_di3_fake (operands[0], reg1, reg2)); + emit_insn (gen_di3_fake (rd, reg1, reg2)); + emit_insn (gen_rtx_SET (operands[0], + simplify_gen_subreg (SImode, rd, DImode, 0))); DONE; } }) @@ -781,9 +784,10 @@ (define_insn "*3" (const_string "no")))]) =20 (define_insn "di3_fake" - [(set (match_operand:SI 0 "register_operand" "=3Dr,&r,&r") - (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0") - (match_operand:DI 2 "register_operand" "r,r,r")))] + [(set (match_operand:DI 0 "register_operand" "=3Dr,&r,&r") + (sign_extend:DI + (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0") + (match_operand:DI 2 "register_operand" "r,r,r"))))] "" { return loongarch_output_division (".w\t%0,%1,%2", operands); diff --git a/gcc/testsuite/gcc.target/loongarch/div-4.c b/gcc/testsuite/gcc= .target/loongarch/div-4.c new file mode 100644 index 00000000000..a52f87d6caf --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/div-4.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "slli" } } */ + +int +div(int a, int b) +{ + return a / b; +} --=20 2.37.0