Re: [PATCH v5 2/3] RISC-V: Add crypto machine descriptions

[Jeff Law <jeffreyalaw@gmail.com>]

On 12/20/23 20:50, juzhe.zhong@rivai.ai wrote:
> +       (and:VI
> +         (match_operand:VI 3 "register_operand"         "vr, vr, vr, vr")
> +         (not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr")))
> 
> This order should be swapped like ARM SVE:
> 
> (define_expand "@cond_bic<mode>"
>    [(set (match_operand:SVE_FULL_I 0 "register_operand")
>    (unspec:SVE_FULL_I
>      [(match_operand:<VPRED> 1 "register_operand")
>       (and:SVE_FULL_I
>         (not:SVE_FULL_I (match_operand:SVE_FULL_I 3 "register_operand"))
>         (match_operand:SVE_FULL_I 2 "register_operand"))
>       (match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero")]
>      UNSPEC_SEL))]
> "TARGET_SVE"
> )

Correct.  This case is even noted in the internals manual ;-)

> A machine that has an instruction that performs a bitwise logical-and of one
> operand with the bitwise negation of the other should specify the pattern
> for that instruction as
> 
> @smallexample
> (define_insn ""
>   [(set (match_operand:@var{m} 0 @dots{})
>         (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
>                      (match_operand:@var{m} 2 @dots{})))]
>   "@dots{}"
>   "@dots{}")
> @end smallexample


Jeff