From: Jeff Law <jeffreyalaw@gmail.com>
To: YunQiang Su <yunqiang.su@cipunited.com>, gcc-patches@gcc.gnu.org
Cc: macro@orcam.me.uk
Subject: Re: [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU
Date: Fri, 11 Feb 2022 20:54:16 -0700 [thread overview]
Message-ID: <5028ca31-8f20-f26b-13cc-8b3ea6b7ffb8@gmail.com> (raw)
In-Reply-To: <20220209031837.3167330-1-yunqiang.su@cipunited.com>
On 2/8/2022 8:18 PM, YunQiang Su wrote:
> If MIPS MCU extension is enable, the IPL section in Cause register
> has been expand to 8bit instead of 6bit.
>
> gcc/ChangeLog:
>
> * config/mips/mips.cc (mips_expand_prologue):
> IPL is 8bit for MCU ASE.
OK
jeff
next prev parent reply other threads:[~2022-02-12 3:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-26 3:29 [PATCH] MIPS: use 8bit for IPL in Cause register YunQiang Su
2022-01-26 18:40 ` Maciej W. Rozycki
2022-02-09 3:18 ` [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU YunQiang Su
2022-02-12 3:54 ` Jeff Law [this message]
2022-02-12 8:47 ` Maciej W. Rozycki
2022-03-15 7:00 ` YunQiang Su
2022-03-15 6:51 ` [PATCH v3] MIPS: IPL is 8bit in Cause and Status registers " YunQiang Su
2022-04-10 17:41 ` Maciej W. Rozycki
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