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Date: Fri, 9 Jul 2021 09:30:50 +0800
From: ALO <rjiejie@linux.alibaba.com>
To: gcc-patches@gcc.gnu.org, Jim Wilson <jimw@sifive.com>, Kito Cheng
 <kito.cheng@gmail.com>
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References: <20210629081107.28391-1-rjiejie@linux.alibaba.com>
Subject: Re: [PATCH 0/2] RISC-V: Add ldr/str instruction for T-HEAD.
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Hi,
	Ping.

=E2=80=94 Jojo
=E5=9C=A8 2021=E5=B9=B46=E6=9C=8829=E6=97=A5 +0800 PM4:11=EF=BC=8CJojo R =
<rjiejie=40linux.alibaba.com>=EF=BC=8C=E5=86=99=E9=81=93=EF=BC=9A
> T-HEAD extends some customized ISAs for Cores.
> The patches support ldr/str insns, it likes arm's LDR insn, the
> memory model is a base register indexed by (optionally scaled) register=
.