[PATCH] [5/10] AArch64 Port

[PATCH] [5/10] AArch64 Port

[Marcus Shawcroft]

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This patch contains all of the new files added to the test suite for
AArch64, the patch does not modify any existing file.

Proposed ChangeLog:

         * gcc.target/aarch64/aapcs/aapcs64.exp: New file.
         * gcc.target/aarch64/aapcs/abitest-2.h: New file.
         * gcc.target/aarch64/aapcs/abitest-common.h: New file.
         * gcc.target/aarch64/aapcs/abitest.S: New file.
         * gcc.target/aarch64/aapcs/abitest.h: New file.
         * gcc.target/aarch64/aapcs/func-ret-1.c: New file.
         * gcc.target/aarch64/aapcs/func-ret-2.c: New file.
         * gcc.target/aarch64/aapcs/func-ret-3.c: New file.
         * gcc.target/aarch64/aapcs/func-ret-3.x: New file.
         * gcc.target/aarch64/aapcs/func-ret-4.c: New file.
         * gcc.target/aarch64/aapcs/func-ret-4.x: New file.
         * gcc.target/aarch64/aapcs/ice_1.c: New file.
         * gcc.target/aarch64/aapcs/ice_2.c: New file.
         * gcc.target/aarch64/aapcs/ice_3.c: New file.
         * gcc.target/aarch64/aapcs/ice_4.c: New file.
         * gcc.target/aarch64/aapcs/ice_5.c: New file.
         * gcc.target/aarch64/aapcs/macro-def.h: New file.
         * gcc.target/aarch64/aapcs/test_1.c: New file.
         * gcc.target/aarch64/aapcs/test_10.c: New file.
         * gcc.target/aarch64/aapcs/test_11.c: New file.
         * gcc.target/aarch64/aapcs/test_12.c: New file.
         * gcc.target/aarch64/aapcs/test_13.c: New file.
         * gcc.target/aarch64/aapcs/test_14.c: New file.
         * gcc.target/aarch64/aapcs/test_15.c: New file.
         * gcc.target/aarch64/aapcs/test_16.c: New file.
         * gcc.target/aarch64/aapcs/test_17.c: New file.
         * gcc.target/aarch64/aapcs/test_18.c: New file.
         * gcc.target/aarch64/aapcs/test_19.c: New file.
         * gcc.target/aarch64/aapcs/test_2.c: New file.
         * gcc.target/aarch64/aapcs/test_20.c: New file.
         * gcc.target/aarch64/aapcs/test_21.c: New file.
         * gcc.target/aarch64/aapcs/test_22.c: New file.
         * gcc.target/aarch64/aapcs/test_23.c: New file.
         * gcc.target/aarch64/aapcs/test_24.c: New file.
         * gcc.target/aarch64/aapcs/test_25.c: New file.
         * gcc.target/aarch64/aapcs/test_26.c: New file.
         * gcc.target/aarch64/aapcs/test_3.c: New file.
         * gcc.target/aarch64/aapcs/test_4.c: New file.
         * gcc.target/aarch64/aapcs/test_5.c: New file.
         * gcc.target/aarch64/aapcs/test_6.c: New file.
         * gcc.target/aarch64/aapcs/test_7.c: New file.
         * gcc.target/aarch64/aapcs/test_8.c: New file.
         * gcc.target/aarch64/aapcs/test_9.c: New file.
         * gcc.target/aarch64/aapcs/test_align-1.c: New file.
         * gcc.target/aarch64/aapcs/test_align-2.c: New file.
         * gcc.target/aarch64/aapcs/test_align-3.c: New file.
         * gcc.target/aarch64/aapcs/test_align-4.c: New file.
         * gcc.target/aarch64/aapcs/test_complex.c: New file.
         * gcc.target/aarch64/aapcs/test_int128.c: New file.
         * gcc.target/aarch64/aapcs/test_quad_double.c: New file.
         * gcc.target/aarch64/aapcs/type-def.h: New file.
         * gcc.target/aarch64/aapcs/va_arg-1.c: New file.
         * gcc.target/aarch64/aapcs/va_arg-10.c: New file.
         * gcc.target/aarch64/aapcs/va_arg-11.c: New file.
         * gcc.target/aarch64/aapcs/va_arg-12.c: New file.
         * gcc.target/aarch64/aapcs/va_arg-2.c: New file.
         * gcc.target/aarch64/aapcs/va_arg-3.c: New file.
         * gcc.target/aarch64/aapcs/va_arg-4.c: New file.
         * gcc.target/aarch64/aapcs/va_arg-5.c: New file.
         * gcc.target/aarch64/aapcs/va_arg-6.c: New file.
         * gcc.target/aarch64/aapcs/va_arg-7.c: New file.
         * gcc.target/aarch64/aapcs/va_arg-8.c: New file.
         * gcc.target/aarch64/aapcs/va_arg-9.c: New file.
         * gcc.target/aarch64/aapcs/validate_memory.h: New file.
         * gcc.target/aarch64/aarch64.exp: New file.
         * gcc.target/aarch64/adc-1.c: New file.
         * gcc.target/aarch64/adc-2.c: New file.
         * gcc.target/aarch64/asm-1.c: New file.
         * gcc.target/aarch64/clrsb.c: New file.
         * gcc.target/aarch64/clz.c: New file.
         * gcc.target/aarch64/ctz.c: New file.
         * gcc.target/aarch64/csinc-1.c: New file.
         * gcc.target/aarch64/csinv-1.c: New file.
         * gcc.target/aarch64/csneg-1.c: New file.
         * gcc.target/aarch64/extend.c: New file.
         * gcc.target/aarch64/fcvt.x: New file.
         * gcc.target/aarch64/fcvt_double_int.c: New file.
         * gcc.target/aarch64/fcvt_double_long.c: New file.
         * gcc.target/aarch64/fcvt_double_uint.c: New file.
         * gcc.target/aarch64/fcvt_double_ulong.c: New file.
         * gcc.target/aarch64/fcvt_float_int.c: New file.
         * gcc.target/aarch64/fcvt_float_long.c: New file.
         * gcc.target/aarch64/fcvt_float_uint.c: New file.
         * gcc.target/aarch64/fcvt_float_ulong.c: New file.
         * gcc.target/aarch64/ffs.c: New file.
         * gcc.target/aarch64/fmadd.c: New file.
         * gcc.target/aarch64/fnmadd-fastmath.c: New file.
         * gcc.target/aarch64/frint.x: New file.
         * gcc.target/aarch64/frint_double.c: New file.
         * gcc.target/aarch64/frint_float.c: New file.
         * gcc.target/aarch64/index.c: New file.
         * gcc.target/aarch64/mneg-1.c: New file.
         * gcc.target/aarch64/mneg-2.c: New file.
         * gcc.target/aarch64/mneg-3.c: New file.
         * gcc.target/aarch64/mnegl-1.c: New file.
         * gcc.target/aarch64/mnegl-2.c: New file.
         * gcc.target/aarch64/narrow_high-intrinsics.c: New file.
         * gcc.target/aarch64/pic-constantpool1.c: New file.
         * gcc.target/aarch64/pic-symrefplus.c: New file.
         * gcc.target/aarch64/predefine_large.c: New file.
         * gcc.target/aarch64/predefine_small.c: New file.
         * gcc.target/aarch64/predefine_tiny.c: New file.
         * gcc.target/aarch64/reload-valid-spoff.c: New file.
         * gcc.target/aarch64/scalar_intrinsics.c: New file.
         * gcc.target/aarch64/table-intrinsics.c: New file.
         * gcc.target/aarch64/tst-1.c: New file.
         * gcc.target/aarch64/vect-abs-compile.c: New file.
         * gcc.target/aarch64/vect-abs.c: New file.
         * gcc.target/aarch64/vect-abs.x: New file.
         * gcc.target/aarch64/vect-compile.c: New file.
         * gcc.target/aarch64/vect-faddv-compile.c: New file.
         * gcc.target/aarch64/vect-faddv.c: New file.
         * gcc.target/aarch64/vect-faddv.x: New file.
         * gcc.target/aarch64/vect-fmax-fmin-compile.c: New file.
         * gcc.target/aarch64/vect-fmax-fmin.c: New file.
         * gcc.target/aarch64/vect-fmax-fmin.x: New file.
         * gcc.target/aarch64/vect-fmaxv-fminv-compile.c: New file.
         * gcc.target/aarch64/vect-fmaxv-fminv.x: New file.
         * gcc.target/aarch64/vect-fp-compile.c: New file.
         * gcc.target/aarch64/vect-fp.c: New file.
         * gcc.target/aarch64/vect-fp.x: New file.
         * gcc.target/aarch64/vect-mull-compile.c: New file.
         * gcc.target/aarch64/vect-mull.c: New file.
         * gcc.target/aarch64/vect-mull.x: New file.
         * gcc.target/aarch64/vect.c: New file.
         * gcc.target/aarch64/vect.x: New file.
         * gcc.target/aarch64/vector_intrinsics.c: New file.
         * gcc.target/aarch64/vfp-1.c: New file.
         * gcc.target/aarch64/volatile-bitfields-1.c: New file.
         * gcc.target/aarch64/volatile-bitfields-2.c: New file.
         * gcc.target/aarch64/volatile-bitfields-3.c: New file.
         * g++.dg/abi/aarch64_guard1.C: New file.

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[PATCH] [2/10] AArch64 Port

[Marcus Shawcroft]

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This patch contains the additions to the gcc/doc files to document
the AArch64 port.

Proposed ChangeLog:

          * doc/invoke.texi (AArch64 Options): New.
          * doc/md.texi (Machine Constraints): Add AArch64.

[-- Attachment #2: xx-gcc-doc-patch.txt --]
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diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index a9a79343985bdc6bcd070453446a40e996199612..cb5de9e1993eabef512cbbcbe79de6588c6b666a 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -467,6 +467,15 @@ Objective-C and Objective-C++ Dialects}.
 @c Try and put the significant identifier (CPU or system) first,
 @c so users have a clue at guessing where the ones they want will be.
 
+@emph{AArch64 Options}
+@gccoptlist{-mbig-endian  -mlittle-endian @gol
+-mgeneral-regs-only @gol
+-mcmodel=tiny  -mcmodel=small  -mcmodel=large @gol
+-mstrict-align @gol
+-momit-leaf-frame-pointer  -mno-omit-leaf-frame-pointer @gol
+-mtls-dialect=desc  -mtls-dialect=traditional @gol
+-march=@var{name}  -mcpu=@var{name}  -mtune=@var{name}}
+
 @emph{Adapteva Epiphany Options}
 @gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol
 -mbranch-cost=@var{num} -mcmove -mnops=@var{num} -msoft-cmpsf @gol
@@ -10611,6 +10620,7 @@ platform.
 @c in Machine Dependent Options
 
 @menu
+* AArch64 Options::
 * Adapteva Epiphany Options::
 * ARM Options::
 * AVR Options::
@@ -10820,6 +10830,125 @@ purpose.  The default is @option{-m1reg-
 
 @end table
 
+@node AArch64 Options
+@subsection AArch64 Options
+@cindex AArch64 Options
+
+These options are defined for AArch64 implementations:
+
+@table @gcctabopt
+
+@item -mbig-endian
+@opindex mbig-endian
+Generate big-endian code.  This is the default when GCC is configured for an
+@samp{aarch64_be-*-*} target.
+
+@item -mgeneral-regs-only
+@opindex mgeneral-regs-only
+Generate code which uses only the general registers.
+
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate little-endian code.  This is the default when GCC is configured for an
+@samp{aarch64-*-*} but not an @samp{aarch64_be-*-*} target.
+
+@item -mcmodel=tiny
+@opindex mcmodel=tiny
+Generate code for the tiny code model.  The program and its statically defined
+symbols must be within 1GB of each other.  Pointers are 64 bits.  Programs can
+be statically or dynamically linked.  This model is not fully implemented and
+mostly treated as "small".
+
+@item -mcmodel=small
+@opindex mcmodel=small
+Generate code for the small code model.  The program and its statically defined
+symbols must be within 4GB of each other.  Pointers are 64 bits.  Programs can
+be statically or dynamically linked.  This is the default code model.
+
+@item -mcmodel=large
+@opindex mcmodel=large
+Generate code for the large code model.  This makes no assumptions about
+addresses and sizes of sections.  Pointers are 64 bits.  Programs can be
+statically linked only.
+
+@item -mstrict-align
+@opindex mstrict-align
+Do not assume that unaligned memory references will be handled by the system.
+
+@item -momit-leaf-frame-pointer
+@item -mno-omit-leaf-frame-pointer
+@opindex momit-leaf-frame-pointer
+@opindex mno-omit-leaf-frame-pointer
+Omit or keep the frame pointer in leaf functions.  The former behaviour is the
+default.
+
+@item -mtls-dialect=desc
+@opindex mtls-dialect=desc
+Use TLS descriptors as the thread-local storage mechanism for dynamic accesses
+of TLS variables.  This is the default.
+
+@item -mtls-dialect=traditional
+@opindex mtls-dialect=traditional
+Use traditional TLS as the thread-local storage mechanism for dynamic accesses
+of TLS variables.
+
+@item -march=@var{name}
+@opindex march
+Specify the name of the target architecture, optionally suffixed by one or
+more feature modifiers.  This option has the form
+@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the
+only value for @var{arch} is @samp{armv8-a}.  The possible values for
+@var{feature} are documented in the sub-section below.
+
+Where conflicting feature modifiers are specified, the right-most feature is
+used.
+
+GCC uses this name to determine what kind of instructions it can emit when
+generating assembly code.  This option can be used in conjunction with or
+instead of the @option{-mcpu=} option.
+
+@item -mcpu=@var{name}
+@opindex mcpu
+Specify the name of the target processor, optionally suffixed by one or more
+feature modifiers.  This option has the form
+@option{-mcpu=@var{cpu}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the
+possible values for @var{cpu} are @samp{generic}, @samp{large}.  The
+possible values for @var{feature} are documented in the sub-section
+below.
+
+Where conflicting feature modifiers are specified, the right-most feature is
+used.
+
+GCC uses this name to determine what kind of instructions it can emit when
+generating assembly code.
+
+@item -mtune=@var{name}
+@opindex mtune
+Specify the name of the processor to tune the performance for.  The code will
+be tuned as if the target processor were of the type specified in this option,
+but still using instructions compatible with the target processor specified
+by a @option{-mcpu=} option.  This option cannot be suffixed by feature
+modifiers.
+
+@end table
+
+@subsubsection @option{-march} and @option{-mcpu} feature modifiers
+@cindex @option{-march} feature modifiers
+@cindex @option{-mcpu} feature modifiers
+Feature modifiers used with @option{-march} and @option{-mcpu} can be one
+the following:
+
+@table @samp
+@item crypto
+Enable Crypto extension.  This implies Advanced SIMD is enabled.
+@item fp
+Enable floating-point instructions.
+@item simd
+Enable Advanced SIMD instructions.  This implies floating-point instructions
+are enabled.  This is the default for all current possible values for options
+@option{-march} and @option{-mcpu=}.
+@end table
+
 @node ARM Options
 @subsection ARM Options
 @cindex ARM options
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index f17d55e292c81836a364e303a115aa376e24b756..02ee623a1b7cfa7dedc83eb9da677373d47cdb3e 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -1653,6 +1653,66 @@ table heading for each architecture is t
 the meanings of that architecture's constraints.
 
 @table @emph
+@item AArch64 family---@file{config/aarch64/constraints.md}
+@table @code
+@item k
+The stack pointer register (@code{SP})
+
+@item w
+Floating point or SIMD vector register
+
+@item I
+Integer constant that is valid as an immediate operand in an @code{ADD}
+instruction
+
+@item J
+Integer constant that is valid as an immediate operand in a @code{SUB}
+instruction (once negated)
+
+@item K
+Integer constant that can be used with a 32-bit logical instruction
+
+@item L
+Integer constant that can be used with a 64-bit logical instruction
+
+@item M
+Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
+pseudo instruction. The @code{MOV} may be assembled to one of several different
+machine instructions depending on the value
+
+@item N
+Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
+pseudo instruction
+
+@item S
+An absolute symbolic address or a label reference
+
+@item Y
+Floating point constant zero
+
+@item Z
+Integer constant zero
+
+@item Usa
+An absolute symbolic address
+
+@item Ush
+The high part (bits 12 and upwards) of the pc-relative address of a symbol
+within 4GB of the instruction
+
+@item Q
+A memory address which uses a single base register with no offset
+
+@item Ump
+A memory address suitable for a load/store pair instruction in SI, DI, SF and
+DF modes
+
+@item Utf
+A memory address suitable for a load/store pair instruction in TF mode
+
+@end table
+
+
 @item ARM family---@file{config/arm/constraints.md}
 @table @code
 @item w

[PATCH] [1/10] AArch64 Port

[Marcus Shawcroft]

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This patch contains the adjustments to top level gcc configury required 
to enable the AArch64 port.

Proposed ChangeLog:

          * config.gcc: Add AArch64.
          * configure.ac: Add AArch64 TLS support detection.
          * configure: Regenerate.

[-- Attachment #2: xx-gcc-configury-patch.txt --]
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diff --git a/gcc/config.gcc b/gcc/config.gcc
index ed7474ad68c4ae7234072d508b697a9a2218d18d..75ca21756ebca80479d69c38ff8d3c4142d822f3 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -310,6 +310,13 @@ m32c*-*-*)
 	tmake_file=m32c/t-m32c
 	target_has_targetm_common=no
         ;;
+aarch64*-*-*)
+	cpu_type=aarch64
+	need_64bit_hwint=yes
+	extra_headers="arm_neon.h"
+	extra_objs="aarch64-builtins.o"
+	target_has_targetm_common=yes
+	;;
 alpha*-*-*)
 	cpu_type=alpha
 	need_64bit_hwint=yes
@@ -796,6 +803,27 @@ case ${target} in
 esac
 
 case ${target} in
+aarch64*-*-elf)
+	tm_file="${tm_file} dbxelf.h elfos.h newlib-stdint.h"
+	tm_file="${tm_file} aarch64/aarch64-elf.h aarch64/aarch64-elf-raw.h"
+	tmake_file="${tmake_file} aarch64/t-aarch64"
+	use_gcc_stdint=wrap
+	case $target in
+	aarch64_be-*)
+		tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
+		;;
+	esac
+	;;
+aarch64*-*-linux*)
+	tm_file="${tm_file} dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h"
+	tm_file="${tm_file} aarch64/aarch64-elf.h aarch64/aarch64-linux.h"
+	tmake_file="${tmake_file} aarch64/t-aarch64 aarch64/t-aarch64-linux"
+	case $target in
+	aarch64_be-*)
+		tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
+		;;
+	esac
+	;;
 alpha*-*-linux*)
 	tm_file="elfos.h ${tm_file} alpha/elf.h alpha/linux.h alpha/linux-elf.h glibc-stdint.h"
 	extra_options="${extra_options} alpha/elf.opt"
@@ -2995,6 +3023,92 @@ fi
 
 supported_defaults=
 case "${target}" in
+	aarch64*-*-*)
+		supported_defaults="cpu arch"
+		for which in cpu arch; do
+
+			eval "val=\$with_$which"
+			base_val=`echo $val | sed -e 's/\+.*//'`
+			ext_val=`echo $val | sed -e 's/[a-z0-9\-]\+//'`
+
+			if [ $which = arch ]; then
+			  def=aarch64-arches.def
+			  pattern=AARCH64_ARCH
+			else
+			  def=aarch64-cores.def
+			  pattern=AARCH64_CORE
+			fi
+
+			ext_mask=AARCH64_CPU_DEFAULT_FLAGS
+
+			# Find the base CPU or ARCH id in aarch64-cores.def or
+			# aarch64-arches.def
+			if [ x"$base_val" = x ] \
+			    || grep "^$pattern(\"$base_val\"," \
+				    ${srcdir}/config/aarch64/$def \
+				    > /dev/null; then
+
+			  if [ $which = arch ]; then
+				base_id=`grep "^$pattern(\"$base_val\"," \
+				  ${srcdir}/config/aarch64/$def | \
+				  sed -e 's/^[^,]*,[ 	]*//' | \
+				  sed -e 's/,.*$//'`
+			  else
+				base_id=`grep "^$pattern(\"$base_val\"," \
+				  ${srcdir}/config/aarch64/$def | \
+				  sed -e 's/^[^,]*,[ 	]*//' | \
+				  sed -e 's/,.*$//'`
+			  fi
+
+			  while [ x"$ext_val" != x ]
+			  do
+				ext_val=`echo $ext_val | sed -e 's/\+//'`
+				ext=`echo $ext_val | sed -e 's/\+.*//'`
+				base_ext=`echo $ext | sed -e 's/^no//'`
+
+				if [ x"$base_ext" = x ] \
+				    || grep "^AARCH64_OPT_EXTENSION(\"$base_ext\"," \
+				    ${srcdir}/config/aarch64/aarch64-option-extensions.def \
+				    > /dev/null; then
+
+				  ext_on=`grep "^AARCH64_OPT_EXTENSION(\"$base_ext\"," \
+					${srcdir}/config/aarch64/aarch64-option-extensions.def | \
+					sed -e 's/^[^,]*,[ 	]*//' | \
+					sed -e 's/,.*$//'`
+				  ext_off=`grep "^AARCH64_OPT_EXTENSION(\"$base_ext\"," \
+					${srcdir}/config/aarch64/aarch64-option-extensions.def | \
+					sed -e 's/^[^,]*,[ 	]*[^,]*,[ 	]*//' | \
+					sed -e 's/,.*$//' | \
+					sed -e 's/).*$//'`
+
+				  if [ $ext = $base_ext ]; then
+					# Adding extension
+					ext_mask="("$ext_mask") | ("$ext_on")"
+				  else
+					# Removing extension
+					ext_mask="("$ext_mask") & ~("$ext_off")"
+				  fi
+
+				  true
+				else
+				  echo "Unknown extension used in --with-$which=$val" 1>&2
+				  exit 1
+				fi
+				ext_val=`echo $ext_val | sed -e 's/[a-z0-9]\+//'`
+			  done
+
+			  ext_mask="(("$ext_mask") << 6)"
+			  if [ x"$base_id" != x ]; then
+				target_cpu_cname="TARGET_CPU_$base_id | $ext_mask"
+			  fi
+			  true
+			else
+			  echo "Unknown $which used in --with-$which=$val" 1>&2
+			  exit 1
+			fi
+		done
+		;;
+
 	alpha*-*-*)
 		supported_defaults="cpu tune"
 		for which in cpu tune; do
@@ -3476,6 +3590,15 @@ esac
 # Set some miscellaneous flags for particular targets.
 target_cpu_default2=
 case ${target} in
+	aarch64*-*-*)
+		if test x$target_cpu_cname = x
+		then
+			target_cpu_default2=TARGET_CPU_generic
+		else
+			target_cpu_default2=$target_cpu_cname
+		fi
+		;;
+
 	arm*-*-*)
 		if test x$target_cpu_cname = x
 		then
diff --git a/gcc/configure b/gcc/configure
index 387de5b743cb2b44afb1206ef6a8689ab1fcbbfa..bef4ea36af785578d111ff702acf615aa556b49c 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -23189,6 +23189,19 @@ foo:
 	tls_first_minor=19
 	tls_as_opt='--fatal-warnings'
 	;;
+  aarch64*-*-*)
+    conftest_s='
+	.section ".tdata","awT",%progbits
+foo:	.long	25
+	.text
+	adrp  x0, :tlsgd:x
+	add   x0, x0, #:tlsgd_lo12:x
+        bl    __tls_get_addr
+	nop'
+	tls_first_major=2
+	tls_first_minor=20
+	tls_as_opt='--fatal-warnings'
+	;;
   powerpc-*-*)
     conftest_s='
 	.section ".tdata","awT",@progbits
diff --git a/gcc/configure.ac b/gcc/configure.ac
index b6c049b022bd85ddf2e42a55f98d57a50ce2775c..dee70dc2061a56a02b5d62954ac75bbfa52a72d8 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -2965,6 +2965,19 @@ foo:
 	tls_first_minor=19
 	tls_as_opt='--fatal-warnings'
 	;;
+  aarch64*-*-*)
+    conftest_s='
+	.section ".tdata","awT",%progbits
+foo:	.long	25
+	.text
+	adrp  x0, :tlsgd:x
+	add   x0, x0, #:tlsgd_lo12:x
+        bl    __tls_get_addr
+	nop'
+	tls_first_major=2
+	tls_first_minor=20
+	tls_as_opt='--fatal-warnings'
+	;;
   powerpc-*-*)
     conftest_s='
 	.section ".tdata","awT",@progbits

[PATCH] [9/10] AArch64 Port

[Marcus Shawcroft]

[-- Attachment #1: Type: text/plain, Size: 118 bytes --]

This patch adjusts the libgomp configury for AArch64.

Proposed ChangeLog:

         * configure.tgt: Add AArch64.

[-- Attachment #2: xx-libgomp-patch.txt --]
[-- Type: text/plain, Size: 455 bytes --]

diff --git a/libgomp/configure.tgt b/libgomp/configure.tgt
index d5a1480e4812634ae280238684cb2187b2c618f8..2eecc93a349f3afe9e0afbbc2e98194065873498 100644
--- a/libgomp/configure.tgt
+++ b/libgomp/configure.tgt
@@ -27,6 +27,10 @@ config_path="posix"
 if test $enable_linux_futex = yes; then
   case "${target}" in
 
+    aarch64*-*-linux*)
+	config_path="linux posix"
+	;;
+
     alpha*-*-linux*)
 	config_path="linux/alpha linux posix"
 	;;

[PATCH] [7/10] AArch64 Port

[Marcus Shawcroft]

[-- Attachment #1: Type: text/plain, Size: 154 bytes --]

This patch adjusts the libcpp configury for AArch64.

Proposed ChangeLog:

         * configure.ac: Enable AArch64.
         * configure: Regenerate.

[-- Attachment #2: xx-libcpp-patch.txt --]
[-- Type: text/plain, Size: 685 bytes --]

diff --git a/libcpp/configure.ac b/libcpp/configure.ac
index 29bd8c5e6f1a7bddb628f415f3138dfeaa69a483..e62da06ce278f832084ff2080d694c99e24f8532 100644
--- a/libcpp/configure.ac
+++ b/libcpp/configure.ac
@@ -134,6 +134,7 @@ fi
 
 m4_changequote(,)
 case $target in
+	aarch64*-*-* | \
 	alpha*-*-* | \
 	arm*-*-*eabi* | \
 	arm*-*-symbianelf* | \
diff --git a/libcpp/configure b/libcpp/configure
index 01e4462307f7ae6aa1b563133746fb45e41af74e..d33969b2b2d5f692ed39a78abd8a94c0385d071e 100755
--- a/libcpp/configure
+++ b/libcpp/configure
@@ -7096,6 +7096,7 @@ fi
 
 
 case $target in
+	aarch64*-*-* | \
 	alpha*-*-* | \
 	arm*-*-*eabi* | \
 	arm*-*-symbianelf* | \

[PATCH] [4/10] AArch64 Port

[Marcus Shawcroft]

[-- Attachment #1: Type: text/plain, Size: 1692 bytes --]

This patch contains the adjustments to the existing test suite to
support AArch64.

Proposed ChangeLog:

          * lib/target-supports.exp
          (check_profiling_available): Add AArch64.
          (check_effective_target_vect_int): Likewise.
          (check_effective_target_vect_shift): Likewise.
          (check_effective_target_vect_float): Likewise.
          (check_effective_target_vect_double): Likewise.
          (check_effective_target_vect_widen_mult_qi_to_hi): Likewise.
          (check_effective_target_vect_widen_mult_hi_to_si): Likewise.
          (check_effective_target_vect_pack_trunc): Likewise.
          (check_effective_target_vect_unpack): Likewise.
          (check_effective_target_vect_hw_misalign): Likewise.
          (check_effective_target_vect_short_mult): Likewise.
          (check_effective_target_vect_int_mult): Likewise.
          (check_effective_target_vect_stridedN): Likewise.
          (check_effective_target_sync_int_long): Likewise.
          (check_effective_target_sync_char_short): Likewise.
          (check_vect_support_and_set_flags): Likewise.
          (check_effective_target_aarch64_tiny): New.
          (check_effective_target_aarch64_small): New.
          (check_effective_target_aarch64_large): New.
          * g++.dg/other/PR23205.C: Enable aarch64.
          * g++.dg/other/pr23205-2.C: Likewise.
          * g++.old-deja/g++.abi/ptrmem.C: Likewise.
          * gcc.c-torture/execute/20101011-1.c: Likewise.
          * gcc.dg/20020312-2.c: Likewise.
          * gcc.dg/20040813-1.c: Likewise.
          * gcc.dg/builtin-apply2.c: Likewise.
          * gcc.dg/stack-usage-1.c: Likewise.

[-- Attachment #2: xx-gcc-testsuite-patch.txt --]
[-- Type: text/plain, Size: 6392 bytes --]

diff --git a/gcc/testsuite/g++.dg/abi/aarch64_guard1.C b/gcc/testsuite/g++.dg/abi/aarch64_guard1.C
index ...af82ad2ec36998135e67a25f47d19b4e977fd8d2 100644
--- a/gcc/testsuite/g++.dg/abi/aarch64_guard1.C
+++ b/gcc/testsuite/g++.dg/abi/aarch64_guard1.C
@@ -0,0 +1,17 @@
+// Check that the initialization guard variable is an 8-byte aligned,
+// 8-byte doubleword and that only the least significant bit is used
+// for initialization guard variables.
+// { dg-do compile { target aarch64*-*-* } }
+// { dg-options "-O -fdump-tree-original" }
+
+int bar();
+
+int *foo ()
+{
+  static int x = bar ();
+  return &x;
+}
+
+// { dg-final { scan-assembler _ZGVZ3foovE1x,8,8 } }
+// { dg-final { scan-tree-dump "_ZGVZ3foovE1x & 1" "original" } }
+// { dg-final { cleanup-tree-dump "original" } }
diff --git a/gcc/testsuite/g++.dg/other/PR23205.C b/gcc/testsuite/g++.dg/other/PR23205.C
index a31fc1d773ddf0b21bdb219be2646c574923d7a5..e55710b40f0a0a69528ca4e27facff742ff2e4ad 100644
--- a/gcc/testsuite/g++.dg/other/PR23205.C
+++ b/gcc/testsuite/g++.dg/other/PR23205.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-skip-if "No stabs" { mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* *-*-vxworks } { "*" } { "" } } */
+/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* *-*-vxworks } { "*" } { "" } } */
 /* { dg-options "-gstabs+ -fno-eliminate-unused-debug-types" } */
 
 const int foobar = 4;
diff --git a/gcc/testsuite/g++.dg/other/pr23205-2.C b/gcc/testsuite/g++.dg/other/pr23205-2.C
index fbd16dfab5836e4f0ceb987cbf42271d3728c63f..607e5a2b4e433a0fec79d3fda4dc265f1f8a39ae 100644
--- a/gcc/testsuite/g++.dg/other/pr23205-2.C
+++ b/gcc/testsuite/g++.dg/other/pr23205-2.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-skip-if "No stabs" { mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* } { "*" } { "" } } */
+/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* } { "*" } { "" } } */
 /* { dg-options "-gstabs+ -fno-eliminate-unused-debug-types -ftoplevel-reorder" } */
 
 const int foobar = 4;
diff --git a/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C b/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C
index 077fa50840c978f9c0dda8c0e7071eda514395b5..341735879c59d517edb1fc49edfb78c6e2e01846 100644
--- a/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C
+++ b/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C
@@ -7,7 +7,7 @@
    function.  However, some platforms use all bits to encode a
    function pointer.  Such platforms use the lowest bit of the delta,
    that is shifted left by one bit.  */
-#if defined __MN10300__ || defined __SH5__ || defined __arm__ || defined __thumb__ || defined __mips__
+#if defined __MN10300__ || defined __SH5__ || defined __arm__ || defined __thumb__ || defined __mips__ || defined __aarch64__
 #define ADJUST_PTRFN(func, virt) ((void (*)())(func))
 #define ADJUST_DELTA(delta, virt) (((delta) << 1) + !!(virt))
 #else
diff --git a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
index b98454e253ef074b6219a83f0f9473f9dbc0188d..76b9f068723994dd3f0543a9a4ece4538cb676de 100644
--- a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
+++ b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
@@ -12,6 +12,10 @@
 #elif defined (__sh__)
   /* On SH division by zero does not trap.  */
 # define DO_TEST 0
+#elif defined (__aarch64__) && !defined(__linux__)
+  /* AArch64 divisions do trap by default, but libgloss targets do not
+     intercept the trap and raise a SIGFPE. So restrict the test to
+     AArch64 systems that use the Linux kernel.  */
 #elif defined (__TMS320C6X__)
   /* On TI C6X division by zero does not trap.  */
 # define DO_TEST 0
diff --git a/gcc/testsuite/gcc.dg/20020312-2.c b/gcc/testsuite/gcc.dg/20020312-2.c
index 768e17e64cda63d12b75f3f40bbddffe4b1b1266..47c2d0fc64895d6ebd0691d49c28d981d29e1b10 100644
--- a/gcc/testsuite/gcc.dg/20020312-2.c
+++ b/gcc/testsuite/gcc.dg/20020312-2.c
@@ -92,6 +92,8 @@ extern void abort (void);
 # else
 #  define PIC_REG "gr17"
 #endif
+#elif defined (__aarch64__)
+/* No pic register -- yet.  */
 #else
 # error "Modify the test for your target."
 #endif
diff --git a/gcc/testsuite/gcc.dg/20040813-1.c b/gcc/testsuite/gcc.dg/20040813-1.c
index e16344164d59f5a09a7e083669132eaac4c54d7e..c1a9fd0409abf4fee7b47c632c6decb4c8fd6a45 100644
--- a/gcc/testsuite/gcc.dg/20040813-1.c
+++ b/gcc/testsuite/gcc.dg/20040813-1.c
@@ -2,7 +2,7 @@
 /* Contributed by Devang Patel  <dpatel@apple.com>  */
 
 /* { dg-do compile } */
-/* { dg-skip-if "No stabs" { mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* *-*-vxworks* } { "*" } { "" } } */
+/* { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* *-*-aix* alpha*-*-* hppa*64*-*-* ia64-*-* tile*-*-* *-*-vxworks* } { "*" } { "" } } */
 /* { dg-options "-gstabs" } */
 
 int
diff --git a/gcc/testsuite/gcc.dg/builtin-apply2.c b/gcc/testsuite/gcc.dg/builtin-apply2.c
index c5b841a849689648d32e11eb9a7530350bd1a57e..7061b1041ce371b742e746313b141a20d1f5491c 100644
--- a/gcc/testsuite/gcc.dg/builtin-apply2.c
+++ b/gcc/testsuite/gcc.dg/builtin-apply2.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { "avr-*-*" } { "*" } { "" } } */
+/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { "aarch64*-*-* avr-*-* " } { "*" } { "" } } */
 /* { dg-skip-if "Variadic funcs use Base AAPCS.  Normal funcs use VFP variant." { "arm*-*-*" } { "-mfloat-abi=hard" } { "" } } */
 
 /* PR target/12503 */
diff --git a/gcc/testsuite/gcc.dg/stack-usage-1.c b/gcc/testsuite/gcc.dg/stack-usage-1.c
index d5cf487979f1d655c645e902163cfe75ce5cc469..b6524f9a1255566d70eee6afcd206381867e88ed 100644
--- a/gcc/testsuite/gcc.dg/stack-usage-1.c
+++ b/gcc/testsuite/gcc.dg/stack-usage-1.c
@@ -7,7 +7,9 @@
    function FOO is reported as 256 or 264 in the stack usage (.su) file.
    Then check that this is the actual stack usage in the assembly file.  */
 
-#if defined(__i386__)
+#if defined(__aarch64__)
+#  define SIZE 256 /* No frame pointer for leaf functions (default) */
+#elif defined(__i386__)
 #  define SIZE 248
 #elif defined(__x86_64__)
 #  ifndef _WIN64

[PATCH] [10/10] AArch64 Port

[Marcus Shawcroft]

[-- Attachment #1: Type: text/plain, Size: 295 bytes --]

This patch provides the AArch64 libstdc++-v3 port, it contains both the
required configury adjustment to config.host and the new file introduced 
by the AArch64 port.

Proposed ChangeLog:

         * config/cpu/aarch64/cxxabi_tweaks.h: New file.
         * configure.host: Enable aarch64.

[-- Attachment #2: xx-libstdc-patch.txt --]
[-- Type: text/plain, Size: 2967 bytes --]

diff --git a/libstdc++-v3/configure.host b/libstdc++-v3/configure.host
index ed9e72109d41774c179190d9546b53d0dd4feef1..af5d3ffbff48eb82dd85ef55c290a3e5d2be9f89 100644
--- a/libstdc++-v3/configure.host
+++ b/libstdc++-v3/configure.host
@@ -99,6 +99,9 @@ error_constants_dir="os/generic"
 # variants into the established source config/cpu/* sub-directories.
 # THIS TABLE IS SORTED.  KEEP IT THAT WAY.
 case "${host_cpu}" in
+  aarch64*)
+    try_cpu=aarch64
+    ;;
   alpha*)
     try_cpu=alpha
     ;;
diff --git a/libstdc++-v3/config/cpu/aarch64/cxxabi_tweaks.h b/libstdc++-v3/config/cpu/aarch64/cxxabi_tweaks.h
index ...31a423f4fd56bffaead1d1f2b0057cdb80cda1fb 100644
--- a/libstdc++-v3/config/cpu/aarch64/cxxabi_tweaks.h
+++ b/libstdc++-v3/config/cpu/aarch64/cxxabi_tweaks.h
@@ -0,0 +1,60 @@
+// Control various target specific ABI tweaks.  AArch64 version.
+
+// Copyright (C) 2004, 2006, 2008, 2009, 2011, 2012
+// Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// Under Section 7 of GPL version 3, you are granted additional
+// permissions described in the GCC Runtime Library Exception, version
+// 3.1, as published by the Free Software Foundation.
+
+// You should have received a copy of the GNU General Public License and
+// a copy of the GCC Runtime Library Exception along with this program;
+// see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+// <http://www.gnu.org/licenses/>.
+
+/** @file cxxabi_tweaks.h
+ *  The header provides an CPU-variable interface to the C++ ABI.
+ */
+
+#ifndef _CXXABI_TWEAKS_H
+#define _CXXABI_TWEAKS_H 1
+
+#ifdef __cplusplus
+namespace __cxxabiv1
+{
+  extern "C"
+  {
+#endif
+
+  // The AArch64 ABI uses the least significant bit of a 64-bit
+  // guard variable.
+#define _GLIBCXX_GUARD_TEST(x) ((*(x) & 1) != 0)
+#define _GLIBCXX_GUARD_SET(x) *(x) = 1
+#define _GLIBCXX_GUARD_BIT 1
+#define _GLIBCXX_GUARD_PENDING_BIT __guard_test_bit (1, 1)
+#define _GLIBCXX_GUARD_WAITING_BIT __guard_test_bit (2, 1)
+  __extension__ typedef int __guard __attribute__((mode (__DI__)));
+
+  // __cxa_vec_ctor has void return type.
+  typedef void __cxa_vec_ctor_return_type;
+#define _GLIBCXX_CXA_VEC_CTOR_RETURN(x) return
+  // Constructors and destructors do not return a value.
+  typedef void __cxa_cdtor_return_type;
+
+#ifdef __cplusplus
+  }
+} // namespace __cxxabiv1
+#endif
+
+#endif

[PATCH] [8/10] AArch64 Port

[Marcus Shawcroft]

[-- Attachment #1: Type: text/plain, Size: 594 bytes --]

This patch provides the AArch64 libgcc port, it contains both the
required configury adjustment to config.host and the new files
introduced by the AArch64 port.

Proposed ChangeLog:

         * config.host (aarch64*-*-elf, aarch64*-*-linux*): New.
         * config/aarch64/crti.S: New file.
         * config/aarch64/crtn.S: New file.
         * config/aarch64/linux-unwind.h: New file.
         * config/aarch64/sfp-machine.h: New file.
         * config/aarch64/sync-cache.c: New file.
         * config/aarch64/t-aarch64: New file.
         * config/aarch64/t-softfp: New file.

[-- Attachment #2: xx-libgcc-patch.txt --]
[-- Type: text/plain, Size: 20135 bytes --]

diff --git a/libgcc/config.host b/libgcc/config.host
index 763f6c3a252223e149eb9b995679f455051bfe7a..96c93a4e6a04f63eb7ab629b822a55c19e6d5f97 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -83,6 +83,9 @@ m32c*-*-*)
         cpu_type=m32c
 	tmake_file=t-fdpbit
         ;;
+aarch64*-*-*)
+	cpu_type=aarch64
+	;;
 alpha*-*-*)
 	cpu_type=alpha
 	;;
@@ -278,6 +281,16 @@ i[34567]86-*-mingw* | x86_64-*-mingw*)
 esac
 
 case ${host} in
+aarch64*-*-elf)
+	extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
+	tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
+	tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp"
+	;;
+aarch64*-*-linux*)
+	md_unwind_header=aarch64/linux-unwind.h
+	tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
+	tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp"
+	;;
 alpha*-*-linux*)
 	tmake_file="${tmake_file} alpha/t-alpha alpha/t-ieee t-crtfm alpha/t-linux"
 	extra_parts="$extra_parts crtfastmath.o"
diff --git a/libgcc/config/aarch64/crti.S b/libgcc/config/aarch64/crti.S
index ...49611303b023206cd9cd72511e49fe4aadca340c 100644
--- a/libgcc/config/aarch64/crti.S
+++ b/libgcc/config/aarch64/crti.S
@@ -0,0 +1,68 @@
+# Machine description for AArch64 architecture.
+# Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+# Contributed by ARM Ltd.
+#
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 3, or (at your option) any
+# later version.
+#
+# This file is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
+#
+# Under Section 7 of GPL version 3, you are granted additional
+# permissions described in the GCC Runtime Library Exception, version
+# 3.1, as published by the Free Software Foundation.
+#
+# You should have received a copy of the GNU General Public License and
+# a copy of the GCC Runtime Library Exception along with this program;
+# see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+# <http://www.gnu.org/licenses/>.
+
+/* An executable stack is *not* required for these functions.  */
+#if defined(__ELF__) && defined(__linux__)
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
+# This file creates a stack frame for the contents of the .fini and
+# .init sections.  Users may put any desired instructions in those
+# sections.
+
+#ifdef __ELF__
+#define TYPE(x) .type x,function
+#else
+#define TYPE(x)
+#endif
+
+	# Note - this macro is complemented by the FUNC_END macro
+	# in crtn.S.  If you change this macro you must also change
+	# that macro match.
+.macro FUNC_START
+	#  Create a stack frame and save any call-preserved registers
+	stp	x29, x30, [sp, #-16]!
+	stp	x27, x28, [sp, #-16]!
+	stp	x25, x26, [sp, #-16]!
+	stp	x23, x24, [sp, #-16]!
+	stp	x21, x22, [sp, #-16]!
+	stp	x19, x20, [sp, #-16]!
+.endm
+
+	.section	".init"
+	.align 2
+	.global	_init
+	TYPE(_init)
+_init:
+	FUNC_START
+
+
+	.section	".fini"
+	.align	2
+	.global	_fini
+	TYPE(_fini)
+_fini:
+	FUNC_START
+
+# end of crti.S
diff --git a/libgcc/config/aarch64/crtn.S b/libgcc/config/aarch64/crtn.S
index ...70dbc19c59275ce591025de1fc4b39596628730b 100644
--- a/libgcc/config/aarch64/crtn.S
+++ b/libgcc/config/aarch64/crtn.S
@@ -0,0 +1,61 @@
+# Machine description for AArch64 architecture.
+# Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+# Contributed by ARM Ltd.
+#
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 3, or (at your option) any
+# later version.
+#
+# This file is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
+#
+# Under Section 7 of GPL version 3, you are granted additional
+# permissions described in the GCC Runtime Library Exception, version
+# 3.1, as published by the Free Software Foundation.
+#
+# You should have received a copy of the GNU General Public License and
+# a copy of the GCC Runtime Library Exception along with this program;
+# see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+# <http://www.gnu.org/licenses/>.
+
+/* An executable stack is *not* required for these functions.  */
+#if defined(__ELF__) && defined(__linux__)
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
+# This file just makes sure that the .fini and .init sections do in
+# fact return.  Users may put any desired instructions in those sections.
+# This file is the last thing linked into any executable.
+
+	# Note - this macro is complemented by the FUNC_START macro
+	# in crti.S.  If you change this macro you must also change
+	# that macro match.
+	#
+	# Note - we do not try any fancy optimizations of the return
+	# sequences here, it is just not worth it.  Instead keep things
+	# simple.  Restore all the save resgisters, including the link
+	# register and then perform the correct function return instruction.
+.macro FUNC_END
+	ldp	x19, x20, [sp], #16
+	ldp	x21, x22, [sp], #16
+	ldp	x23, x24, [sp], #16
+	ldp	x25, x26, [sp], #16
+	ldp	x27, x28, [sp], #16
+	ldp	x29, x30, [sp], #16
+	ret
+.endm
+
+
+	.section	".init"
+	;;
+	FUNC_END
+
+	.section	".fini"
+	;;
+	FUNC_END
+
+# end of crtn.S
diff --git a/libgcc/config/aarch64/linux-unwind.h b/libgcc/config/aarch64/linux-unwind.h
index ...1e2d40b7d98e306dc761db222e7f12a090ef8e5e 100644
--- a/libgcc/config/aarch64/linux-unwind.h
+++ b/libgcc/config/aarch64/linux-unwind.h
@@ -0,0 +1,143 @@
+/* Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 3, or (at your option) any
+   later version.
+
+   This file is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef inhibit_libc
+
+#include <signal.h>
+#include <sys/ucontext.h>
+
+#define MD_FALLBACK_FRAME_STATE_FOR aarch64_fallback_frame_state
+
+static _Unwind_Reason_Code
+aarch64_fallback_frame_state (struct _Unwind_Context *context,
+			      _Unwind_FrameState * fs)
+{
+  /* The kernel creates an rt_sigframe on the stack immediately prior
+     to delivering a signal.
+
+     This structure must have the same shape as the linux kernel
+     equivalent.  */
+  struct rt_sigframe
+  {
+    siginfo_t info;
+    struct ucontext uc;
+  };
+
+  struct rt_sigframe *rt_;
+  _Unwind_Ptr new_cfa;
+  unsigned *pc = context->ra;
+  struct sigcontext *sc;
+  struct _aarch64_ctx *extension_marker;
+  int i;
+
+  /* A signal frame will have a return address pointing to
+     __default_sa_restorer. This code is hardwired as:
+
+     0xd2801168         movz x8, #0x8b
+     0xd4000001         svc  0x0
+   */
+  if (pc[0] != 0xd2801168 || pc[1] != 0xd4000001)
+    {
+      return _URC_END_OF_STACK;
+    }
+
+  rt_ = context->cfa;
+  sc = &rt_->uc.uc_mcontext;
+
+/* This define duplicates the definition in aarch64.md */
+#define SP_REGNUM 31
+
+  new_cfa = (_Unwind_Ptr) sc;
+  fs->regs.cfa_how = CFA_REG_OFFSET;
+  fs->regs.cfa_reg = STACK_POINTER_REGNUM;
+  fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa;
+
+  for (i = 0; i < AARCH64_DWARF_NUMBER_R; i++)
+    {
+      fs->regs.reg[AARCH64_DWARF_R0 + i].how = REG_SAVED_OFFSET;
+      fs->regs.reg[AARCH64_DWARF_R0 + i].loc.offset =
+	(_Unwind_Ptr) & (sc->regs[i]) - new_cfa;
+    }
+
+  /* The core context may be extended with an arbitrary set of
+     additional contexts appended sequentially. Each additional
+     context contains a magic identifier and size in bytes.  The size
+     field can be used to skip over unrecognized context extensions.
+     The end of the context sequence is marked by a context with magic
+     0 or size 0.  */
+  for (extension_marker = (struct _aarch64_ctx *) &sc->__reserved;
+       extension_marker->magic;
+       extension_marker = (struct _aarch64_ctx *)
+       ((unsigned char *) extension_marker + extension_marker->size))
+    {
+      if (extension_marker->magic == FPSIMD_MAGIC)
+	{
+	  struct fpsimd_context *ctx =
+	    (struct fpsimd_context *) extension_marker;
+	  int i;
+
+	  for (i = 0; i < AARCH64_DWARF_NUMBER_V; i++)
+	    {
+	      _Unwind_Sword offset;
+
+	      fs->regs.reg[AARCH64_DWARF_V0 + i].how = REG_SAVED_OFFSET;
+
+	      /* sigcontext contains 32 128bit registers for V0 to
+		 V31.  The kernel will have saved the contents of the
+		 V registers.  We want to unwind the callee save D
+		 registers.  Each D register comprises the least
+		 significant half of the corresponding V register.  We
+		 need to offset into the saved V register dependent on
+		 our endianness to find the saved D register.  */
+
+	      offset = (_Unwind_Ptr) & (ctx->vregs[i]) - new_cfa;
+
+	      /* The endianness adjustment code below expects that a
+		 saved V register is 16 bytes.  */
+	      gcc_assert (sizeof (ctx->vregs[0]) == 16);
+#if defined (__AARCH64EB__)
+	      offset = offset + 8;
+#endif
+	      fs->regs.reg[AARCH64_DWARF_V0 + i].loc.offset = offset;
+	    }
+	}
+      else
+	{
+	  /* There is context provided that we do not recognize!  */
+	}
+    }
+
+  fs->regs.reg[31].how = REG_SAVED_OFFSET;
+  fs->regs.reg[31].loc.offset = (_Unwind_Ptr) & (sc->sp) - new_cfa;
+
+  fs->signal_frame = 1;
+
+  fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].how = REG_SAVED_VAL_OFFSET;
+  fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].loc.offset =
+    (_Unwind_Ptr) (sc->pc) - new_cfa;
+
+  fs->retaddr_column = DWARF_ALT_FRAME_RETURN_COLUMN;
+
+  return _URC_NO_REASON;
+}
+
+#endif
diff --git a/libgcc/config/aarch64/sfp-machine.h b/libgcc/config/aarch64/sfp-machine.h
index ...3a09ae7605f295af6ba40acc05d33b2fec7a96b2 100644
--- a/libgcc/config/aarch64/sfp-machine.h
+++ b/libgcc/config/aarch64/sfp-machine.h
@@ -0,0 +1,153 @@
+/* Machine description for AArch64 architecture.
+   Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#define _FP_W_TYPE_SIZE		64
+#define _FP_W_TYPE		unsigned long
+#define _FP_WS_TYPE		signed long
+#define _FP_I_TYPE		int
+
+typedef int TItype __attribute__ ((mode (TI)));
+typedef unsigned int UTItype __attribute__ ((mode (TI)));
+#define TI_BITS (__CHAR_BIT__ * (int)sizeof(TItype))
+
+/* The type of the result of a floating point comparison.  This must
+   match __libgcc_cmp_return__ in GCC for the target.  */
+typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
+#define CMPtype __gcc_CMPtype
+
+#define _FP_MUL_MEAT_Q(R,X,Y)				\
+  _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_Q(R,X,Y)	_FP_DIV_MEAT_2_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S		((_FP_QNANBIT_S << 1) - 1)
+#define _FP_NANFRAC_D		((_FP_QNANBIT_D << 1) - 1)
+#define _FP_NANFRAC_Q		((_FP_QNANBIT_Q << 1) - 1), -1
+#define _FP_NANSIGN_S		0
+#define _FP_NANSIGN_D		0
+#define _FP_NANSIGN_Q		0
+
+#define _FP_KEEPNANFRACP 1
+
+/* This appears to be in line with the VFP conventions in the v7-a
+   ARM-ARM. Need to check with the v8 version.  */
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)			\
+  do {								\
+    if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)		\
+	&& !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs))	\
+      {								\
+	R##_s = Y##_s;						\
+	_FP_FRAC_COPY_##wc(R,Y);				\
+      }								\
+    else							\
+      {								\
+	R##_s = X##_s;						\
+	_FP_FRAC_COPY_##wc(R,X);				\
+      }								\
+    R##_c = FP_CLS_NAN;						\
+  } while (0)
+
+#define FP_EX_INVALID	0x01
+#define FP_EX_DIVZERO	0x02
+#define FP_EX_OVERFLOW	0x04
+#define FP_EX_UNDERFLOW	0x08
+#define FP_EX_INEXACT	0x10
+
+#define FP_HANDLE_EXCEPTIONS						\
+  do {									\
+    const float fp_max = __FLT_MAX__;					\
+    const float fp_min = __FLT_MIN__;					\
+    const float fp_1e32 = 1.0e32f;					\
+    const float fp_zero = 0.0;						\
+    const float fp_one = 1.0;						\
+    unsigned fpsr;							\
+    if (_fex & FP_EX_INVALID)						\
+      {									\
+        __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
+			      :						\
+			      : "w" (fp_zero)				\
+			      : "s0");					\
+	__asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));		\
+      }									\
+    if (_fex & FP_EX_DIVZERO)						\
+      {									\
+	__asm__ __volatile__ ("fdiv\ts0, %s0, %s1"			\
+			      :						\
+			      : "w" (fp_one), "w" (fp_zero)		\
+			      : "s0");					\
+	__asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));		\
+      }									\
+    if (_fex & FP_EX_OVERFLOW)						\
+      {									\
+        __asm__ __volatile__ ("fadd\ts0, %s0, %s1"			\
+			      :						\
+			      : "w" (fp_max), "w" (fp_1e32)		\
+			      : "s0");					\
+        __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));		\
+      }									\
+    if (_fex & FP_EX_UNDERFLOW)						\
+      {									\
+	__asm__ __volatile__ ("fmul\ts0, %s0, %s0"			\
+			      :						\
+			      : "w" (fp_min)				\
+			      : "s0");					\
+	__asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));		\
+      }									\
+    if (_fex & FP_EX_INEXACT)						\
+      {									\
+	__asm__ __volatile__ ("fsub\ts0, %s0, %s1"			\
+			      :						\
+			      : "w" (fp_max), "w" (fp_one)		\
+			      : "s0");					\
+	__asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));		\
+      }									\
+  } while (0)
+
+
+#define FP_RND_NEAREST		0
+#define FP_RND_ZERO		0xc00000
+#define FP_RND_PINF		0x400000
+#define FP_RND_MINF		0x800000
+
+#define _FP_DECL_EX \
+  unsigned long int _fpcr __attribute__ ((unused)) = FP_RND_NEAREST
+
+#define FP_INIT_ROUNDMODE			\
+  do {						\
+    __asm__ __volatile__ ("mrs	%0, fpcr"	\
+			  : "=r" (_fpcr));	\
+  } while (0)
+
+#define FP_ROUNDMODE (_fpcr & 0xc00000)
+
+#define	__LITTLE_ENDIAN	1234
+#define	__BIG_ENDIAN	4321
+
+#if defined __AARCH64EB__
+# define __BYTE_ORDER __BIG_ENDIAN
+#else
+# define __BYTE_ORDER __LITTLE_ENDIAN
+#endif
+
+
+/* Define ALIASNAME as a strong alias for NAME.  */
+# define strong_alias(name, aliasname) _strong_alias(name, aliasname)
+# define _strong_alias(name, aliasname) \
+  extern __typeof (name) aliasname __attribute__ ((alias (#name)));
diff --git a/libgcc/config/aarch64/sync-cache.c b/libgcc/config/aarch64/sync-cache.c
index ...d7b621ee6d8504371a547e616ffeac4f1f37a6a1 100644
--- a/libgcc/config/aarch64/sync-cache.c
+++ b/libgcc/config/aarch64/sync-cache.c
@@ -0,0 +1,57 @@
+/* Machine description for AArch64 architecture.
+   Copyright (C) 2012 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+void
+__aarch64_sync_cache_range (const void *base, const void *end)
+{
+  unsigned icache_lsize;
+  unsigned dcache_lsize;
+  static unsigned int cache_info = 0;
+  const char *address;
+
+  if (! cache_info)
+    /* CTR_EL0 [3:0] contains log2 of icache line size in words.
+       CTR_EL0 [19:16] contains log2 of dcache line size in words.  */
+    asm volatile ("mrs\t%0, ctr_el0":"=r" (cache_info));
+
+  icache_lsize = 4 << (cache_info & 0xF);
+  dcache_lsize = 4 << ((cache_info >> 16) & 0xF);
+
+  /* Loop over the address range, clearing one cache line at once.
+     Data cache must be flushed to unification first to make sure the
+     instruction cache fetches the updated data.  'end' is exclusive,
+     as per the GNU definition of __clear_cache.  */
+
+  for (address = base; address < (const char *) end; address += dcache_lsize)
+    asm volatile ("dc\tcvau, %0"
+		  :
+		  : "r" (address)
+		  : "memory");
+
+  asm volatile ("dsb\tish" : : : "memory");
+
+  for (address = base; address < (const char *) end; address += icache_lsize)
+    asm volatile ("ic\tivau, %0"
+		  :
+		  : "r" (address)
+		  : "memory");
+
+  asm volatile ("dsb\tish; isb" : : : "memory");
+}
diff --git a/libgcc/config/aarch64/t-aarch64 b/libgcc/config/aarch64/t-aarch64
index ...002cb832902f87703a973bef0ee741c0516455bf 100644
--- a/libgcc/config/aarch64/t-aarch64
+++ b/libgcc/config/aarch64/t-aarch64
@@ -0,0 +1,21 @@
+# Machine description for AArch64 architecture.
+# Copyright (C) 2012 Free Software Foundation, Inc.
+# Contributed by ARM Ltd.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+LIB2ADD += $(srcdir)/config/aarch64/sync-cache.c
diff --git a/libgcc/config/aarch64/t-softfp b/libgcc/config/aarch64/t-softfp
index ...6500b5243e415e5bc10cd352cba8a75f05e8b433 100644
--- a/libgcc/config/aarch64/t-softfp
+++ b/libgcc/config/aarch64/t-softfp
@@ -0,0 +1,7 @@
+softfp_float_modes := tf
+softfp_int_modes := si di ti
+softfp_extensions := sftf dftf
+softfp_truncations := tfsf tfdf
+softfp_exclude_libgcc2 := n
+
+TARGET_LIBGCC2_CFLAGS += -Wno-missing-prototypes

[PATCH] [6/10] AArch64 Port

[Marcus Shawcroft]

[-- Attachment #1: Type: text/plain, Size: 137 bytes --]


This patch adjusts the libatomic configury for AArch64.

Proposed ChangeLog:

         * configure.tgt: Mark libatomic unsupported.

[-- Attachment #2: xx-libatomic-patch.txt --]
[-- Type: text/plain, Size: 491 bytes --]

diff --git a/libatomic/configure.tgt b/libatomic/configure.tgt
index 847ac41ebed81efff601fcb966d76f35d228dda2..0caa0f42ff99766d1020acd8d966509d0f3447ce 100644
--- a/libatomic/configure.tgt
+++ b/libatomic/configure.tgt
@@ -95,6 +95,11 @@ fi
 
 # Other system configury
 case "${target}" in
+  aarch64*)
+	# This is currently not supported in AArch64.
+	UNSUPPORTED=1
+	;;
+
   arm*-*-linux*)
 	# OS support for atomic primitives.
 	config_path="${config_path} linux/arm posix"

[PATCH] [3/10] AArch64 Port

[Marcus Shawcroft]

[-- Attachment #1: Type: text/plain, Size: 1651 bytes --]

This patch contains all of the new files for the target port itself,
the patch does not modify any existing file.

Proposed ChangeLog:

          * common/config/aarch64/aarch64-common.c: New file.
          * config/aarch64/aarch64-arches.def: New file.
          * config/aarch64/aarch64-builtins.c: New file.
          * config/aarch64/aarch64-cores.def: New file.
          * config/aarch64/aarch64-elf-raw.h: New file.
          * config/aarch64/aarch64-elf.h: New file.
          * config/aarch64/aarch64-generic.md: New file.
          * config/aarch64/aarch64-linux.h: New file.
          * config/aarch64/aarch64-modes.def: New file.
          * config/aarch64/aarch64-option-extensions.def: New file.
          * config/aarch64/aarch64-opts.h: New file.
          * config/aarch64/aarch64-protos.h: New file.
          * config/aarch64/aarch64-simd.md: New file.
          * config/aarch64/aarch64-tune.md: New file.
          * config/aarch64/aarch64.c: New file.
          * config/aarch64/aarch64.h: New file.
          * config/aarch64/aarch64.md: New file.
          * config/aarch64/aarch64.opt: New file.
          * config/aarch64/arm_neon.h: New file.
          * config/aarch64/constraints.md: New file.
          * config/aarch64/gentune.sh: New file.
          * config/aarch64/iterators.md: New file.
          * config/aarch64/large.md: New file.
          * config/aarch64/predicates.md: New file.
          * config/aarch64/small.md: New file.
          * config/aarch64/sync.md: New file.
          * config/aarch64/t-aarch64-linux: New file.
          * config/aarch64/t-aarch64: New file.

[-- Attachment #2: xx-gcc-new-files-patch.txt.gz --]
[-- Type: application/x-gzip, Size: 163204 bytes --]

Re: [PATCH] [9/10] AArch64 Port

[Jakub Jelinek]

On Tue, Oct 23, 2012 at 10:42:57AM +0100, Marcus Shawcroft wrote:
> This patch adjusts the libgomp configury for AArch64.
> 
> Proposed ChangeLog:
> 
>         * configure.tgt: Add AArch64.

This is ok.

> diff --git a/libgomp/configure.tgt b/libgomp/configure.tgt
> index d5a1480e4812634ae280238684cb2187b2c618f8..2eecc93a349f3afe9e0afbbc2e98194065873498 100644
> --- a/libgomp/configure.tgt
> +++ b/libgomp/configure.tgt
> @@ -27,6 +27,10 @@ config_path="posix"
>  if test $enable_linux_futex = yes; then
>    case "${target}" in
>  
> +    aarch64*-*-linux*)
> +	config_path="linux posix"
> +	;;
> +
>      alpha*-*-linux*)
>  	config_path="linux/alpha linux posix"
>  	;;


	Jakub

Re: [PATCH] [2/10] AArch64 Port

[Joseph S. Myers]

On Tue, 23 Oct 2012, Marcus Shawcroft wrote:

> +@item -mcmodel=tiny
> +@opindex mcmodel=tiny
> +Generate code for the tiny code model.  The program and its statically defined
> +symbols must be within 1GB of each other.  Pointers are 64 bits.  Programs can
> +be statically or dynamically linked.  This model is not fully implemented and
> +mostly treated as "small".

Say @samp{small} instead of using "" quotes in Texinfo sources.

-- 
Joseph S. Myers
joseph@codesourcery.com

Re: [PATCH] [4/10] AArch64 Port

[Jeff Law]

On 10/23/2012 03:42 AM, Marcus Shawcroft wrote:
> This patch contains the adjustments to the existing test suite to
> support AArch64.
>
> Proposed ChangeLog:
>
>           * lib/target-supports.exp
>           (check_profiling_available): Add AArch64.
>           (check_effective_target_vect_int): Likewise.
>           (check_effective_target_vect_shift): Likewise.
>           (check_effective_target_vect_float): Likewise.
>           (check_effective_target_vect_double): Likewise.
>           (check_effective_target_vect_widen_mult_qi_to_hi): Likewise.
>           (check_effective_target_vect_widen_mult_hi_to_si): Likewise.
>           (check_effective_target_vect_pack_trunc): Likewise.
>           (check_effective_target_vect_unpack): Likewise.
>           (check_effective_target_vect_hw_misalign): Likewise.
>           (check_effective_target_vect_short_mult): Likewise.
>           (check_effective_target_vect_int_mult): Likewise.
>           (check_effective_target_vect_stridedN): Likewise.
>           (check_effective_target_sync_int_long): Likewise.
>           (check_effective_target_sync_char_short): Likewise.
>           (check_vect_support_and_set_flags): Likewise.
>           (check_effective_target_aarch64_tiny): New.
>           (check_effective_target_aarch64_small): New.
>           (check_effective_target_aarch64_large): New.
>           * g++.dg/other/PR23205.C: Enable aarch64.
>           * g++.dg/other/pr23205-2.C: Likewise.
>           * g++.old-deja/g++.abi/ptrmem.C: Likewise.
>           * gcc.c-torture/execute/20101011-1.c: Likewise.
>           * gcc.dg/20020312-2.c: Likewise.
>           * gcc.dg/20040813-1.c: Likewise.
>           * gcc.dg/builtin-apply2.c: Likewise.
>           * gcc.dg/stack-usage-1.c: Likewise.
This is good.  Please install.
jeff

Re: [PATCH] [7/10] AArch64 Port

[Jeff Law]

On 10/23/2012 03:42 AM, Marcus Shawcroft wrote:
> This patch adjusts the libcpp configury for AArch64.
>
> Proposed ChangeLog:
>
>          * configure.ac: Enable AArch64.
>          * configure: Regenerate.
This is fine.  Please install.

Jeff

Re: [PATCH] [6/10] AArch64 Port

[Jeff Law]

On 10/23/2012 03:42 AM, Marcus Shawcroft wrote:
>
> This patch adjusts the libatomic configury for AArch64.
>
> Proposed ChangeLog:
>
>          * configure.tgt: Mark libatomic unsupported.
This is good.  Please install.  Presumably at some point in the not too 
distant future, aarch support will be added to libatomic?

jeff

Re: [PATCH] [5/10] AArch64 Port

[Jeff Law]

On 10/23/2012 03:42 AM, Marcus Shawcroft wrote:
> This patch contains all of the new files added to the test suite for
> AArch64, the patch does not modify any existing file.
>
> Proposed ChangeLog:
>
>          * gcc.target/aarch64/aapcs/aapcs64.exp: New file.
>          * gcc.target/aarch64/aapcs/abitest-2.h: New file.
>          * gcc.target/aarch64/aapcs/abitest-common.h: New file.
>          * gcc.target/aarch64/aapcs/abitest.S: New file.
>          * gcc.target/aarch64/aapcs/abitest.h: New file.
>          * gcc.target/aarch64/aapcs/func-ret-1.c: New file.
>          * gcc.target/aarch64/aapcs/func-ret-2.c: New file.
>          * gcc.target/aarch64/aapcs/func-ret-3.c: New file.
>          * gcc.target/aarch64/aapcs/func-ret-3.x: New file.
>          * gcc.target/aarch64/aapcs/func-ret-4.c: New file.
>          * gcc.target/aarch64/aapcs/func-ret-4.x: New file.
>          * gcc.target/aarch64/aapcs/ice_1.c: New file.
>          * gcc.target/aarch64/aapcs/ice_2.c: New file.
>          * gcc.target/aarch64/aapcs/ice_3.c: New file.
>          * gcc.target/aarch64/aapcs/ice_4.c: New file.
>          * gcc.target/aarch64/aapcs/ice_5.c: New file.
>          * gcc.target/aarch64/aapcs/macro-def.h: New file.
>          * gcc.target/aarch64/aapcs/test_1.c: New file.
>          * gcc.target/aarch64/aapcs/test_10.c: New file.
>          * gcc.target/aarch64/aapcs/test_11.c: New file.
>          * gcc.target/aarch64/aapcs/test_12.c: New file.
>          * gcc.target/aarch64/aapcs/test_13.c: New file.
>          * gcc.target/aarch64/aapcs/test_14.c: New file.
>          * gcc.target/aarch64/aapcs/test_15.c: New file.
>          * gcc.target/aarch64/aapcs/test_16.c: New file.
>          * gcc.target/aarch64/aapcs/test_17.c: New file.
>          * gcc.target/aarch64/aapcs/test_18.c: New file.
>          * gcc.target/aarch64/aapcs/test_19.c: New file.
>          * gcc.target/aarch64/aapcs/test_2.c: New file.
>          * gcc.target/aarch64/aapcs/test_20.c: New file.
>          * gcc.target/aarch64/aapcs/test_21.c: New file.
>          * gcc.target/aarch64/aapcs/test_22.c: New file.
>          * gcc.target/aarch64/aapcs/test_23.c: New file.
>          * gcc.target/aarch64/aapcs/test_24.c: New file.
>          * gcc.target/aarch64/aapcs/test_25.c: New file.
>          * gcc.target/aarch64/aapcs/test_26.c: New file.
>          * gcc.target/aarch64/aapcs/test_3.c: New file.
>          * gcc.target/aarch64/aapcs/test_4.c: New file.
>          * gcc.target/aarch64/aapcs/test_5.c: New file.
>          * gcc.target/aarch64/aapcs/test_6.c: New file.
>          * gcc.target/aarch64/aapcs/test_7.c: New file.
>          * gcc.target/aarch64/aapcs/test_8.c: New file.
>          * gcc.target/aarch64/aapcs/test_9.c: New file.
>          * gcc.target/aarch64/aapcs/test_align-1.c: New file.
>          * gcc.target/aarch64/aapcs/test_align-2.c: New file.
>          * gcc.target/aarch64/aapcs/test_align-3.c: New file.
>          * gcc.target/aarch64/aapcs/test_align-4.c: New file.
>          * gcc.target/aarch64/aapcs/test_complex.c: New file.
>          * gcc.target/aarch64/aapcs/test_int128.c: New file.
>          * gcc.target/aarch64/aapcs/test_quad_double.c: New file.
>          * gcc.target/aarch64/aapcs/type-def.h: New file.
>          * gcc.target/aarch64/aapcs/va_arg-1.c: New file.
>          * gcc.target/aarch64/aapcs/va_arg-10.c: New file.
>          * gcc.target/aarch64/aapcs/va_arg-11.c: New file.
>          * gcc.target/aarch64/aapcs/va_arg-12.c: New file.
>          * gcc.target/aarch64/aapcs/va_arg-2.c: New file.
>          * gcc.target/aarch64/aapcs/va_arg-3.c: New file.
>          * gcc.target/aarch64/aapcs/va_arg-4.c: New file.
>          * gcc.target/aarch64/aapcs/va_arg-5.c: New file.
>          * gcc.target/aarch64/aapcs/va_arg-6.c: New file.
>          * gcc.target/aarch64/aapcs/va_arg-7.c: New file.
>          * gcc.target/aarch64/aapcs/va_arg-8.c: New file.
>          * gcc.target/aarch64/aapcs/va_arg-9.c: New file.
>          * gcc.target/aarch64/aapcs/validate_memory.h: New file.
>          * gcc.target/aarch64/aarch64.exp: New file.
>          * gcc.target/aarch64/adc-1.c: New file.
>          * gcc.target/aarch64/adc-2.c: New file.
>          * gcc.target/aarch64/asm-1.c: New file.
>          * gcc.target/aarch64/clrsb.c: New file.
>          * gcc.target/aarch64/clz.c: New file.
>          * gcc.target/aarch64/ctz.c: New file.
>          * gcc.target/aarch64/csinc-1.c: New file.
>          * gcc.target/aarch64/csinv-1.c: New file.
>          * gcc.target/aarch64/csneg-1.c: New file.
>          * gcc.target/aarch64/extend.c: New file.
>          * gcc.target/aarch64/fcvt.x: New file.
>          * gcc.target/aarch64/fcvt_double_int.c: New file.
>          * gcc.target/aarch64/fcvt_double_long.c: New file.
>          * gcc.target/aarch64/fcvt_double_uint.c: New file.
>          * gcc.target/aarch64/fcvt_double_ulong.c: New file.
>          * gcc.target/aarch64/fcvt_float_int.c: New file.
>          * gcc.target/aarch64/fcvt_float_long.c: New file.
>          * gcc.target/aarch64/fcvt_float_uint.c: New file.
>          * gcc.target/aarch64/fcvt_float_ulong.c: New file.
>          * gcc.target/aarch64/ffs.c: New file.
>          * gcc.target/aarch64/fmadd.c: New file.
>          * gcc.target/aarch64/fnmadd-fastmath.c: New file.
>          * gcc.target/aarch64/frint.x: New file.
>          * gcc.target/aarch64/frint_double.c: New file.
>          * gcc.target/aarch64/frint_float.c: New file.
>          * gcc.target/aarch64/index.c: New file.
>          * gcc.target/aarch64/mneg-1.c: New file.
>          * gcc.target/aarch64/mneg-2.c: New file.
>          * gcc.target/aarch64/mneg-3.c: New file.
>          * gcc.target/aarch64/mnegl-1.c: New file.
>          * gcc.target/aarch64/mnegl-2.c: New file.
>          * gcc.target/aarch64/narrow_high-intrinsics.c: New file.
>          * gcc.target/aarch64/pic-constantpool1.c: New file.
>          * gcc.target/aarch64/pic-symrefplus.c: New file.
>          * gcc.target/aarch64/predefine_large.c: New file.
>          * gcc.target/aarch64/predefine_small.c: New file.
>          * gcc.target/aarch64/predefine_tiny.c: New file.
>          * gcc.target/aarch64/reload-valid-spoff.c: New file.
>          * gcc.target/aarch64/scalar_intrinsics.c: New file.
>          * gcc.target/aarch64/table-intrinsics.c: New file.
>          * gcc.target/aarch64/tst-1.c: New file.
>          * gcc.target/aarch64/vect-abs-compile.c: New file.
>          * gcc.target/aarch64/vect-abs.c: New file.
>          * gcc.target/aarch64/vect-abs.x: New file.
>          * gcc.target/aarch64/vect-compile.c: New file.
>          * gcc.target/aarch64/vect-faddv-compile.c: New file.
>          * gcc.target/aarch64/vect-faddv.c: New file.
>          * gcc.target/aarch64/vect-faddv.x: New file.
>          * gcc.target/aarch64/vect-fmax-fmin-compile.c: New file.
>          * gcc.target/aarch64/vect-fmax-fmin.c: New file.
>          * gcc.target/aarch64/vect-fmax-fmin.x: New file.
>          * gcc.target/aarch64/vect-fmaxv-fminv-compile.c: New file.
>          * gcc.target/aarch64/vect-fmaxv-fminv.x: New file.
>          * gcc.target/aarch64/vect-fp-compile.c: New file.
>          * gcc.target/aarch64/vect-fp.c: New file.
>          * gcc.target/aarch64/vect-fp.x: New file.
>          * gcc.target/aarch64/vect-mull-compile.c: New file.
>          * gcc.target/aarch64/vect-mull.c: New file.
>          * gcc.target/aarch64/vect-mull.x: New file.
>          * gcc.target/aarch64/vect.c: New file.
>          * gcc.target/aarch64/vect.x: New file.
>          * gcc.target/aarch64/vector_intrinsics.c: New file.
>          * gcc.target/aarch64/vfp-1.c: New file.
>          * gcc.target/aarch64/volatile-bitfields-1.c: New file.
>          * gcc.target/aarch64/volatile-bitfields-2.c: New file.
>          * gcc.target/aarch64/volatile-bitfields-3.c: New file.
>          * g++.dg/abi/aarch64_guard1.C: New file.
This is good.  I like seeing the ABI testing.   Please install.

Thanks,
Jeff

Re: [PATCH] [8/10] AArch64 Port

[Jeff Law]

On 10/23/2012 03:42 AM, Marcus Shawcroft wrote:
> This patch provides the AArch64 libgcc port, it contains both the
> required configury adjustment to config.host and the new files
> introduced by the AArch64 port.
>
> Proposed ChangeLog:
>
>          * config.host (aarch64*-*-elf, aarch64*-*-linux*): New.
>          * config/aarch64/crti.S: New file.
>          * config/aarch64/crtn.S: New file.
>          * config/aarch64/linux-unwind.h: New file.
>          * config/aarch64/sfp-machine.h: New file.
>          * config/aarch64/sync-cache.c: New file.
>          * config/aarch64/t-aarch64: New file.
>          * config/aarch64/t-softfp: New file.
This is fine.  Please install.

Jeff

Re: [PATCH] [2/10] AArch64 Port

[Jeff Law]

On 10/23/2012 03:42 AM, Marcus Shawcroft wrote:
> This patch contains the additions to the gcc/doc files to document
> the AArch64 port.
>
> Proposed ChangeLog:
>
>           * doc/invoke.texi (AArch64 Options): New.
>           * doc/md.texi (Machine Constraints): Add AArch64.
This is fine.  Please install.
jeff

Re: [PATCH] [3/10] AArch64 Port

[Jeff Law]

On 10/23/2012 03:42 AM, Marcus Shawcroft wrote:
> This patch contains all of the new files for the target port itself,
> the patch does not modify any existing file.
>
> Proposed ChangeLog:
>
>           * common/config/aarch64/aarch64-common.c: New file.
>           * config/aarch64/aarch64-arches.def: New file.
>           * config/aarch64/aarch64-builtins.c: New file.
>           * config/aarch64/aarch64-cores.def: New file.
>           * config/aarch64/aarch64-elf-raw.h: New file.
>           * config/aarch64/aarch64-elf.h: New file.
>           * config/aarch64/aarch64-generic.md: New file.
>           * config/aarch64/aarch64-linux.h: New file.
>           * config/aarch64/aarch64-modes.def: New file.
>           * config/aarch64/aarch64-option-extensions.def: New file.
>           * config/aarch64/aarch64-opts.h: New file.
>           * config/aarch64/aarch64-protos.h: New file.
>           * config/aarch64/aarch64-simd.md: New file.
>           * config/aarch64/aarch64-tune.md: New file.
>           * config/aarch64/aarch64.c: New file.
>           * config/aarch64/aarch64.h: New file.
>           * config/aarch64/aarch64.md: New file.
>           * config/aarch64/aarch64.opt: New file.
>           * config/aarch64/arm_neon.h: New file.
>           * config/aarch64/constraints.md: New file.
>           * config/aarch64/gentune.sh: New file.
>           * config/aarch64/iterators.md: New file.
>           * config/aarch64/large.md: New file.
>           * config/aarch64/predicates.md: New file.
>           * config/aarch64/small.md: New file.
>           * config/aarch64/sync.md: New file.
>           * config/aarch64/t-aarch64-linux: New file.
>           * config/aarch64/t-aarch64: New file.
Given that you and Richard Earnshaw are the approved maintainers for the 
AAarch64 port, I'm going to give this an OK without diving into it.  I'm 
going to assume you and Richard will iterate with anyone who does dive 
deeply into the port and has comments/suggestions.

The one question in the back of my mind is whether or not this uses the 
new iterator support we discussed a few months ago?  I can't recall if 
that was integrated into the trunk or not.

Jeff

Re: [PATCH] [10/10] AArch64 Port

[Jeff Law]

On 10/23/2012 03:43 AM, Marcus Shawcroft wrote:
> This patch provides the AArch64 libstdc++-v3 port, it contains both the
> required configury adjustment to config.host and the new file introduced
> by the AArch64 port.
>
> Proposed ChangeLog:
>
>          * config/cpu/aarch64/cxxabi_tweaks.h: New file.
>          * configure.host: Enable aarch64.
This is fine.  Thanks.

Jeff

Re: [PATCH] [1/10] AArch64 Port

[Jeff Law]

On 10/23/2012 03:42 AM, Marcus Shawcroft wrote:
>
> This patch contains the adjustments to top level gcc configury required
> to enable the AArch64 port.
>
> Proposed ChangeLog:
>
>           * config.gcc: Add AArch64.
>           * configure.ac: Add AArch64 TLS support detection.
>           * configure: Regenerate.
OK.
Jeff

Re: [PATCH] [3/10] AArch64 Port

[Ramana Radhakrishnan]

On 10/23/12 16:38, Jeff Law wrote:
 > On 10/23/2012 03:42 AM, Marcus Shawcroft wrote:
 >
 > The one question in the back of my mind is whether or not this uses the
 > new iterator support we discussed a few months ago?  I can't recall if
 > that was integrated into the trunk or not.

Generic support for int-iterators went in around June . So I'd expect 
the port to be using it quite aggressively especially as the feature was 
first developed as part of the aarch64 port.

Ramana

Re: [PATCH] [3/10] AArch64 Port

[Marcus Shawcroft]

On 23/10/12 16:38, Jeff Law wrote:

> Given that you and Richard Earnshaw are the approved maintainers for the
> AAarch64 port, I'm going to give this an OK without diving into it.  I'm
> going to assume you and Richard will iterate with anyone who does dive
> deeply into the port and has comments/suggestions.

We will iterate as required with any further comments and suggestions 
raised.

> The one question in the back of my mind is whether or not this uses the
> new iterator support we discussed a few months ago?  I can't recall if
> that was integrated into the trunk or not.

The int-iterator support was accepted on trunk ~ 12th June.  The AArch64 
port does make extensive use of them.

/Marcus

Re: [PATCH] [6/10] AArch64 Port

[Marcus Shawcroft]

On 23/10/12 16:14, Jeff Law wrote:
> On 10/23/2012 03:42 AM, Marcus Shawcroft wrote:
>>
>> This patch adjusts the libatomic configury for AArch64.
>>
>> Proposed ChangeLog:
>>
>>           * configure.tgt: Mark libatomic unsupported.
> This is good.  Please install.  Presumably at some point in the not too
> distant future, aarch support will be added to libatomic?
>
> jeff
>
>

We have support for atomic optab coming real soon now at which point I 
think we can simply revert this patch.

/Marcus

Re: [PATCH] [2/10] AArch64 Port

[Marcus Shawcroft]

On 23/10/12 15:39, Joseph S. Myers wrote:
> On Tue, 23 Oct 2012, Marcus Shawcroft wrote:
>
>> +@item -mcmodel=tiny
>> +@opindex mcmodel=tiny
>> +Generate code for the tiny code model.  The program and its statically defined
>> +symbols must be within 1GB of each other.  Pointers are 64 bits.  Programs can
>> +be statically or dynamically linked.  This model is not fully implemented and
>> +mostly treated as "small".
>
> Say @samp{small} instead of using "" quotes in Texinfo sources.
>

Committed with this correction.

Thankyou

/Marcus

Re: [PATCH] [7/10] AArch64 Port

[Tom Tromey]

>>>>> "Marcus" == Marcus Shawcroft <marcus.shawcroft@arm.com> writes:

Marcus> This patch adjusts the libcpp configury for AArch64.
Marcus> Proposed ChangeLog:

Marcus>         * configure.ac: Enable AArch64.
Marcus>         * configure: Regenerate.

This is ok.  Thanks.

Tom