* [PATCH] RISC-V: Fix vsetvl pass ICE
@ 2023-08-30 9:51 Lehua Ding
2023-08-31 0:07 ` juzhe.zhong
0 siblings, 1 reply; 7+ messages in thread
From: Lehua Ding @ 2023-08-30 9:51 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, rdapp.gcc, palmer, jeffreyalaw
This patch fix pr111234 (a vsetvl pass ICE) when fuse a mask any
vlmax vsetvl_vtype_change_only insn with a mu vsetvl insn.
PR target/111234
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Remove condition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr111234.c: New test.
---
gcc/config/riscv/riscv-vsetvl.cc | 2 +-
.../gcc.target/riscv/rvv/vsetvl/pr111234.c | 19 +++++++++++++++++++
2 files changed, 20 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 1386d9250ca..a81bb53a521 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -655,7 +655,7 @@ gen_vsetvl_pat (rtx_insn *rinsn, const vector_insn_info &info,
new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, vl);
else
{
- if (vsetvl_insn_p (rinsn) || vlmax_avl_p (info.get_avl ()))
+ if (vsetvl_insn_p (rinsn))
new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, get_vl (rinsn));
else if (INSN_CODE (rinsn) == CODE_FOR_vsetvl_vtype_change_only)
new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, new_info, NULL_RTX);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
new file mode 100644
index 00000000000..ee5eec4a257
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include <riscv_vector.h>
+
+void
+f (vint32m1_t *in, vint64m2_t *out, vbool32_t *m, int b)
+{
+ vint32m1_t va = *in;
+ vbool32_t mask = *m;
+ vint64m2_t vb
+ = __riscv_vwadd_vx_i64m2_m (mask, va, 1, __riscv_vsetvlmax_e64m2 ());
+ vint64m2_t vc = __riscv_vadd_vx_i64m2 (vb, 1, __riscv_vsetvlmax_e64m2 ());
+
+ if (b != 0)
+ vc = __riscv_vadd_vx_i64m2_mu (mask, vc, vc, 1, __riscv_vsetvlmax_e64m2 ());
+
+ *out = vc;
+}
--
2.36.3
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Fix vsetvl pass ICE
2023-08-30 9:51 [PATCH] RISC-V: Fix vsetvl pass ICE Lehua Ding
@ 2023-08-31 0:07 ` juzhe.zhong
2023-08-31 1:44 ` Kito Cheng
0 siblings, 1 reply; 7+ messages in thread
From: juzhe.zhong @ 2023-08-31 0:07 UTC (permalink / raw)
To: 丁乐华, gcc-patches
Cc: kito.cheng, Robin Dapp, palmer, jeffreyalaw
[-- Attachment #1: Type: text/plain, Size: 2337 bytes --]
Ok for trunk. But not sure whether it's ok for GCC-13.
juzhe.zhong@rivai.ai
From: Lehua Ding
Date: 2023-08-30 17:51
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
Subject: [PATCH] RISC-V: Fix vsetvl pass ICE
This patch fix pr111234 (a vsetvl pass ICE) when fuse a mask any
vlmax vsetvl_vtype_change_only insn with a mu vsetvl insn.
PR target/111234
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Remove condition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr111234.c: New test.
---
gcc/config/riscv/riscv-vsetvl.cc | 2 +-
.../gcc.target/riscv/rvv/vsetvl/pr111234.c | 19 +++++++++++++++++++
2 files changed, 20 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 1386d9250ca..a81bb53a521 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -655,7 +655,7 @@ gen_vsetvl_pat (rtx_insn *rinsn, const vector_insn_info &info,
new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, vl);
else
{
- if (vsetvl_insn_p (rinsn) || vlmax_avl_p (info.get_avl ()))
+ if (vsetvl_insn_p (rinsn))
new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, get_vl (rinsn));
else if (INSN_CODE (rinsn) == CODE_FOR_vsetvl_vtype_change_only)
new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, new_info, NULL_RTX);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
new file mode 100644
index 00000000000..ee5eec4a257
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include <riscv_vector.h>
+
+void
+f (vint32m1_t *in, vint64m2_t *out, vbool32_t *m, int b)
+{
+ vint32m1_t va = *in;
+ vbool32_t mask = *m;
+ vint64m2_t vb
+ = __riscv_vwadd_vx_i64m2_m (mask, va, 1, __riscv_vsetvlmax_e64m2 ());
+ vint64m2_t vc = __riscv_vadd_vx_i64m2 (vb, 1, __riscv_vsetvlmax_e64m2 ());
+
+ if (b != 0)
+ vc = __riscv_vadd_vx_i64m2_mu (mask, vc, vc, 1, __riscv_vsetvlmax_e64m2 ());
+
+ *out = vc;
+}
--
2.36.3
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Fix vsetvl pass ICE
2023-08-31 0:07 ` juzhe.zhong
@ 2023-08-31 1:44 ` Kito Cheng
2023-08-31 2:12 ` Lehua Ding
0 siblings, 1 reply; 7+ messages in thread
From: Kito Cheng @ 2023-08-31 1:44 UTC (permalink / raw)
To: juzhe.zhong; +Cc: 丁乐华, gcc-patches
OK for gcc 13 branch too, the general rule for backport is to wait one
week on trunk to make sure the fix is stable.
On Thu, Aug 31, 2023 at 8:08 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> Ok for trunk. But not sure whether it's ok for GCC-13.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: Lehua Ding
> Date: 2023-08-30 17:51
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
> Subject: [PATCH] RISC-V: Fix vsetvl pass ICE
> This patch fix pr111234 (a vsetvl pass ICE) when fuse a mask any
> vlmax vsetvl_vtype_change_only insn with a mu vsetvl insn.
>
> PR target/111234
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Remove condition.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/pr111234.c: New test.
>
> ---
> gcc/config/riscv/riscv-vsetvl.cc | 2 +-
> .../gcc.target/riscv/rvv/vsetvl/pr111234.c | 19 +++++++++++++++++++
> 2 files changed, 20 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
> index 1386d9250ca..a81bb53a521 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -655,7 +655,7 @@ gen_vsetvl_pat (rtx_insn *rinsn, const vector_insn_info &info,
> new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, vl);
> else
> {
> - if (vsetvl_insn_p (rinsn) || vlmax_avl_p (info.get_avl ()))
> + if (vsetvl_insn_p (rinsn))
> new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, get_vl (rinsn));
> else if (INSN_CODE (rinsn) == CODE_FOR_vsetvl_vtype_change_only)
> new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, new_info, NULL_RTX);
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> new file mode 100644
> index 00000000000..ee5eec4a257
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> @@ -0,0 +1,19 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include <riscv_vector.h>
> +
> +void
> +f (vint32m1_t *in, vint64m2_t *out, vbool32_t *m, int b)
> +{
> + vint32m1_t va = *in;
> + vbool32_t mask = *m;
> + vint64m2_t vb
> + = __riscv_vwadd_vx_i64m2_m (mask, va, 1, __riscv_vsetvlmax_e64m2 ());
> + vint64m2_t vc = __riscv_vadd_vx_i64m2 (vb, 1, __riscv_vsetvlmax_e64m2 ());
> +
> + if (b != 0)
> + vc = __riscv_vadd_vx_i64m2_mu (mask, vc, vc, 1, __riscv_vsetvlmax_e64m2 ());
> +
> + *out = vc;
> +}
> --
> 2.36.3
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Fix vsetvl pass ICE
2023-08-31 1:44 ` Kito Cheng
@ 2023-08-31 2:12 ` Lehua Ding
2023-09-18 7:54 ` Lehua Ding
0 siblings, 1 reply; 7+ messages in thread
From: Lehua Ding @ 2023-08-31 2:12 UTC (permalink / raw)
To: Kito Cheng, juzhe.zhong; +Cc: gcc-patches
Committed to the trunk and backported to GCC 13 one week later.
Thanks Juzhe and Kito.
On 2023/8/31 9:44, Kito Cheng via Gcc-patches wrote:
> OK for gcc 13 branch too, the general rule for backport is to wait one
> week on trunk to make sure the fix is stable.
>
>
> On Thu, Aug 31, 2023 at 8:08 AM juzhe.zhong@rivai.ai
> <juzhe.zhong@rivai.ai> wrote:
>>
>> Ok for trunk. But not sure whether it's ok for GCC-13.
>>
>>
>>
>> juzhe.zhong@rivai.ai
>>
>> From: Lehua Ding
>> Date: 2023-08-30 17:51
>> To: gcc-patches
>> CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
>> Subject: [PATCH] RISC-V: Fix vsetvl pass ICE
>> This patch fix pr111234 (a vsetvl pass ICE) when fuse a mask any
>> vlmax vsetvl_vtype_change_only insn with a mu vsetvl insn.
>>
>> PR target/111234
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Remove condition.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/rvv/vsetvl/pr111234.c: New test.
>>
>> ---
>> gcc/config/riscv/riscv-vsetvl.cc | 2 +-
>> .../gcc.target/riscv/rvv/vsetvl/pr111234.c | 19 +++++++++++++++++++
>> 2 files changed, 20 insertions(+), 1 deletion(-)
>> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
>>
>> diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
>> index 1386d9250ca..a81bb53a521 100644
>> --- a/gcc/config/riscv/riscv-vsetvl.cc
>> +++ b/gcc/config/riscv/riscv-vsetvl.cc
>> @@ -655,7 +655,7 @@ gen_vsetvl_pat (rtx_insn *rinsn, const vector_insn_info &info,
>> new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, vl);
>> else
>> {
>> - if (vsetvl_insn_p (rinsn) || vlmax_avl_p (info.get_avl ()))
>> + if (vsetvl_insn_p (rinsn))
>> new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, get_vl (rinsn));
>> else if (INSN_CODE (rinsn) == CODE_FOR_vsetvl_vtype_change_only)
>> new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, new_info, NULL_RTX);
>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
>> new file mode 100644
>> index 00000000000..ee5eec4a257
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
>> @@ -0,0 +1,19 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
>> +
>> +#include <riscv_vector.h>
>> +
>> +void
>> +f (vint32m1_t *in, vint64m2_t *out, vbool32_t *m, int b)
>> +{
>> + vint32m1_t va = *in;
>> + vbool32_t mask = *m;
>> + vint64m2_t vb
>> + = __riscv_vwadd_vx_i64m2_m (mask, va, 1, __riscv_vsetvlmax_e64m2 ());
>> + vint64m2_t vc = __riscv_vadd_vx_i64m2 (vb, 1, __riscv_vsetvlmax_e64m2 ());
>> +
>> + if (b != 0)
>> + vc = __riscv_vadd_vx_i64m2_mu (mask, vc, vc, 1, __riscv_vsetvlmax_e64m2 ());
>> +
>> + *out = vc;
>> +}
>> --
>> 2.36.3
>>
--
Best,
Lehua
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Fix vsetvl pass ICE
2023-08-31 2:12 ` Lehua Ding
@ 2023-09-18 7:54 ` Lehua Ding
2023-09-18 8:08 ` Kito Cheng
0 siblings, 1 reply; 7+ messages in thread
From: Lehua Ding @ 2023-09-18 7:54 UTC (permalink / raw)
To: Kito Cheng; +Cc: gcc-patches, juzhe.zhong
Hi Kito,
Can this bugfix be backported to GCC 13 now? If so, how can I do it?
On 2023/8/31 10:12, Lehua Ding wrote:
> Committed to the trunk and backported to GCC 13 one week later.
> Thanks Juzhe and Kito.
>
> On 2023/8/31 9:44, Kito Cheng via Gcc-patches wrote:
>> OK for gcc 13 branch too, the general rule for backport is to wait one
>> week on trunk to make sure the fix is stable.
>>
>>
>> On Thu, Aug 31, 2023 at 8:08 AM juzhe.zhong@rivai.ai
>> <juzhe.zhong@rivai.ai> wrote:
>>>
>>> Ok for trunk. But not sure whether it's ok for GCC-13.
>>>
>>>
>>>
>>> juzhe.zhong@rivai.ai
>>>
>>> From: Lehua Ding
>>> Date: 2023-08-30 17:51
>>> To: gcc-patches
>>> CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
>>> Subject: [PATCH] RISC-V: Fix vsetvl pass ICE
>>> This patch fix pr111234 (a vsetvl pass ICE) when fuse a mask any
>>> vlmax vsetvl_vtype_change_only insn with a mu vsetvl insn.
>>>
>>> PR target/111234
>>>
>>> gcc/ChangeLog:
>>>
>>> * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Remove condition.
>>>
>>> gcc/testsuite/ChangeLog:
>>>
>>> * gcc.target/riscv/rvv/vsetvl/pr111234.c: New test.
>>>
>>> ---
>>> gcc/config/riscv/riscv-vsetvl.cc | 2 +-
>>> .../gcc.target/riscv/rvv/vsetvl/pr111234.c | 19 +++++++++++++++++++
>>> 2 files changed, 20 insertions(+), 1 deletion(-)
>>> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
>>>
>>> diff --git a/gcc/config/riscv/riscv-vsetvl.cc
>>> b/gcc/config/riscv/riscv-vsetvl.cc
>>> index 1386d9250ca..a81bb53a521 100644
>>> --- a/gcc/config/riscv/riscv-vsetvl.cc
>>> +++ b/gcc/config/riscv/riscv-vsetvl.cc
>>> @@ -655,7 +655,7 @@ gen_vsetvl_pat (rtx_insn *rinsn, const
>>> vector_insn_info &info,
>>> new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, vl);
>>> else
>>> {
>>> - if (vsetvl_insn_p (rinsn) || vlmax_avl_p (info.get_avl ()))
>>> + if (vsetvl_insn_p (rinsn))
>>> new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, get_vl (rinsn));
>>> else if (INSN_CODE (rinsn) == CODE_FOR_vsetvl_vtype_change_only)
>>> new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, new_info, NULL_RTX);
>>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
>>> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
>>> new file mode 100644
>>> index 00000000000..ee5eec4a257
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
>>> @@ -0,0 +1,19 @@
>>> +/* { dg-do compile } */
>>> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
>>> +
>>> +#include <riscv_vector.h>
>>> +
>>> +void
>>> +f (vint32m1_t *in, vint64m2_t *out, vbool32_t *m, int b)
>>> +{
>>> + vint32m1_t va = *in;
>>> + vbool32_t mask = *m;
>>> + vint64m2_t vb
>>> + = __riscv_vwadd_vx_i64m2_m (mask, va, 1, __riscv_vsetvlmax_e64m2
>>> ());
>>> + vint64m2_t vc = __riscv_vadd_vx_i64m2 (vb, 1,
>>> __riscv_vsetvlmax_e64m2 ());
>>> +
>>> + if (b != 0)
>>> + vc = __riscv_vadd_vx_i64m2_mu (mask, vc, vc, 1,
>>> __riscv_vsetvlmax_e64m2 ());
>>> +
>>> + *out = vc;
>>> +}
>>> --
>>> 2.36.3
>>>
>
--
Best,
Lehua
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Fix vsetvl pass ICE
2023-09-18 7:54 ` Lehua Ding
@ 2023-09-18 8:08 ` Kito Cheng
2023-09-18 8:22 ` Lehua Ding
0 siblings, 1 reply; 7+ messages in thread
From: Kito Cheng @ 2023-09-18 8:08 UTC (permalink / raw)
To: Lehua Ding; +Cc: gcc-patches, juzhe.zhong
OK for backport now, steps for backport:
- checkout to releases/gcc-13 branch
- ./contrib/git-backport.py <hash-in-trunk>
- Make sure everything is alright, build-able, no extra regression.
- push releases/gcc-13 branch!
On Mon, Sep 18, 2023 at 3:54 PM Lehua Ding <lehua.ding@rivai.ai> wrote:
>
> Hi Kito,
>
> Can this bugfix be backported to GCC 13 now? If so, how can I do it?
>
> On 2023/8/31 10:12, Lehua Ding wrote:
> > Committed to the trunk and backported to GCC 13 one week later.
> > Thanks Juzhe and Kito.
> >
> > On 2023/8/31 9:44, Kito Cheng via Gcc-patches wrote:
> >> OK for gcc 13 branch too, the general rule for backport is to wait one
> >> week on trunk to make sure the fix is stable.
> >>
> >>
> >> On Thu, Aug 31, 2023 at 8:08 AM juzhe.zhong@rivai.ai
> >> <juzhe.zhong@rivai.ai> wrote:
> >>>
> >>> Ok for trunk. But not sure whether it's ok for GCC-13.
> >>>
> >>>
> >>>
> >>> juzhe.zhong@rivai.ai
> >>>
> >>> From: Lehua Ding
> >>> Date: 2023-08-30 17:51
> >>> To: gcc-patches
> >>> CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
> >>> Subject: [PATCH] RISC-V: Fix vsetvl pass ICE
> >>> This patch fix pr111234 (a vsetvl pass ICE) when fuse a mask any
> >>> vlmax vsetvl_vtype_change_only insn with a mu vsetvl insn.
> >>>
> >>> PR target/111234
> >>>
> >>> gcc/ChangeLog:
> >>>
> >>> * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Remove condition.
> >>>
> >>> gcc/testsuite/ChangeLog:
> >>>
> >>> * gcc.target/riscv/rvv/vsetvl/pr111234.c: New test.
> >>>
> >>> ---
> >>> gcc/config/riscv/riscv-vsetvl.cc | 2 +-
> >>> .../gcc.target/riscv/rvv/vsetvl/pr111234.c | 19 +++++++++++++++++++
> >>> 2 files changed, 20 insertions(+), 1 deletion(-)
> >>> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> >>>
> >>> diff --git a/gcc/config/riscv/riscv-vsetvl.cc
> >>> b/gcc/config/riscv/riscv-vsetvl.cc
> >>> index 1386d9250ca..a81bb53a521 100644
> >>> --- a/gcc/config/riscv/riscv-vsetvl.cc
> >>> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> >>> @@ -655,7 +655,7 @@ gen_vsetvl_pat (rtx_insn *rinsn, const
> >>> vector_insn_info &info,
> >>> new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, vl);
> >>> else
> >>> {
> >>> - if (vsetvl_insn_p (rinsn) || vlmax_avl_p (info.get_avl ()))
> >>> + if (vsetvl_insn_p (rinsn))
> >>> new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, get_vl (rinsn));
> >>> else if (INSN_CODE (rinsn) == CODE_FOR_vsetvl_vtype_change_only)
> >>> new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, new_info, NULL_RTX);
> >>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> >>> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> >>> new file mode 100644
> >>> index 00000000000..ee5eec4a257
> >>> --- /dev/null
> >>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
> >>> @@ -0,0 +1,19 @@
> >>> +/* { dg-do compile } */
> >>> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> >>> +
> >>> +#include <riscv_vector.h>
> >>> +
> >>> +void
> >>> +f (vint32m1_t *in, vint64m2_t *out, vbool32_t *m, int b)
> >>> +{
> >>> + vint32m1_t va = *in;
> >>> + vbool32_t mask = *m;
> >>> + vint64m2_t vb
> >>> + = __riscv_vwadd_vx_i64m2_m (mask, va, 1, __riscv_vsetvlmax_e64m2
> >>> ());
> >>> + vint64m2_t vc = __riscv_vadd_vx_i64m2 (vb, 1,
> >>> __riscv_vsetvlmax_e64m2 ());
> >>> +
> >>> + if (b != 0)
> >>> + vc = __riscv_vadd_vx_i64m2_mu (mask, vc, vc, 1,
> >>> __riscv_vsetvlmax_e64m2 ());
> >>> +
> >>> + *out = vc;
> >>> +}
> >>> --
> >>> 2.36.3
> >>>
> >
>
> --
> Best,
> Lehua
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] RISC-V: Fix vsetvl pass ICE
2023-09-18 8:08 ` Kito Cheng
@ 2023-09-18 8:22 ` Lehua Ding
0 siblings, 0 replies; 7+ messages in thread
From: Lehua Ding @ 2023-09-18 8:22 UTC (permalink / raw)
To: Kito Cheng; +Cc: gcc-patches, juzhe.zhong
Hi Kito,
On 2023/9/18 16:08, Kito Cheng wrote:
> - ./contrib/git-backport.py <hash-in-trunk>
This step fails because of conflicts. So am I should send another patch
based on the GCC 13 code?
--
Best,
Lehua
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-09-18 8:22 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-08-30 9:51 [PATCH] RISC-V: Fix vsetvl pass ICE Lehua Ding
2023-08-31 0:07 ` juzhe.zhong
2023-08-31 1:44 ` Kito Cheng
2023-08-31 2:12 ` Lehua Ding
2023-09-18 7:54 ` Lehua Ding
2023-09-18 8:08 ` Kito Cheng
2023-09-18 8:22 ` Lehua Ding
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