From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13784 invoked by alias); 9 Jan 2013 16:37:15 -0000 Received: (qmail 13683 invoked by uid 22791); 9 Jan 2013 16:37:12 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 09 Jan 2013 16:37:06 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Wed, 09 Jan 2013 16:37:02 +0000 Received: from [10.1.79.66] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Wed, 9 Jan 2013 16:36:59 +0000 Message-ID: <50ED9CAB.7060500@arm.com> Date: Wed, 09 Jan 2013 16:37:00 -0000 From: Tejas Belagod User-Agent: Thunderbird 2.0.0.18 (X11/20081120) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: Marcus Shawcroft Subject: [Patch, AArch64-4.7] Implement support for LD1R. X-MC-Unique: 113010916370200801 Content-Type: multipart/mixed; boundary="------------050901050609090407010006" X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2013-01/txt/msg00494.txt.bz2 This is a multi-part message in MIME format. --------------050901050609090407010006 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 587 Hi, Attached is a patch that implements support for AdvSIMD instruction LD1R. Tested on aarch64-none-elf. OK to commit on aarch64-4.7-branch? Thanks, Tejas Belagod ARM. 2013-01-09 Tejas Belagod gcc/ * config/aarch64/aarch64-simd.md (*aarch64_simd_ld1r): New. * config/aarch64/iterators.md (VALLDI): New. testsuite/ * gcc.target/aarch64/aarch64/vect-ld1r-compile-fp.c: New. * gcc.target/aarch64/vect-ld1r-compile.c: New. * gcc.target/aarch64/vect-ld1r-fp.c: New. * gcc.target/aarch64/vect-ld1r.c: New. * gcc.target/aarch64/vect-ld1r.x: New.= --------------050901050609090407010006 Content-Type: text/plain; name=ld1r-1.txt Content-Transfer-Encoding: quoted-printable Content-Disposition: inline; filename="ld1r-1.txt" Content-length: 5637 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch6= 4-simd.md index 98511cb..0b83866 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3417,3 +3417,11 @@ DONE; }) =20 +(define_insn "*aarch64_simd_ld1r" + [(set (match_operand:VALLDI 0 "register_operand" "=3Dw") + (vec_duplicate:VALLDI + (match_operand: 1 "aarch64_simd_struct_operand" "Utv")))] + "TARGET_SIMD" + "ld1r\\t{%0.}, %1" + [(set_attr "simd_type" "simd_load1r") + (set_attr "simd_mode" "")]) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators= .md index 7a1cdc8..1ad3334 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -89,6 +89,9 @@ ;; All modes. (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF = V2DF]) =20 +;; All vector modes and DI. +(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4S= F V2DF DI]) + ;; Vector modes for Integer reduction across lanes. (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI]) =20 diff --git a/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c b/gcc/= testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c new file mode 100644 index 0000000..257ec21 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +#include "stdint.h" +#include "vect-ld1r.x" + +DEF (float) +DEF (double) + +/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4s"} } */ +/* { dg-final { scan-assembler "ldr\\t\d\[0-9\]+"} } */ +/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.2d"} } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c b/gcc/tes= tsuite/gcc.target/aarch64/vect-ld1r-compile.c new file mode 100644 index 0000000..9cc54fe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +#include "stdint.h" +#include "vect-ld1r.x" + +DEF (int8_t) +DEF (int16_t) +DEF (int32_t) +DEF (int64_t) + +/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.8b"} } */ +/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.16b"} } */ +/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4h"} } */ +/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.8h"} } */ +/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4s"} } */ +/* { dg-final { scan-assembler "ldr\\t\x\[0-9\]+"} } */ +/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.2d"} } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-ld1r-fp.c b/gcc/testsuit= e/gcc.target/aarch64/vect-ld1r-fp.c new file mode 100644 index 0000000..5e384e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-ld1r-fp.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O3" } */ + +extern void abort (void); + +#include "stdint.h" +#include "vect-ld1r.x" + +DEF (float) +DEF (double) + +#define FOOD(TYPE) \ + foo_ ## TYPE ## _d (&a_ ## TYPE, output_ ## TYPE) + +#define FOOQ(TYPE) \ + foo_ ## TYPE ## _q (&a_ ## TYPE, output_ ## TYPE) + +#define CHECKD(TYPE) \ + for (i =3D 0; i < 8 / sizeof (TYPE); i++) \ + if (output_ ## TYPE[i] !=3D a_ ## TYPE) \ + abort () + +#define CHECKQ(TYPE) \ + for (i =3D 0; i < 32 / sizeof (TYPE); i++) \ + if (output_ ## TYPE[i] !=3D a_ ## TYPE) \ + abort () + +#define DECL(TYPE) \ + TYPE output_ ## TYPE[32]; \ + TYPE a_ ## TYPE =3D (TYPE)12.2 + +int +main (void) +{ + + DECL(float); + DECL(double); + int i; + + FOOD (float); + CHECKD (float); + FOOQ (float); + CHECKQ (float); + + FOOD (double); + CHECKD (double); + FOOQ (double); + CHECKQ (double); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/vect-ld1r.c b/gcc/testsuite/g= cc.target/aarch64/vect-ld1r.c new file mode 100644 index 0000000..f0571de --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-ld1r.c @@ -0,0 +1,65 @@ +/* { dg-do run } */ +/* { dg-options "-O3" } */ + +extern void abort (void); + +#include "stdint.h" +#include "vect-ld1r.x" + +DEF (int8_t) +DEF (int16_t) +DEF (int32_t) +DEF (int64_t) + +#define FOOD(TYPE) \ + foo_ ## TYPE ## _d (&a_ ## TYPE, output_ ## TYPE) + +#define FOOQ(TYPE) \ + foo_ ## TYPE ## _q (&a_ ## TYPE, output_ ## TYPE) + +#define CHECKD(TYPE) \ + for (i =3D 0; i < 8 / sizeof (TYPE); i++) \ + if (output_ ## TYPE[i] !=3D a_ ## TYPE) \ + abort () + +#define CHECKQ(TYPE) \ + for (i =3D 0; i < 32 / sizeof (TYPE); i++) \ + if (output_ ## TYPE[i] !=3D a_ ## TYPE) \ + abort () + +#define DECL(TYPE) \ + TYPE output_ ## TYPE[32]; \ + TYPE a_ ## TYPE =3D (TYPE)12 + +int +main (void) +{ + + DECL(int8_t); + DECL(int16_t); + DECL(int32_t); + DECL(int64_t); + int i; + + FOOD (int8_t); + CHECKD (int8_t); + FOOQ (int8_t); + CHECKQ (int8_t); + + FOOD (int16_t); + CHECKD (int16_t); + FOOQ (int16_t); + CHECKQ (int16_t); + + FOOD (int32_t); + CHECKD (int32_t); + FOOQ (int32_t); + CHECKQ (int32_t); + + FOOD (int64_t); + CHECKD (int64_t); + FOOQ (int64_t); + CHECKQ (int64_t); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/vect-ld1r.x b/gcc/testsuite/g= cc.target/aarch64/vect-ld1r.x new file mode 100644 index 0000000..680ce43 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-ld1r.x @@ -0,0 +1,15 @@ + +#define DEF(TYPE) \ + void \ + foo_ ## TYPE ## _d (TYPE *a, TYPE *output) \ + { \ + int i; \ + for (i =3D 0; i < 8 / sizeof (TYPE); i++) \ + output[i] =3D *a; \ + } \ + foo_ ## TYPE ## _q (TYPE *a, TYPE *output) \ + { \ + int i; \ + for (i =3D 0; i < 32 / sizeof (TYPE); i++) \ + output[i] =3D *a; \ + }= --------------050901050609090407010006--