* [Patch, AArch64-4.7] Implement support for LD1R.
@ 2013-01-09 16:37 Tejas Belagod
2013-01-14 13:53 ` [PING][Patch, " Tejas Belagod
2013-01-14 17:09 ` [Patch, " Marcus Shawcroft
0 siblings, 2 replies; 3+ messages in thread
From: Tejas Belagod @ 2013-01-09 16:37 UTC (permalink / raw)
To: gcc-patches; +Cc: Marcus Shawcroft
[-- Attachment #1: Type: text/plain, Size: 607 bytes --]
Hi,
Attached is a patch that implements support for AdvSIMD instruction LD1R.
Tested on aarch64-none-elf. OK to commit on aarch64-4.7-branch?
Thanks,
Tejas Belagod
ARM.
2013-01-09 Tejas Belagod <tejas.belagod@arm.com>
gcc/
* config/aarch64/aarch64-simd.md (*aarch64_simd_ld1r<mode>): New.
* config/aarch64/iterators.md (VALLDI): New.
testsuite/
* gcc.target/aarch64/aarch64/vect-ld1r-compile-fp.c: New.
* gcc.target/aarch64/vect-ld1r-compile.c: New.
* gcc.target/aarch64/vect-ld1r-fp.c: New.
* gcc.target/aarch64/vect-ld1r.c: New.
* gcc.target/aarch64/vect-ld1r.x: New.
[-- Attachment #2: ld1r-1.txt --]
[-- Type: text/plain, Size: 5802 bytes --]
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 98511cb..0b83866 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3417,3 +3417,11 @@
DONE;
})
+(define_insn "*aarch64_simd_ld1r<mode>"
+ [(set (match_operand:VALLDI 0 "register_operand" "=w")
+ (vec_duplicate:VALLDI
+ (match_operand:<VEL> 1 "aarch64_simd_struct_operand" "Utv")))]
+ "TARGET_SIMD"
+ "ld1r\\t{%0.<Vtype>}, %1"
+ [(set_attr "simd_type" "simd_load1r")
+ (set_attr "simd_mode" "<MODE>")])
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 7a1cdc8..1ad3334 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -89,6 +89,9 @@
;; All modes.
(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
+;; All vector modes and DI.
+(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
+
;; Vector modes for Integer reduction across lanes.
(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI])
diff --git a/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c b/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c
new file mode 100644
index 0000000..257ec21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include "stdint.h"
+#include "vect-ld1r.x"
+
+DEF (float)
+DEF (double)
+
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "ldr\\t\d\[0-9\]+"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.2d"} } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c b/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c
new file mode 100644
index 0000000..9cc54fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include "stdint.h"
+#include "vect-ld1r.x"
+
+DEF (int8_t)
+DEF (int16_t)
+DEF (int32_t)
+DEF (int64_t)
+
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.8b"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.16b"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4h"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "ldr\\t\x\[0-9\]+"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.2d"} } */
diff --git a/gcc/testsuite/gcc.target/aarch64/vect-ld1r-fp.c b/gcc/testsuite/gcc.target/aarch64/vect-ld1r-fp.c
new file mode 100644
index 0000000..5e384e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vect-ld1r-fp.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+extern void abort (void);
+
+#include "stdint.h"
+#include "vect-ld1r.x"
+
+DEF (float)
+DEF (double)
+
+#define FOOD(TYPE) \
+ foo_ ## TYPE ## _d (&a_ ## TYPE, output_ ## TYPE)
+
+#define FOOQ(TYPE) \
+ foo_ ## TYPE ## _q (&a_ ## TYPE, output_ ## TYPE)
+
+#define CHECKD(TYPE) \
+ for (i = 0; i < 8 / sizeof (TYPE); i++) \
+ if (output_ ## TYPE[i] != a_ ## TYPE) \
+ abort ()
+
+#define CHECKQ(TYPE) \
+ for (i = 0; i < 32 / sizeof (TYPE); i++) \
+ if (output_ ## TYPE[i] != a_ ## TYPE) \
+ abort ()
+
+#define DECL(TYPE) \
+ TYPE output_ ## TYPE[32]; \
+ TYPE a_ ## TYPE = (TYPE)12.2
+
+int
+main (void)
+{
+
+ DECL(float);
+ DECL(double);
+ int i;
+
+ FOOD (float);
+ CHECKD (float);
+ FOOQ (float);
+ CHECKQ (float);
+
+ FOOD (double);
+ CHECKD (double);
+ FOOQ (double);
+ CHECKQ (double);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/vect-ld1r.c b/gcc/testsuite/gcc.target/aarch64/vect-ld1r.c
new file mode 100644
index 0000000..f0571de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vect-ld1r.c
@@ -0,0 +1,65 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+extern void abort (void);
+
+#include "stdint.h"
+#include "vect-ld1r.x"
+
+DEF (int8_t)
+DEF (int16_t)
+DEF (int32_t)
+DEF (int64_t)
+
+#define FOOD(TYPE) \
+ foo_ ## TYPE ## _d (&a_ ## TYPE, output_ ## TYPE)
+
+#define FOOQ(TYPE) \
+ foo_ ## TYPE ## _q (&a_ ## TYPE, output_ ## TYPE)
+
+#define CHECKD(TYPE) \
+ for (i = 0; i < 8 / sizeof (TYPE); i++) \
+ if (output_ ## TYPE[i] != a_ ## TYPE) \
+ abort ()
+
+#define CHECKQ(TYPE) \
+ for (i = 0; i < 32 / sizeof (TYPE); i++) \
+ if (output_ ## TYPE[i] != a_ ## TYPE) \
+ abort ()
+
+#define DECL(TYPE) \
+ TYPE output_ ## TYPE[32]; \
+ TYPE a_ ## TYPE = (TYPE)12
+
+int
+main (void)
+{
+
+ DECL(int8_t);
+ DECL(int16_t);
+ DECL(int32_t);
+ DECL(int64_t);
+ int i;
+
+ FOOD (int8_t);
+ CHECKD (int8_t);
+ FOOQ (int8_t);
+ CHECKQ (int8_t);
+
+ FOOD (int16_t);
+ CHECKD (int16_t);
+ FOOQ (int16_t);
+ CHECKQ (int16_t);
+
+ FOOD (int32_t);
+ CHECKD (int32_t);
+ FOOQ (int32_t);
+ CHECKQ (int32_t);
+
+ FOOD (int64_t);
+ CHECKD (int64_t);
+ FOOQ (int64_t);
+ CHECKQ (int64_t);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/vect-ld1r.x b/gcc/testsuite/gcc.target/aarch64/vect-ld1r.x
new file mode 100644
index 0000000..680ce43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vect-ld1r.x
@@ -0,0 +1,15 @@
+
+#define DEF(TYPE) \
+ void \
+ foo_ ## TYPE ## _d (TYPE *a, TYPE *output) \
+ { \
+ int i; \
+ for (i = 0; i < 8 / sizeof (TYPE); i++) \
+ output[i] = *a; \
+ } \
+ foo_ ## TYPE ## _q (TYPE *a, TYPE *output) \
+ { \
+ int i; \
+ for (i = 0; i < 32 / sizeof (TYPE); i++) \
+ output[i] = *a; \
+ }
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PING][Patch, AArch64-4.7] Implement support for LD1R.
2013-01-09 16:37 [Patch, AArch64-4.7] Implement support for LD1R Tejas Belagod
@ 2013-01-14 13:53 ` Tejas Belagod
2013-01-14 17:09 ` [Patch, " Marcus Shawcroft
1 sibling, 0 replies; 3+ messages in thread
From: Tejas Belagod @ 2013-01-14 13:53 UTC (permalink / raw)
To: Marcus Shawcroft; +Cc: gcc-patches
PING.
Tejas Belagod wrote:
> Hi,
>
> Attached is a patch that implements support for AdvSIMD instruction LD1R.
>
> Tested on aarch64-none-elf. OK to commit on aarch64-4.7-branch?
>
> Thanks,
> Tejas Belagod
> ARM.
>
> 2013-01-09 Tejas Belagod <tejas.belagod@arm.com>
>
> gcc/
> * config/aarch64/aarch64-simd.md (*aarch64_simd_ld1r<mode>): New.
> * config/aarch64/iterators.md (VALLDI): New.
>
> testsuite/
> * gcc.target/aarch64/aarch64/vect-ld1r-compile-fp.c: New.
> * gcc.target/aarch64/vect-ld1r-compile.c: New.
> * gcc.target/aarch64/vect-ld1r-fp.c: New.
> * gcc.target/aarch64/vect-ld1r.c: New.
> * gcc.target/aarch64/vect-ld1r.x: New.
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Patch, AArch64-4.7] Implement support for LD1R.
2013-01-09 16:37 [Patch, AArch64-4.7] Implement support for LD1R Tejas Belagod
2013-01-14 13:53 ` [PING][Patch, " Tejas Belagod
@ 2013-01-14 17:09 ` Marcus Shawcroft
1 sibling, 0 replies; 3+ messages in thread
From: Marcus Shawcroft @ 2013-01-14 17:09 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
On 09/01/13 16:36, Tejas Belagod wrote:
>
> Hi,
>
> Attached is a patch that implements support for AdvSIMD instruction LD1R.
>
> Tested on aarch64-none-elf. OK to commit on aarch64-4.7-branch?
>
> Thanks,
> Tejas Belagod
> ARM.
>
> 2013-01-09 Tejas Belagod <tejas.belagod@arm.com>
>
> gcc/
> * config/aarch64/aarch64-simd.md (*aarch64_simd_ld1r<mode>): New.
> * config/aarch64/iterators.md (VALLDI): New.
>
> testsuite/
> * gcc.target/aarch64/aarch64/vect-ld1r-compile-fp.c: New.
> * gcc.target/aarch64/vect-ld1r-compile.c: New.
> * gcc.target/aarch64/vect-ld1r-fp.c: New.
> * gcc.target/aarch64/vect-ld1r.c: New.
> * gcc.target/aarch64/vect-ld1r.x: New.
>
OK
^ permalink raw reply [flat|nested] 3+ messages in thread
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2013-01-09 16:37 [Patch, AArch64-4.7] Implement support for LD1R Tejas Belagod
2013-01-14 13:53 ` [PING][Patch, " Tejas Belagod
2013-01-14 17:09 ` [Patch, " Marcus Shawcroft
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