Hi,

Attached is a patch that fixes sq<r>dmulh<q>_lane_* intrinsics. Previously they,
used to accept 128-bit lane index range. This fixes this bug to accept 64-bit 
lane index range. sq<r>dmulh<q>_laneq_* and AdvSIMD scalar ones still accept 
128-bit lane index range as before.

It has passed regressions on aarch64-none-elf. OK for trunk and aarch64-4.7-branch?

Thanks,
Tejas Belagod
ARM.

Changelog

2013-01-14  Tejas Belagod  <tejas.belagod@arm.com>

gcc/
	* config/aarch64/aarch64-simd-builtins.def: Separate sq<r>dmulh_lane
	entries into lane and laneq entries.
	* config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh_lane<mode>): Remove
	AdvSIMD scalar modes.
	(aarch64_sq<r>dmulh_laneq<mode>): New.
	(aarch64_sq<r>dmulh_lane<mode>): New RTL pattern for Scalar AdvSIMD
	modes.
	* config/aarch64/arm_neon.h: Fix all the vq<r>dmulh_lane* intrinsics'
	builtin implementations to relfect changes in RTL in aarch64-simd.md.
	* config/aarch64/iterators.md (VCOND): New.
	(VCONQ): New.