From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15828 invoked by alias); 18 Jan 2013 14:28:37 -0000 Received: (qmail 15817 invoked by uid 22791); 18 Jan 2013 14:28:34 -0000 X-SWARE-Spam-Status: No, hits=-3.3 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,KHOP_THREADED,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 18 Jan 2013 14:28:27 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 18 Jan 2013 14:28:24 +0000 Received: from [10.1.69.70] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Fri, 18 Jan 2013 14:28:19 +0000 Message-ID: <50F95BFB.1060808@arm.com> Date: Fri, 18 Jan 2013 14:28:00 -0000 From: Ramana Radhakrishnan Reply-To: ramrad01@arm.com User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:14.0) Gecko/20120713 Thunderbird/14.0 MIME-Version: 1.0 To: ahsu@marvell.com CC: "gcc-patches@gcc.gnu.org ;" Subject: Re: RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores References: <689C75E0D210324F8BE88961219F681624B5949520@SC-VEXCH2.marvell.com> <689C75E0D210324F8BE88961219F681624B5BCD276@SC-VEXCH2.marvell.com> In-Reply-To: <689C75E0D210324F8BE88961219F681624B5BCD276@SC-VEXCH2.marvell.com> X-MC-Unique: 113011814282406001 Content-Type: multipart/mixed; boundary="------------000908030407010003070806" X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2013-01/txt/msg00962.txt.bz2 This is a multi-part message in MIME format. --------------000908030407010003070806 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 2699 On 06/20/12 03:53, Yi-Hsiu Hsu wrote: > marvell-pj4 is added to BE8_LINK_SPEC. Sorry about the time it's taken to finish this patch up. I seem to have=20 missed this one in the review process. I've now applied the attached patch after taking into account the recent=20 attribute changes and treated alu_reg and simple_alu_imm as you have=20 treated alu, rebased to trunk to fix up some small issues with=20 BE8_LINK_SPECS. Additionally I've removed tune_marvell as that seems redundant at this=20 point of time - an additional attribute and testing that appears to be=20 unnecessary instead of just one more inequality test. The only part I'm not sure about is how to treat the simple_alu_shift=20 category here , so a patch to handle them in the pj4 pipeline=20 description would be welcome. Thanks Ramana 2013-01-18 Yi-Hsiu Hsu Ramana Radhakrishnan * config/arm/marvell-pj4.md: New file. * config/arm/arm.c (arm_issue_rate): Add marvell_pj4. * config/arm/arm.md (generic_sched): Add marvell_pj4. (generic_vfp): Likewise. * config/arm/arm-cores.def: Add marvell-pj4. * config/arm/arm-tune.md: Regenerate. * config/arm/arm-tables.opt: Regenerate. * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell_pj4. * doc/invoke.texi: Document marvell-pj4. > > Modified patch is attached. > > Thanks! > > B.R. > Yi-Hsiu, Hsu > > -----Original Message----- > From: Ramana Radhakrishnan [mailto:ramana.radhakrishnan@linaro.org] > Sent: Thursday, June 14, 2012 2:19 AM > To: Yi-Hsiu Hsu > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores > > On 29 May 2012 10:07, Yi-Hsiu Hsu wrote: >> Hi, >> >> This patch maintains Marvell PJ4 cores pipeline description. >> Run arm testsuite on arm-linux-gnueabi and no extra regressions are foun= d. >> >> * config/arm/marvell-pj4.md: New marvell-pj4 pipeline descriptio= n. >> * config/arm/arm.c (arm_issue_rate): Add marvell_pj4. >> * config/arm/arm-cores.def: Add core marvell-pj4. >> * config/arm/arm-tune.md: Regenerated. >> * config/arm/arm-tables.opt: Regenerated. >> * doc/invoke.texi: Added entry for marvell-pj4. > > This command line option should also be added to BE8_LINK_SPEC similar > to what's done for the other v7-a cores. > > Ok with that change. > > regards, > Ramana > > > >> >> >> Thanks! >> >> P.S. I create the patch from revision 187308, but this revision is unabl= e to build successfully, then I apply this patch to revision 187623 and suc= cessfully build and pass the testsuite. >> --------------000908030407010003070806 Content-Type: text/plain; charset=WINDOWS-1252; name=p1 Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="p1" Content-length: 14630 commit faf5471d7d4616ad19d6bbae2c41e382ae506110 Author: Ramana Radhakrishnan Date: Fri Jan 18 14:12:19 2013 +0000 Apply tuning for marvell-pj4 diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 0cd8714..a4cb7c6 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -137,3 +137,4 @@ ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, c= ortex) ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, v6m) ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, v6m) ARM_CORE("cortex-m0plus", cortexm0plus, 6M, FL_LDSCHED, v6m) +ARM_CORE("marvell-pj4", marvell_pj4, 7A, F= L_LDSCHED, 9e) diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 6d0af59..06a529d 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -273,6 +273,9 @@ Enum(processor_type) String(cortex-m0) Value(cortexm0) EnumValue Enum(processor_type) String(cortex-m0plus) Value(cortexm0plus) =20 +EnumValue +Enum(processor_type) String(marvell-pj4) Value(marvell_pj4) + Enum Name(arm_arch) Type(int) Known ARM architectures (for use with the -march=3D option): diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 040587a..26c2e1f 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from arm-cores.def (define_attr "tune" - "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70= ,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7d= m,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa= 526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,a= rm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,ar= m968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp62= 6,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,= mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cort= exa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,corte= xm1,cortexm0,cortexm0plus" + "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70= ,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7d= m,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa= 526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,a= rm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,ar= m968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp62= 6,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,= mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cort= exa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,corte= xm1,cortexm0,cortexm0plus,marvell_pj4" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 3bf7397..9d3981d 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -25644,6 +25644,7 @@ arm_issue_rate (void) case cortexa8: case cortexa9: case fa726te: + case marvell_pj4: return 2; =20 default: diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index c7b30eb..22f2218 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -500,7 +500,7 @@ =20 (define_attr "generic_sched" "yes,no" (const (if_then_else - (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te= ,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa7,corte= xa8,cortexa9,cortexa15,cortexm4") + (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te= ,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa7,corte= xa8,cortexa9,cortexa15,cortexm4,marvell_pj4") (eq_attr "tune_cortexr4" "yes")) (const_string "no") (const_string "yes")))) @@ -508,7 +508,7 @@ (define_attr "generic_vfp" "yes,no" (const (if_then_else (and (eq_attr "fpu" "vfp") - (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,cortexa8,cor= texa9,cortexm4") + (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,cortexa8,cor= texa9,cortexm4,marvell_pj4") (eq_attr "tune_cortexr4" "no")) (const_string "yes") (const_string "no")))) @@ -534,6 +534,7 @@ (include "cortex-m4.md") (include "cortex-m4-fpu.md") (include "vfp11.md") +(include "marvell-pj4.md") =20 =0C ;;------------------------------------------------------------------------= --- diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index eaf2cbb..bee429f 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -59,6 +59,7 @@ " %{!mlittle-endian:%{march=3Darmv7-a|mcpu=3Dcortex-a5 \ |mcpu=3Dcortex-a7 \ |mcpu=3Dcortex-a8|mcpu=3Dcortex-a9|mcpu=3Dcortex-a15 \ + |mcpu=3Dmarvell-pj4 \ |mcpu=3Dgeneric-armv7-a \ |march=3Darmv7-m|mcpu=3Dcortex-m3 \ |march=3Darmv7e-m|mcpu=3Dcortex-m4 \ @@ -70,6 +71,7 @@ " %{mbig-endian:%{march=3Darmv7-a|mcpu=3Dcortex-a5 \ |mcpu=3Dcortex-a7 \ |mcpu=3Dcortex-a8|mcpu=3Dcortex-a9|mcpu=3Dcortex-a15 \ + |mcpu=3Dmarvell-pj4 \ |mcpu=3Dgeneric-armv7-a \ |march=3Darmv7-m|mcpu=3Dcortex-m3 \ |march=3Darmv7e-m|mcpu=3Dcortex-m4 \ diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md new file mode 100644 index 0000000..8df47d3 --- /dev/null +++ b/gcc/config/arm/marvell-pj4.md @@ -0,0 +1,205 @@ +;; Marvell ARM Processor Pipeline Description +;; Copyright (C) 2010, 2011, 2012 Free Software Foundation, Inc. +;; Contributed by Marvell. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Pipeline description for the Marvell PJ4, aka "Flareon". +(define_automaton "pj4") + +;; Issue resources +(define_cpu_unit "pj4_is1,pj4_is2" "pj4") +(define_reservation "pj4_is" "(pj4_is1|pj4_is2)") +(define_reservation "pj4_isb" "(pj4_is1+pj4_is2)") + +;; Functional units +(define_cpu_unit "pj4_alu1,pj4_alu2,pj4_mul,pj4_div" "pj4") + +;; Completion ports +(define_cpu_unit "pj4_w1,pj4_w2" "pj4") + +;; Complete/Retire control +(define_cpu_unit "pj4_c1,pj4_c2" "pj4") +(define_reservation "pj4_cp" "(pj4_c1|pj4_c2)") +(define_reservation "pj4_cpb" "(pj4_c1+pj4_c2)") + +;; Integer arithmetic instructions + +(define_insn_reservation "pj4_alu_e1" 1 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "alu_reg,simple_alu_imm") + (not (eq_attr "conds" "set")) + (eq_attr "insn" "mov,mvn")) + "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,= pj4_w2+pj4_cp)") + +(define_insn_reservation "pj4_alu_e1_conds" 4 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "alu_reg,simple_alu_imm") + (eq_attr "conds" "set") + (eq_attr "insn" "mov,mvn")) + "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,= pj4_w2+pj4_cp)") + +(define_insn_reservation "pj4_alu" 1 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "alu_reg,simple_alu_imm") + (not (eq_attr "conds" "set")) + (not (eq_attr "insn" "mov,mvn"))) + "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,= pj4_w2+pj4_cp)") + +(define_insn_reservation "pj4_alu_conds" 4 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "alu_reg,simple_alu_imm") + (eq_attr "conds" "set") + (not (eq_attr "insn" "mov,mvn"))) + "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,= pj4_w2+pj4_cp)") + +(define_insn_reservation "pj4_shift" 1 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "alu_shift,alu_shift_reg") + (not (eq_attr "conds" "set")) + (eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,= pj4_w2+pj4_cp)") + +(define_insn_reservation "pj4_shift_conds" 4 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "alu_shift,alu_shift_reg") + (eq_attr "conds" "set") + (eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,= pj4_w2+pj4_cp)") + +(define_insn_reservation "pj4_alu_shift" 1 + (and (eq_attr "tune" "marvell_pj4") + (not (eq_attr "conds" "set")) + (eq_attr "type" "alu_shift,alu_shift_reg")) + "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(p= j4_alu2,nothing,pj4_w2+pj4_cp)") + +(define_insn_reservation "pj4_alu_shift_conds" 4 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "conds" "set") + (eq_attr "type" "alu_shift,alu_shift_reg")) + "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(p= j4_alu2,nothing,pj4_w2+pj4_cp)") + +(define_bypass 2 "pj4_alu_shift,pj4_shift" + "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp") + +(define_insn_reservation "pj4_ir_mul" 3 + (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "mult")) "pj4_is,pj4= _mul,nothing*2,pj4_cp") + +(define_insn_reservation "pj4_ir_div" 20 + (and (eq_attr "tune" "marvell_pj4") (eq_attr "insn" "udiv,sdiv")) "pj4_i= s,pj4_div*19,pj4_cp") + +;; Branches and calls. + +(define_insn_reservation "pj4_branches" 0 + (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "branch")) "pj4_is") + +(define_insn_reservation "pj4_calls" 32 + (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "call")) "pj4_is") + +;; Load/store instructions + +(define_insn_reservation "pj4_ldr" 3 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "load_byte,load1")) + "pj4_is,pj4_alu1,nothing*2,pj4_cp") + +(define_insn_reservation "pj4_ldrd" 3 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "load2")) + "pj4_is,pj4_alu1,nothing*2,pj4_cpb") + +(define_insn_reservation "pj4_str" 1 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "store1")) + "pj4_is,pj4_alu1,nothing*2,pj4_cp") + +(define_insn_reservation "pj4_strd" 1 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "store2")) + "pj4_is,pj4_alu1,nothing*2,pj4_cpb") + +(define_insn_reservation "pj4_ldm" 4 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "load3,load4")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,= nothing,pj4_cp,pj4_cp") + +(define_insn_reservation "pj4_stm" 2 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "store3,store4")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu= 1,nothing,pj4_cp,pj4_cp") + +;; Loads forward at WR-stage to ALU pipes +(define_bypass 2 "pj4_ldr,pj4_ldrd" "pj4_alu") +(define_bypass 2 "pj4_ldr,pj4_ldrd" "pj4_alu_shift" "arm_no_early_alu_shif= t_dep") + +(define_bypass 4 "pj4_ldr,pj4_ldrd" "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp= ") +(define_bypass 5 "pj4_ldm" "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp") + +;; Loads to stores can back-to-back forward +(define_bypass 1 "pj4_ldr,pj4_ldrd" "pj4_str,pj4_strd" "arm_no_early_store= _addr_dep") + +;; PJ4 VFP floating point unit +(define_automaton "pj4_vfp") + +(define_cpu_unit "vissue" "pj4_vfp") +(define_cpu_unit "vadd" "pj4_vfp") +(define_cpu_unit "vmul" "pj4_vfp") +(define_cpu_unit "vdiv" "pj4_vfp") +(define_cpu_unit "vfast" "pj4_vfp") + +(define_insn_reservation "pj4_vfp_add" 5 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "fadds,faddd")) "pj4_is,nothing*2,vissue,vadd,nothi= ng*3") + +(define_insn_reservation "pj4_vfp_mul" 6 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "fmuls,fmuld")) "pj4_is,nothing*2,vissue,vmul,nothi= ng*4") + +(define_insn_reservation "pj4_vfp_divs" 20 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "fdivs")) "pj4_is,nothing*2,vissue,vdiv*18,no= thing") + +(define_insn_reservation "pj4_vfp_divd" 34 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "fdivd")) "pj4_is,nothing*2,vissue,vdiv*32,no= thing") + +(define_insn_reservation "pj4_vfp_mac" 9 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "fmacs,fmacd")) + "pj4_is,nothing*2,vissue,vmul,nothing*3,vadd,nothin= g*3") + +(define_bypass 5 "pj4_vfp_mac" "pj4_vfp_mac" "arm_no_early_mul_dep") + +(define_insn_reservation "pj4_vfp_cpy" 4 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,\ + fcmps,fcmpd,f_cvt")) "pj4_is,nothing*2,vissue,vfa= st,nothing*2") + +;; Enlarge latency, and wish that more nondependent insns are +;; scheduled immediately after VFP load. +(define_insn_reservation "pj4_vfp_load" 4 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "f_loads,f_loadd")) "pj4_isb,pj4_alu1,nothing,vi= ssue,pj4_cp") + +(define_insn_reservation "pj4_vfp_store" 1 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "f_stores,f_stored")) "pj4_isb,pj4_alu1,nothing,vi= ssue,pj4_cp") + +(define_insn_reservation "pj4_vfp_to_core" 7 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "f_2_r,f_flag")) "pj4_isb,nothing,nothing,vis= sue,vfast,nothing*2") + +(define_insn_reservation "pj4_core_to_vfp" 2 + (and (eq_attr "tune" "marvell_pj4") + (eq_attr "type" "r_2_f")) "pj4_isb,pj4_alu1,pj4_w1,vis= sue,pj4_cp") + diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9ef6c93..887d31e 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -11242,6 +11242,7 @@ assembly code. Permissible names are: @samp{arm2},= @samp{arm250}, @samp{cortex-m1}, @samp{cortex-m0}, @samp{cortex-m0plus}, +@samp{marvell-pj4}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626}, @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}.= --------------000908030407010003070806--