[PATCH, ARM] New CPU support for Marvell PJ4 cores

[PATCH, ARM] New CPU support for Marvell PJ4 cores

[Yi-Hsiu Hsu]

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Hi,

This patch maintains Marvell PJ4 cores pipeline description.
Run arm testsuite on arm-linux-gnueabi and no extra regressions are found.

        * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
        * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
        * config/arm/arm-cores.def: Add core marvell-pj4.
        * config/arm/arm-tune.md: Regenerated.
        * config/arm/arm-tables.opt: Regenerated.
        * doc/invoke.texi: Added entry for marvell-pj4.


Thanks!

P.S. I create the patch from revision 187308, but this revision is unable to build successfully, then I apply this patch to revision 187623 and successfully build and pass the testsuite.


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Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Ramana Radhakrishnan]

On 29 May 2012 10:07, Yi-Hsiu Hsu <ahsu@marvell.com> wrote:
> Hi,
>
> This patch maintains Marvell PJ4 cores pipeline description.
> Run arm testsuite on arm-linux-gnueabi and no extra regressions are found.
>
>        * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
>        * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>        * config/arm/arm-cores.def: Add core marvell-pj4.
>        * config/arm/arm-tune.md: Regenerated.
>        * config/arm/arm-tables.opt: Regenerated.
>        * doc/invoke.texi: Added entry for marvell-pj4.

This command line option should also be added to BE8_LINK_SPEC similar
to what's done for the other v7-a cores.

Ok with that change.

regards,
Ramana



>
>
> Thanks!
>
> P.S. I create the patch from revision 187308, but this revision is unable to build successfully, then I apply this patch to revision 187623 and successfully build and pass the testsuite.
>

Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Chung-Lin Tang]

On 2012/6/14 02:18 AM, Ramana Radhakrishnan wrote:
> On 29 May 2012 10:07, Yi-Hsiu Hsu <ahsu@marvell.com> wrote:
>> Hi,
>>
>> This patch maintains Marvell PJ4 cores pipeline description.
>> Run arm testsuite on arm-linux-gnueabi and no extra regressions are found.
>>
>>        * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
>>        * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>>        * config/arm/arm-cores.def: Add core marvell-pj4.
>>        * config/arm/arm-tune.md: Regenerated.
>>        * config/arm/arm-tables.opt: Regenerated.
>>        * doc/invoke.texi: Added entry for marvell-pj4.
> 
> This command line option should also be added to BE8_LINK_SPEC similar
> to what's done for the other v7-a cores.
> 
> Ok with that change.

I take the blame for not doing this back then, but I suggest the
resource names be properly qualified, similar to most recently added
pipeline descriptions, e.g. prepend resource/reservation names with
"pj4_"  ("is" to "pj4_is", etc.)

Chung-Lin

RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Yi-Hsiu Hsu]

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marvell-pj4 is added to BE8_LINK_SPEC.

Modified patch is attached.

Thanks!

B.R.
Yi-Hsiu, Hsu

-----Original Message-----
From: Ramana Radhakrishnan [mailto:ramana.radhakrishnan@linaro.org] 
Sent: Thursday, June 14, 2012 2:19 AM
To: Yi-Hsiu Hsu
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores

On 29 May 2012 10:07, Yi-Hsiu Hsu <ahsu@marvell.com> wrote:
> Hi,
>
> This patch maintains Marvell PJ4 cores pipeline description.
> Run arm testsuite on arm-linux-gnueabi and no extra regressions are found.
>
>        * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
>        * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>        * config/arm/arm-cores.def: Add core marvell-pj4.
>        * config/arm/arm-tune.md: Regenerated.
>        * config/arm/arm-tables.opt: Regenerated.
>        * doc/invoke.texi: Added entry for marvell-pj4.

This command line option should also be added to BE8_LINK_SPEC similar
to what's done for the other v7-a cores.

Ok with that change.

regards,
Ramana



>
>
> Thanks!
>
> P.S. I create the patch from revision 187308, but this revision is unable to build successfully, then I apply this patch to revision 187623 and successfully build and pass the testsuite.
>

[-- Attachment #2: marvell-pj4-core.patch --]
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Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi	(revision 187623)
+++ gcc/doc/invoke.texi	(working copy)
@@ -10760,6 +10760,7 @@ assembly code.  Permissible names are: @samp{arm2}
 @samp{cortex-m1},
 @samp{cortex-m0},
 @samp{cortex-m0plus},
+@samp{marvell-pj4},
 @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
 @samp{fa526}, @samp{fa626},
 @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}.
Index: gcc/config/arm/arm-tables.opt
===================================================================
--- gcc/config/arm/arm-tables.opt	(revision 187623)
+++ gcc/config/arm/arm-tables.opt	(working copy)
@@ -273,6 +273,9 @@ Enum(processor_type) String(cortex-m0) Value(corte
 EnumValue
 Enum(processor_type) String(cortex-m0plus) Value(cortexm0plus)
 
+EnumValue
+Enum(processor_type) String(marvell-pj4) Value(marvell_pj4)
+
 Enum
 Name(arm_arch) Type(int)
 Known ARM architectures (for use with the -march= option):
Index: gcc/config/arm/marvell-pj4.md
===================================================================
--- gcc/config/arm/marvell-pj4.md	(revision 0)
+++ gcc/config/arm/marvell-pj4.md	(revision 0)
@@ -0,0 +1,205 @@
+;; Marvell ARM Processor Pipeline Description
+;; Copyright (C) 2010, 2011, 2012 Free Software Foundation, Inc.
+;; Contributed by Marvell.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; Pipeline description for the Marvell PJ4, aka "Flareon".
+(define_automaton "pj4")
+
+;; Issue resources
+(define_cpu_unit    "pj4_is1,pj4_is2"        "pj4")
+(define_reservation "pj4_is"             "(pj4_is1|pj4_is2)")
+(define_reservation "pj4_isb"            "(pj4_is1+pj4_is2)")
+
+;; Functional units
+(define_cpu_unit "pj4_alu1,pj4_alu2,pj4_mul,pj4_div" "pj4")
+
+;; Completion ports
+(define_cpu_unit "pj4_w1,pj4_w2"             "pj4")
+
+;; Complete/Retire control
+(define_cpu_unit    "pj4_c1,pj4_c2"          "pj4")
+(define_reservation "pj4_cp"             "(pj4_c1|pj4_c2)")
+(define_reservation "pj4_cpb"            "(pj4_c1+pj4_c2)")
+
+;; Integer arithmetic instructions
+
+(define_insn_reservation "pj4_alu_e1" 1
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "alu")
+       (not (eq_attr "conds" "set"))
+       (eq_attr "insn" "mov,mvn"))
+                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
+
+(define_insn_reservation "pj4_alu_e1_conds" 4
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "alu")
+       (eq_attr "conds" "set")
+       (eq_attr "insn" "mov,mvn"))
+                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
+
+(define_insn_reservation "pj4_alu" 1
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "alu")
+       (not (eq_attr "conds" "set"))
+       (not (eq_attr "insn" "mov,mvn")))
+                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
+
+(define_insn_reservation "pj4_alu_conds" 4
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "alu")
+       (eq_attr "conds" "set")
+       (not (eq_attr "insn" "mov,mvn")))
+                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
+
+(define_insn_reservation "pj4_shift" 1
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "alu_shift,alu_shift_reg")
+       (not (eq_attr "conds" "set"))
+       (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
+
+(define_insn_reservation "pj4_shift_conds" 4
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "alu_shift,alu_shift_reg")
+       (eq_attr "conds" "set")
+       (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
+
+(define_insn_reservation "pj4_alu_shift" 1
+  (and (eq_attr "tune" "marvell_pj4")
+       (not (eq_attr "conds" "set"))
+       (eq_attr "type" "alu_shift,alu_shift_reg"))
+                               "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
+
+(define_insn_reservation "pj4_alu_shift_conds" 4
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "conds" "set")
+       (eq_attr "type" "alu_shift,alu_shift_reg"))
+                               "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
+
+(define_bypass 2 "pj4_alu_shift,pj4_shift"
+                 "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp")
+
+(define_insn_reservation "pj4_ir_mul" 3
+  (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "mult")) "pj4_is,pj4_mul,nothing*2,pj4_cp")
+
+(define_insn_reservation "pj4_ir_div" 20
+  (and (eq_attr "tune" "marvell_pj4") (eq_attr "insn" "udiv,sdiv")) "pj4_is,pj4_div*19,pj4_cp")
+
+;; Branches and calls.
+
+(define_insn_reservation "pj4_branches" 0
+  (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "branch")) "pj4_is")
+
+(define_insn_reservation "pj4_calls" 32
+  (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "call")) "pj4_is")
+
+;; Load/store instructions
+
+(define_insn_reservation "pj4_ldr"  3
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "load_byte,load1"))
+                       "pj4_is,pj4_alu1,nothing*2,pj4_cp")
+
+(define_insn_reservation "pj4_ldrd" 3
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "load2"))
+                       "pj4_is,pj4_alu1,nothing*2,pj4_cpb")
+
+(define_insn_reservation "pj4_str"  1
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "store1"))
+                       "pj4_is,pj4_alu1,nothing*2,pj4_cp")
+
+(define_insn_reservation "pj4_strd" 1
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "store2"))
+                       "pj4_is,pj4_alu1,nothing*2,pj4_cpb")
+
+(define_insn_reservation "pj4_ldm" 4
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "load3,load4")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,nothing,pj4_cp,pj4_cp")
+
+(define_insn_reservation "pj4_stm" 2
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "store3,store4")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,nothing,pj4_cp,pj4_cp")
+
+;; Loads forward at WR-stage to ALU pipes
+(define_bypass 2 "pj4_ldr,pj4_ldrd" "pj4_alu")
+(define_bypass 2 "pj4_ldr,pj4_ldrd" "pj4_alu_shift" "arm_no_early_alu_shift_dep")
+
+(define_bypass 4 "pj4_ldr,pj4_ldrd" "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp")
+(define_bypass 5 "pj4_ldm" "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp")
+
+;; Loads to stores can back-to-back forward
+(define_bypass 1 "pj4_ldr,pj4_ldrd" "pj4_str,pj4_strd" "arm_no_early_store_addr_dep")
+
+;; PJ4 VFP floating point unit
+(define_automaton "pj4_vfp")
+
+(define_cpu_unit "vissue" "pj4_vfp")
+(define_cpu_unit "vadd"   "pj4_vfp")
+(define_cpu_unit "vmul"   "pj4_vfp")
+(define_cpu_unit "vdiv"   "pj4_vfp")
+(define_cpu_unit "vfast"  "pj4_vfp")
+
+(define_insn_reservation "pj4_vfp_add"  5
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "fadds,faddd")) "pj4_is,nothing*2,vissue,vadd,nothing*3")
+
+(define_insn_reservation "pj4_vfp_mul"  6
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "fmuls,fmuld")) "pj4_is,nothing*2,vissue,vmul,nothing*4")
+
+(define_insn_reservation "pj4_vfp_divs" 20
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "fdivs"))       "pj4_is,nothing*2,vissue,vdiv*18,nothing")
+
+(define_insn_reservation "pj4_vfp_divd" 34
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "fdivd"))       "pj4_is,nothing*2,vissue,vdiv*32,nothing")
+
+(define_insn_reservation "pj4_vfp_mac"  9
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "fmacs,fmacd"))
+                       "pj4_is,nothing*2,vissue,vmul,nothing*3,vadd,nothing*3")
+
+(define_bypass 5 "pj4_vfp_mac" "pj4_vfp_mac" "arm_no_early_mul_dep")
+
+(define_insn_reservation "pj4_vfp_cpy"  4
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,\
+                        fcmps,fcmpd,f_cvt"))  "pj4_is,nothing*2,vissue,vfast,nothing*2")
+
+;; Enlarge latency, and wish that more nondependent insns are
+;; scheduled immediately after VFP load.
+(define_insn_reservation "pj4_vfp_load" 4
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "f_loads,f_loadd"))    "pj4_isb,pj4_alu1,nothing,vissue,pj4_cp")
+
+(define_insn_reservation "pj4_vfp_store" 1
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "f_stores,f_stored"))  "pj4_isb,pj4_alu1,nothing,vissue,pj4_cp")
+
+(define_insn_reservation "pj4_vfp_to_core" 7
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "f_2_r,f_flag"))       "pj4_isb,nothing,nothing,vissue,vfast,nothing*2")
+
+(define_insn_reservation "pj4_core_to_vfp" 2
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "r_2_f"))              "pj4_isb,pj4_alu1,pj4_w1,vissue,pj4_cp")
+
Index: gcc/config/arm/arm.c
===================================================================
--- gcc/config/arm/arm.c	(revision 187623)
+++ gcc/config/arm/arm.c	(working copy)
@@ -24717,6 +24717,7 @@ arm_issue_rate (void)
     case cortexa8:
     case cortexa9:
     case fa726te:
+    case marvell_pj4:
       return 2;
 
     default:
Index: gcc/config/arm/arm-cores.def
===================================================================
--- gcc/config/arm/arm-cores.def	(revision 187623)
+++ gcc/config/arm/arm-cores.def	(working copy)
@@ -138,3 +138,6 @@ ARM_CORE("cortex-m3",	  cortexm3,	7M,				 FL_LDSCH
 ARM_CORE("cortex-m1",	  cortexm1,	6M,				 FL_LDSCHED, cortex)
 ARM_CORE("cortex-m0",	  cortexm0,	6M,				 FL_LDSCHED, cortex)
 ARM_CORE("cortex-m0plus", cortexm0plus,	6M,				 FL_LDSCHED, cortex)
+
+/* Marvell Processor */
+ARM_CORE("marvell-pj4",   marvell_pj4,  7A,                              FL_LDSCHED, 9e)
Index: gcc/config/arm/arm-tune.md
===================================================================
--- gcc/config/arm/arm-tune.md	(revision 187623)
+++ gcc/config/arm/arm-tune.md	(working copy)
@@ -1,5 +1,5 @@
 ;; -*- buffer-read-only: t -*-
 ;; Generated automatically by gentune.sh from arm-cores.def
 (define_attr "tune"
-	"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus"
+	"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
Index: gcc/config/arm/bpabi.h
===================================================================
--- gcc/config/arm/bpabi.h	(revision 187623)
+++ gcc/config/arm/bpabi.h	(working copy)
@@ -60,6 +60,7 @@
    |mcpu=cortex-a7					\
    |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15	\
    |mcpu=generic-armv7-a				\
+   |mcpu=marvell-pj4				\
    |march=armv7-m|mcpu=cortex-m3			\
    |march=armv7e-m|mcpu=cortex-m4			\
    |march=armv6-m|mcpu=cortex-m0			\
Index: gcc/config/arm/arm.md
===================================================================
--- gcc/config/arm/arm.md	(revision 187623)
+++ gcc/config/arm/arm.md	(working copy)
@@ -521,12 +521,19 @@
 	  (const_string "yes")
 	  (const_string "no"))))
 
+(define_attr "tune_marvell" "yes,no"
+  (const (if_then_else
+	  (eq_attr "tune" "marvell_pj4")
+	  (const_string "yes")
+	  (const_string "no"))))
+
 ;; True if the generic scheduling description should be used.
 
 (define_attr "generic_sched" "yes,no"
   (const (if_then_else
           (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexa15,cortexm4")
-	       (eq_attr "tune_cortexr4" "yes"))
+	       (eq_attr "tune_cortexr4" "yes")
+	       (eq_attr "tune_marvell" "yes"))
           (const_string "no")
           (const_string "yes"))))
 
@@ -534,7 +541,8 @@
   (const (if_then_else
 	  (and (eq_attr "fpu" "vfp")
 	       (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9,cortexm4")
-	       (eq_attr "tune_cortexr4" "no"))
+	       (eq_attr "tune_cortexr4" "no")
+	       (eq_attr "tune_marvell" "no"))
 	  (const_string "yes")
 	  (const_string "no"))))
 
@@ -557,6 +565,7 @@
 (include "cortex-m4.md")
 (include "cortex-m4-fpu.md")
 (include "vfp11.md")
+(include "marvell-pj4.md")
 
 \f
 ;;---------------------------------------------------------------------------

Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Ramana Radhakrishnan]

On 20 June 2012 03:53, Yi-Hsiu Hsu <ahsu@marvell.com> wrote:
> marvell-pj4 is added to BE8_LINK_SPEC.
>
> Modified patch is attached.

Missing a modified changelog entry.


Ramana

>
> Thanks!
>
> B.R.
> Yi-Hsiu, Hsu
>
> -----Original Message-----
> From: Ramana Radhakrishnan [mailto:ramana.radhakrishnan@linaro.org]
> Sent: Thursday, June 14, 2012 2:19 AM
> To: Yi-Hsiu Hsu
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores
>
> On 29 May 2012 10:07, Yi-Hsiu Hsu <ahsu@marvell.com> wrote:
>> Hi,
>>
>> This patch maintains Marvell PJ4 cores pipeline description.
>> Run arm testsuite on arm-linux-gnueabi and no extra regressions are found.
>>
>>        * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
>>        * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>>        * config/arm/arm-cores.def: Add core marvell-pj4.
>>        * config/arm/arm-tune.md: Regenerated.
>>        * config/arm/arm-tables.opt: Regenerated.
>>        * doc/invoke.texi: Added entry for marvell-pj4.
>
> This command line option should also be added to BE8_LINK_SPEC similar
> to what's done for the other v7-a cores.
>
> Ok with that change.
>
> regards,
> Ramana
>
>
>
>>
>>
>> Thanks!
>>
>> P.S. I create the patch from revision 187308, but this revision is unable to build successfully, then I apply this patch to revision 187623 and successfully build and pass the testsuite.
>>

RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Yi-Hsiu Hsu]

Updated changelog.

* config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
* config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
* config/arm/arm.md (tune_marvell): Add marvell_pj4.
* config/arm/arm-cores.def: Add core marvell-pj4.
* config/arm/arm-tune.md: Regenerated.
* config/arm/arm-tables.opt: Regenerated.
* config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell_pj4.
* doc/invoke.texi: Added entry for marvell-pj4.

B.R.
Yi-Hsiu, Hsu


-----Original Message-----
From: Ramana Radhakrishnan [mailto:ramana.radhakrishnan@linaro.org] 
Sent: Tuesday, June 26, 2012 3:36 AM
To: Yi-Hsiu Hsu
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores

On 20 June 2012 03:53, Yi-Hsiu Hsu <ahsu@marvell.com> wrote:
> marvell-pj4 is added to BE8_LINK_SPEC.
>
> Modified patch is attached.

Missing a modified changelog entry.


Ramana

>
> Thanks!
>
> B.R.
> Yi-Hsiu, Hsu
>
> -----Original Message-----
> From: Ramana Radhakrishnan [mailto:ramana.radhakrishnan@linaro.org]
> Sent: Thursday, June 14, 2012 2:19 AM
> To: Yi-Hsiu Hsu
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores
>
> On 29 May 2012 10:07, Yi-Hsiu Hsu <ahsu@marvell.com> wrote:
>> Hi,
>>
>> This patch maintains Marvell PJ4 cores pipeline description.
>> Run arm testsuite on arm-linux-gnueabi and no extra regressions are found.
>>
>>        * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
>>        * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>>        * config/arm/arm-cores.def: Add core marvell-pj4.
>>        * config/arm/arm-tune.md: Regenerated.
>>        * config/arm/arm-tables.opt: Regenerated.
>>        * doc/invoke.texi: Added entry for marvell-pj4.
>
> This command line option should also be added to BE8_LINK_SPEC similar
> to what's done for the other v7-a cores.
>
> Ok with that change.
>
> regards,
> Ramana
>
>
>
>>
>>
>> Thanks!
>>
>> P.S. I create the patch from revision 187308, but this revision is unable to build successfully, then I apply this patch to revision 187623 and successfully build and pass the testsuite.
>>

Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Chung-Lin Tang]

On 2012/6/26 09:37 AM, Yi-Hsiu Hsu wrote:
> Updated changelog.
> 
> * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
> * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
> * config/arm/arm.md (tune_marvell): Add marvell_pj4.
> * config/arm/arm-cores.def: Add core marvell-pj4.
> * config/arm/arm-tune.md: Regenerated.
> * config/arm/arm-tables.opt: Regenerated.
> * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell_pj4.
> * doc/invoke.texi: Added entry for marvell-pj4.

Another nit, I think the tune_marvell attribute now looks a bit
unneeded. You can just fold it into the "tune" clause of "generic_sched".

Thanks,
Chung-Lin

RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Yi-Hsiu Hsu]

Hi Chung-Lin,

I think tune_marvell attribute better be kept for future Marvell cores extension.
Thanks!

B.R.
Yi-Hsiu, Hsu


-----Original Message-----
From: Chung-Lin Tang [mailto:cltang@codesourcery.com] 
Sent: Tuesday, June 26, 2012 12:12 PM
To: Yi-Hsiu Hsu
Cc: Ramana Radhakrishnan; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores

On 2012/6/26 09:37 AM, Yi-Hsiu Hsu wrote:
> Updated changelog.
> 
> * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
> * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
> * config/arm/arm.md (tune_marvell): Add marvell_pj4.
> * config/arm/arm-cores.def: Add core marvell-pj4.
> * config/arm/arm-tune.md: Regenerated.
> * config/arm/arm-tables.opt: Regenerated.
> * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell_pj4.
> * doc/invoke.texi: Added entry for marvell-pj4.

Another nit, I think the tune_marvell attribute now looks a bit
unneeded. You can just fold it into the "tune" clause of "generic_sched".

Thanks,
Chung-Lin

PING: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Yi-Hsiu Hsu]

Ping!!

Cheers,
Yi-Hsiu, Hsu


-----Original Message-----
From: Yi-Hsiu Hsu 
Sent: Tuesday, June 26, 2012 1:51 PM
To: 'Chung-Lin Tang'
Cc: Ramana Radhakrishnan; gcc-patches@gcc.gnu.org
Subject: RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores

Hi Chung-Lin,

I think tune_marvell attribute better be kept for future Marvell cores extension.
Thanks!

B.R.
Yi-Hsiu, Hsu


-----Original Message-----
From: Chung-Lin Tang [mailto:cltang@codesourcery.com]
Sent: Tuesday, June 26, 2012 12:12 PM
To: Yi-Hsiu Hsu
Cc: Ramana Radhakrishnan; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores

On 2012/6/26 09:37 AM, Yi-Hsiu Hsu wrote:
> Updated changelog.
> 
> * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
> * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
> * config/arm/arm.md (tune_marvell): Add marvell_pj4.
> * config/arm/arm-cores.def: Add core marvell-pj4.
> * config/arm/arm-tune.md: Regenerated.
> * config/arm/arm-tables.opt: Regenerated.
> * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell_pj4.
> * doc/invoke.texi: Added entry for marvell-pj4.

Another nit, I think the tune_marvell attribute now looks a bit unneeded. You can just fold it into the "tune" clause of "generic_sched".

Thanks,
Chung-Lin

PING: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Yi-Hsiu Hsu]

This patch is pending for a long time.
Any progress?

Cheers,
Yi-Hsiu, Hsu


-----Original Message-----
From: Yi-Hsiu Hsu 
Sent: Tuesday, June 26, 2012 1:51 PM
To: 'Chung-Lin Tang'
Cc: Ramana Radhakrishnan; gcc-patches@gcc.gnu.org
Subject: RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores

Hi Chung-Lin,

I think tune_marvell attribute better be kept for future Marvell cores extension.
Thanks!

B.R.
Yi-Hsiu, Hsu

-----Original Message-----
From: Chung-Lin Tang [mailto:cltang@codesourcery.com] 
Sent: Tuesday, June 26, 2012 12:12 PM
To: Yi-Hsiu Hsu
Cc: Ramana Radhakrishnan; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores

On 2012/6/26 09:37 AM, Yi-Hsiu Hsu wrote:
> Updated changelog.
> 
> * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
> * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
> * config/arm/arm.md (tune_marvell): Add marvell_pj4.
> * config/arm/arm-cores.def: Add core marvell-pj4.
> * config/arm/arm-tune.md: Regenerated.
> * config/arm/arm-tables.opt: Regenerated.
> * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell_pj4.
> * doc/invoke.texi: Added entry for marvell-pj4.

Another nit, I think the tune_marvell attribute now looks a bit unneeded. You can just fold it into the "tune" clause of "generic_sched".

Thanks,
Chung-Lin

Re: RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Ramana Radhakrishnan]

[-- Attachment #1: Type: text/plain, Size: 2755 bytes --]

On 06/20/12 03:53, Yi-Hsiu Hsu wrote:
> marvell-pj4 is added to BE8_LINK_SPEC.

Sorry about the time it's taken to finish this patch up. I seem to have 
missed this one in the review process.

I've now applied the attached patch after taking into account the recent 
attribute changes and treated alu_reg and simple_alu_imm as you have 
treated alu, rebased to trunk to fix up some small issues with 
BE8_LINK_SPECS.

Additionally I've removed tune_marvell as that seems redundant at this 
point of time - an additional attribute and testing that appears to be 
unnecessary instead of just one more inequality test.

The only part I'm not sure about is how to treat the simple_alu_shift 
category here , so a patch to handle them in the pj4 pipeline 
description would be welcome.


Thanks
Ramana

2013-01-18  Yi-Hsiu Hsu  <ahsu@marvell.com>
             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

         * config/arm/marvell-pj4.md: New file.
         * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
         * config/arm/arm.md (generic_sched): Add marvell_pj4.
         (generic_vfp): Likewise.
         * config/arm/arm-cores.def: Add marvell-pj4.
         * config/arm/arm-tune.md: Regenerate.
         * config/arm/arm-tables.opt: Regenerate.
         * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell_pj4.
         * doc/invoke.texi: Document marvell-pj4.

>
> Modified patch is attached.
>
> Thanks!
>
> B.R.
> Yi-Hsiu, Hsu
>
> -----Original Message-----
> From: Ramana Radhakrishnan [mailto:ramana.radhakrishnan@linaro.org]
> Sent: Thursday, June 14, 2012 2:19 AM
> To: Yi-Hsiu Hsu
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores
>
> On 29 May 2012 10:07, Yi-Hsiu Hsu <ahsu@marvell.com> wrote:
>> Hi,
>>
>> This patch maintains Marvell PJ4 cores pipeline description.
>> Run arm testsuite on arm-linux-gnueabi and no extra regressions are found.
>>
>>         * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
>>         * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>>         * config/arm/arm-cores.def: Add core marvell-pj4.
>>         * config/arm/arm-tune.md: Regenerated.
>>         * config/arm/arm-tables.opt: Regenerated.
>>         * doc/invoke.texi: Added entry for marvell-pj4.
>
> This command line option should also be added to BE8_LINK_SPEC similar
> to what's done for the other v7-a cores.
>
> Ok with that change.
>
> regards,
> Ramana
>
>
>
>>
>>
>> Thanks!
>>
>> P.S. I create the patch from revision 187308, but this revision is unable to build successfully, then I apply this patch to revision 187623 and successfully build and pass the testsuite.
>>

[-- Attachment #2: p1 --]
[-- Type: text/plain, Size: 14786 bytes --]

commit faf5471d7d4616ad19d6bbae2c41e382ae506110
Author: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Date:   Fri Jan 18 14:12:19 2013 +0000

    Apply tuning for marvell-pj4

diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 0cd8714..a4cb7c6 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -137,3 +137,4 @@ ARM_CORE("cortex-m3",	  cortexm3,	7M,				 FL_LDSCHED, cortex)
 ARM_CORE("cortex-m1",	  cortexm1,	6M,				 FL_LDSCHED, v6m)
 ARM_CORE("cortex-m0",	  cortexm0,	6M,				 FL_LDSCHED, v6m)
 ARM_CORE("cortex-m0plus", cortexm0plus,	6M,				 FL_LDSCHED, v6m)
+ARM_CORE("marvell-pj4",   marvell_pj4,  7A,                              FL_LDSCHED, 9e)
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 6d0af59..06a529d 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -273,6 +273,9 @@ Enum(processor_type) String(cortex-m0) Value(cortexm0)
 EnumValue
 Enum(processor_type) String(cortex-m0plus) Value(cortexm0plus)
 
+EnumValue
+Enum(processor_type) String(marvell-pj4) Value(marvell_pj4)
+
 Enum
 Name(arm_arch) Type(int)
 Known ARM architectures (for use with the -march= option):
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index 040587a..26c2e1f 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -1,5 +1,5 @@
 ;; -*- buffer-read-only: t -*-
 ;; Generated automatically by gentune.sh from arm-cores.def
 (define_attr "tune"
-	"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus"
+	"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3bf7397..9d3981d 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -25644,6 +25644,7 @@ arm_issue_rate (void)
     case cortexa8:
     case cortexa9:
     case fa726te:
+    case marvell_pj4:
       return 2;
 
     default:
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index c7b30eb..22f2218 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -500,7 +500,7 @@
 
 (define_attr "generic_sched" "yes,no"
   (const (if_then_else
-          (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexm4")
+          (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexm4,marvell_pj4")
 	       (eq_attr "tune_cortexr4" "yes"))
           (const_string "no")
           (const_string "yes"))))
@@ -508,7 +508,7 @@
 (define_attr "generic_vfp" "yes,no"
   (const (if_then_else
 	  (and (eq_attr "fpu" "vfp")
-	       (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,cortexa8,cortexa9,cortexm4")
+	       (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,cortexa8,cortexa9,cortexm4,marvell_pj4")
 	       (eq_attr "tune_cortexr4" "no"))
 	  (const_string "yes")
 	  (const_string "no"))))
@@ -534,6 +534,7 @@
 (include "cortex-m4.md")
 (include "cortex-m4-fpu.md")
 (include "vfp11.md")
+(include "marvell-pj4.md")
 
 \f
 ;;---------------------------------------------------------------------------
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index eaf2cbb..bee429f 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -59,6 +59,7 @@
   " %{!mlittle-endian:%{march=armv7-a|mcpu=cortex-a5    \
    |mcpu=cortex-a7                                      \
    |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15       \
+   |mcpu=marvell-pj4					\
    |mcpu=generic-armv7-a                                \
    |march=armv7-m|mcpu=cortex-m3                        \
    |march=armv7e-m|mcpu=cortex-m4                       \
@@ -70,6 +71,7 @@
   " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5        \
    |mcpu=cortex-a7                                      \
    |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15       \
+   |mcpu=marvell-pj4					\
    |mcpu=generic-armv7-a                                \
    |march=armv7-m|mcpu=cortex-m3                        \
    |march=armv7e-m|mcpu=cortex-m4                       \
diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md
new file mode 100644
index 0000000..8df47d3
--- /dev/null
+++ b/gcc/config/arm/marvell-pj4.md
@@ -0,0 +1,205 @@
+;; Marvell ARM Processor Pipeline Description
+;; Copyright (C) 2010, 2011, 2012 Free Software Foundation, Inc.
+;; Contributed by Marvell.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; Pipeline description for the Marvell PJ4, aka "Flareon".
+(define_automaton "pj4")
+
+;; Issue resources
+(define_cpu_unit    "pj4_is1,pj4_is2"        "pj4")
+(define_reservation "pj4_is"             "(pj4_is1|pj4_is2)")
+(define_reservation "pj4_isb"            "(pj4_is1+pj4_is2)")
+
+;; Functional units
+(define_cpu_unit "pj4_alu1,pj4_alu2,pj4_mul,pj4_div" "pj4")
+
+;; Completion ports
+(define_cpu_unit "pj4_w1,pj4_w2"             "pj4")
+
+;; Complete/Retire control
+(define_cpu_unit    "pj4_c1,pj4_c2"          "pj4")
+(define_reservation "pj4_cp"             "(pj4_c1|pj4_c2)")
+(define_reservation "pj4_cpb"            "(pj4_c1+pj4_c2)")
+
+;; Integer arithmetic instructions
+
+(define_insn_reservation "pj4_alu_e1" 1
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "alu_reg,simple_alu_imm")
+       (not (eq_attr "conds" "set"))
+       (eq_attr "insn" "mov,mvn"))
+                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
+
+(define_insn_reservation "pj4_alu_e1_conds" 4
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "alu_reg,simple_alu_imm")
+       (eq_attr "conds" "set")
+       (eq_attr "insn" "mov,mvn"))
+                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
+
+(define_insn_reservation "pj4_alu" 1
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "alu_reg,simple_alu_imm")
+       (not (eq_attr "conds" "set"))
+       (not (eq_attr "insn" "mov,mvn")))
+                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
+
+(define_insn_reservation "pj4_alu_conds" 4
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "alu_reg,simple_alu_imm")
+       (eq_attr "conds" "set")
+       (not (eq_attr "insn" "mov,mvn")))
+                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
+
+(define_insn_reservation "pj4_shift" 1
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "alu_shift,alu_shift_reg")
+       (not (eq_attr "conds" "set"))
+       (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
+
+(define_insn_reservation "pj4_shift_conds" 4
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "alu_shift,alu_shift_reg")
+       (eq_attr "conds" "set")
+       (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
+
+(define_insn_reservation "pj4_alu_shift" 1
+  (and (eq_attr "tune" "marvell_pj4")
+       (not (eq_attr "conds" "set"))
+       (eq_attr "type" "alu_shift,alu_shift_reg"))
+                               "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
+
+(define_insn_reservation "pj4_alu_shift_conds" 4
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "conds" "set")
+       (eq_attr "type" "alu_shift,alu_shift_reg"))
+                               "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
+
+(define_bypass 2 "pj4_alu_shift,pj4_shift"
+                 "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp")
+
+(define_insn_reservation "pj4_ir_mul" 3
+  (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "mult")) "pj4_is,pj4_mul,nothing*2,pj4_cp")
+
+(define_insn_reservation "pj4_ir_div" 20
+  (and (eq_attr "tune" "marvell_pj4") (eq_attr "insn" "udiv,sdiv")) "pj4_is,pj4_div*19,pj4_cp")
+
+;; Branches and calls.
+
+(define_insn_reservation "pj4_branches" 0
+  (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "branch")) "pj4_is")
+
+(define_insn_reservation "pj4_calls" 32
+  (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "call")) "pj4_is")
+
+;; Load/store instructions
+
+(define_insn_reservation "pj4_ldr"  3
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "load_byte,load1"))
+                       "pj4_is,pj4_alu1,nothing*2,pj4_cp")
+
+(define_insn_reservation "pj4_ldrd" 3
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "load2"))
+                       "pj4_is,pj4_alu1,nothing*2,pj4_cpb")
+
+(define_insn_reservation "pj4_str"  1
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "store1"))
+                       "pj4_is,pj4_alu1,nothing*2,pj4_cp")
+
+(define_insn_reservation "pj4_strd" 1
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "store2"))
+                       "pj4_is,pj4_alu1,nothing*2,pj4_cpb")
+
+(define_insn_reservation "pj4_ldm" 4
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "load3,load4")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,nothing,pj4_cp,pj4_cp")
+
+(define_insn_reservation "pj4_stm" 2
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "store3,store4")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,nothing,pj4_cp,pj4_cp")
+
+;; Loads forward at WR-stage to ALU pipes
+(define_bypass 2 "pj4_ldr,pj4_ldrd" "pj4_alu")
+(define_bypass 2 "pj4_ldr,pj4_ldrd" "pj4_alu_shift" "arm_no_early_alu_shift_dep")
+
+(define_bypass 4 "pj4_ldr,pj4_ldrd" "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp")
+(define_bypass 5 "pj4_ldm" "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp")
+
+;; Loads to stores can back-to-back forward
+(define_bypass 1 "pj4_ldr,pj4_ldrd" "pj4_str,pj4_strd" "arm_no_early_store_addr_dep")
+
+;; PJ4 VFP floating point unit
+(define_automaton "pj4_vfp")
+
+(define_cpu_unit "vissue" "pj4_vfp")
+(define_cpu_unit "vadd"   "pj4_vfp")
+(define_cpu_unit "vmul"   "pj4_vfp")
+(define_cpu_unit "vdiv"   "pj4_vfp")
+(define_cpu_unit "vfast"  "pj4_vfp")
+
+(define_insn_reservation "pj4_vfp_add"  5
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "fadds,faddd")) "pj4_is,nothing*2,vissue,vadd,nothing*3")
+
+(define_insn_reservation "pj4_vfp_mul"  6
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "fmuls,fmuld")) "pj4_is,nothing*2,vissue,vmul,nothing*4")
+
+(define_insn_reservation "pj4_vfp_divs" 20
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "fdivs"))       "pj4_is,nothing*2,vissue,vdiv*18,nothing")
+
+(define_insn_reservation "pj4_vfp_divd" 34
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "fdivd"))       "pj4_is,nothing*2,vissue,vdiv*32,nothing")
+
+(define_insn_reservation "pj4_vfp_mac"  9
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "fmacs,fmacd"))
+                       "pj4_is,nothing*2,vissue,vmul,nothing*3,vadd,nothing*3")
+
+(define_bypass 5 "pj4_vfp_mac" "pj4_vfp_mac" "arm_no_early_mul_dep")
+
+(define_insn_reservation "pj4_vfp_cpy"  4
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,\
+                        fcmps,fcmpd,f_cvt"))  "pj4_is,nothing*2,vissue,vfast,nothing*2")
+
+;; Enlarge latency, and wish that more nondependent insns are
+;; scheduled immediately after VFP load.
+(define_insn_reservation "pj4_vfp_load" 4
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "f_loads,f_loadd"))    "pj4_isb,pj4_alu1,nothing,vissue,pj4_cp")
+
+(define_insn_reservation "pj4_vfp_store" 1
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "f_stores,f_stored"))  "pj4_isb,pj4_alu1,nothing,vissue,pj4_cp")
+
+(define_insn_reservation "pj4_vfp_to_core" 7
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "f_2_r,f_flag"))       "pj4_isb,nothing,nothing,vissue,vfast,nothing*2")
+
+(define_insn_reservation "pj4_core_to_vfp" 2
+  (and (eq_attr "tune" "marvell_pj4")
+       (eq_attr "type" "r_2_f"))              "pj4_isb,pj4_alu1,pj4_w1,vissue,pj4_cp")
+
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 9ef6c93..887d31e 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -11242,6 +11242,7 @@ assembly code.  Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{cortex-m1},
 @samp{cortex-m0},
 @samp{cortex-m0plus},
+@samp{marvell-pj4},
 @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
 @samp{fa526}, @samp{fa626},
 @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}.

Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Matthias Klose]

Am 18.01.2013 15:28, schrieb Ramana Radhakrishnan:
> On 06/20/12 03:53, Yi-Hsiu Hsu wrote:
>> marvell-pj4 is added to BE8_LINK_SPEC.
> 
> Sorry about the time it's taken to finish this patch up. I seem to have missed
> this one in the review process.
> 
> I've now applied the attached patch after taking into account the recent
> attribute changes and treated alu_reg and simple_alu_imm as you have treated
> alu, rebased to trunk to fix up some small issues with BE8_LINK_SPECS.
> 
> Additionally I've removed tune_marvell as that seems redundant at this point of
> time - an additional attribute and testing that appears to be unnecessary
> instead of just one more inequality test.
> 
> The only part I'm not sure about is how to treat the simple_alu_shift category
> here , so a patch to handle them in the pj4 pipeline description would be welcome.
> 
> 
> Thanks
> Ramana
> 
> 2013-01-18  Yi-Hsiu Hsu  <ahsu@marvell.com>
>             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
> 
>         * config/arm/marvell-pj4.md: New file.
>         * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>         * config/arm/arm.md (generic_sched): Add marvell_pj4.
>         (generic_vfp): Likewise.
>         * config/arm/arm-cores.def: Add marvell-pj4.
>         * config/arm/arm-tune.md: Regenerate.
>         * config/arm/arm-tables.opt: Regenerate.
>         * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell_pj4.
>         * doc/invoke.texi: Document marvell-pj4.
> 
>>
>> Modified patch is attached.

the patch was missing the new file config/arm/marvell-pj4.md. Checked is as
obvious to restore the bootstrap.

  Matthias

Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Bin.Cheng]

On Mon, Jan 21, 2013 at 4:36 AM, Matthias Klose <doko@ubuntu.com> wrote:
> Am 18.01.2013 15:28, schrieb Ramana Radhakrishnan:
>> On 06/20/12 03:53, Yi-Hsiu Hsu wrote:
>>> marvell-pj4 is added to BE8_LINK_SPEC.
>>
>> Sorry about the time it's taken to finish this patch up. I seem to have missed
>> this one in the review process.
>>
>> I've now applied the attached patch after taking into account the recent
>> attribute changes and treated alu_reg and simple_alu_imm as you have treated
>> alu, rebased to trunk to fix up some small issues with BE8_LINK_SPECS.
>>
>> Additionally I've removed tune_marvell as that seems redundant at this point of
>> time - an additional attribute and testing that appears to be unnecessary
>> instead of just one more inequality test.
>>
>> The only part I'm not sure about is how to treat the simple_alu_shift category
>> here , so a patch to handle them in the pj4 pipeline description would be welcome.
>>
>>
>> Thanks
>> Ramana
>>
>> 2013-01-18  Yi-Hsiu Hsu  <ahsu@marvell.com>
>>             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
>>
>>         * config/arm/marvell-pj4.md: New file.
>>         * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>>         * config/arm/arm.md (generic_sched): Add marvell_pj4.
>>         (generic_vfp): Likewise.
>>         * config/arm/arm-cores.def: Add marvell-pj4.
>>         * config/arm/arm-tune.md: Regenerate.
>>         * config/arm/arm-tables.opt: Regenerate.
>>         * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell_pj4.
>>         * doc/invoke.texi: Document marvell-pj4.
>>
>>>
>>> Modified patch is attached.
>
> the patch was missing the new file config/arm/marvell-pj4.md. Checked is as
> obvious to restore the bootstrap.
>
>   Matthias
>

Checkin R195295 for this patch causes build failure for arm-none-eabi.
Please see PR56058.

--
Best Regards.

RE: RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Yi-Hsiu Hsu]

[-- Attachment #1: Type: text/plain, Size: 3134 bytes --]

Hi Ramana,

Attached is the patch for marvell-pj4.md to fix the simple_alu_shift category.
Thanks for your kindly help.

Cheers,
Yi-Hsiu, Hsu

-----Original Message-----
From: Ramana Radhakrishnan [mailto:ramrad01@arm.com] 
Sent: Friday, January 18, 2013 10:28 PM
To: Yi-Hsiu Hsu
Cc: gcc-patches@gcc.gnu.org ;
Subject: Re: RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores

On 06/20/12 03:53, Yi-Hsiu Hsu wrote:
> marvell-pj4 is added to BE8_LINK_SPEC.

Sorry about the time it's taken to finish this patch up. I seem to have missed this one in the review process.

I've now applied the attached patch after taking into account the recent attribute changes and treated alu_reg and simple_alu_imm as you have treated alu, rebased to trunk to fix up some small issues with BE8_LINK_SPECS.

Additionally I've removed tune_marvell as that seems redundant at this point of time - an additional attribute and testing that appears to be unnecessary instead of just one more inequality test.

The only part I'm not sure about is how to treat the simple_alu_shift category here , so a patch to handle them in the pj4 pipeline description would be welcome.


Thanks
Ramana

2013-01-18  Yi-Hsiu Hsu  <ahsu@marvell.com>
             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

         * config/arm/marvell-pj4.md: New file.
         * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
         * config/arm/arm.md (generic_sched): Add marvell_pj4.
         (generic_vfp): Likewise.
         * config/arm/arm-cores.def: Add marvell-pj4.
         * config/arm/arm-tune.md: Regenerate.
         * config/arm/arm-tables.opt: Regenerate.
         * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell_pj4.
         * doc/invoke.texi: Document marvell-pj4.

>
> Modified patch is attached.
>
> Thanks!
>
> B.R.
> Yi-Hsiu, Hsu
>
> -----Original Message-----
> From: Ramana Radhakrishnan [mailto:ramana.radhakrishnan@linaro.org]
> Sent: Thursday, June 14, 2012 2:19 AM
> To: Yi-Hsiu Hsu
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores
>
> On 29 May 2012 10:07, Yi-Hsiu Hsu <ahsu@marvell.com> wrote:
>> Hi,
>>
>> This patch maintains Marvell PJ4 cores pipeline description.
>> Run arm testsuite on arm-linux-gnueabi and no extra regressions are found.
>>
>>         * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
>>         * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>>         * config/arm/arm-cores.def: Add core marvell-pj4.
>>         * config/arm/arm-tune.md: Regenerated.
>>         * config/arm/arm-tables.opt: Regenerated.
>>         * doc/invoke.texi: Added entry for marvell-pj4.
>
> This command line option should also be added to BE8_LINK_SPEC similar 
> to what's done for the other v7-a cores.
>
> Ok with that change.
>
> regards,
> Ramana
>
>
>
>>
>>
>> Thanks!
>>
>> P.S. I create the patch from revision 187308, but this revision is unable to build successfully, then I apply this patch to revision 187623 and successfully build and pass the testsuite.
>>

[-- Attachment #2: pj4.patch --]
[-- Type: application/octet-stream, Size: 2953 bytes --]

diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md
index cbf3110..fcbd31f 100644
--- a/gcc/config/arm/marvell-pj4.md
+++ b/gcc/config/arm/marvell-pj4.md
@@ -41,54 +41,54 @@
 
 (define_insn_reservation "pj4_alu_e1" 1
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu")
+       (eq_attr "type" "simple_alu_imm,alu_reg")
        (not (eq_attr "conds" "set"))
        (eq_attr "insn" "mov,mvn,andor"))
                                "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_e1_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu")
+       (eq_attr "type" "simple_alu_imm,alu_reg")
        (eq_attr "conds" "set")
        (eq_attr "insn" "mov,mvn,andor"))
                                "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu" 1
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu")
+       (eq_attr "type" "simple_alu_imm,alu_reg")
        (not (eq_attr "conds" "set"))
        (not (eq_attr "insn" "mov,mvn,andor")))
                                "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu")
+       (eq_attr "type" "simple_alu_imm,alu_reg")
        (eq_attr "conds" "set")
        (not (eq_attr "insn" "mov,mvn,andor")))
                                "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_shift" 1
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu_shift,alu_shift_reg")
+       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")
        (not (eq_attr "conds" "set"))
        (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_shift_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu_shift,alu_shift_reg")
+       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")
        (eq_attr "conds" "set")
        (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_shift" 1
   (and (eq_attr "tune" "marvell_pj4")
        (not (eq_attr "conds" "set"))
-       (eq_attr "type" "alu_shift,alu_shift_reg"))
+       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift"))
                                "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_shift_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
        (eq_attr "conds" "set")
-       (eq_attr "type" "alu_shift,alu_shift_reg"))
+       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift"))
                                "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
 
 (define_bypass 2 "pj4_alu_shift,pj4_shift"

Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Ramana Radhakrishnan]

On 01/20/13 20:36, Matthias Klose wrote:
> Am 18.01.2013 15:28, schrieb Ramana Radhakrishnan:
>> On 06/20/12 03:53, Yi-Hsiu Hsu wrote:
>>> marvell-pj4 is added to BE8_LINK_SPEC.
>>
>> Sorry about the time it's taken to finish this patch up. I seem to have missed
>> this one in the review process.
>>
>> I've now applied the attached patch after taking into account the recent
>> attribute changes and treated alu_reg and simple_alu_imm as you have treated
>> alu, rebased to trunk to fix up some small issues with BE8_LINK_SPECS.
>>
>> Additionally I've removed tune_marvell as that seems redundant at this point of
>> time - an additional attribute and testing that appears to be unnecessary
>> instead of just one more inequality test.
>>
>> The only part I'm not sure about is how to treat the simple_alu_shift category
>> here , so a patch to handle them in the pj4 pipeline description would be welcome.
>>
>>
>> Thanks
>> Ramana
>>
>> 2013-01-18  Yi-Hsiu Hsu  <ahsu@marvell.com>
>>              Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
>>
>>          * config/arm/marvell-pj4.md: New file.
>>          * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>>          * config/arm/arm.md (generic_sched): Add marvell_pj4.
>>          (generic_vfp): Likewise.
>>          * config/arm/arm-cores.def: Add marvell-pj4.
>>          * config/arm/arm-tune.md: Regenerate.
>>          * config/arm/arm-tables.opt: Regenerate.
>>          * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell_pj4.
>>          * doc/invoke.texi: Document marvell-pj4.
>>
>>>
>>> Modified patch is attached.
>
> the patch was missing the new file config/arm/marvell-pj4.md. Checked is as
> obvious to restore the bootstrap.

Thanks - Looks like I missed adding that. Uggh.

Ramana

Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Ramana Radhakrishnan]

[-- Attachment #1: Type: text/plain, Size: 3802 bytes --]


Hi Yi-Hsiu Hsu,

On 01/21/13 08:51, Yi-Hsiu Hsu wrote:
> Hi Ramana,
>
> Attached is the patch for marvell-pj4.md to fix the simple_alu_shift category.
> Thanks for your kindly help.


In the future please submit patches with a Changelog entry. I've created 
one for this patch as it needed a bit of splitting up given the 
mis-commit earlier by doko.

So in this case I've now committed the following with the following 
Changelog entry.

Regards,
Ramana


2013-01-21  Yi-Hsiu Hsu  <ahsu@marvell.com>

         * config/arm/marvell-pj4.md (pj4_shift_conds, pj4_alu_shift,
         pj4_alu_shift_conds, pj4_shift): Handle simple_alu_shift.

>
> Cheers,
> Yi-Hsiu, Hsu
>
> -----Original Message-----
> From: Ramana Radhakrishnan [mailto:ramrad01@arm.com]
> Sent: Friday, January 18, 2013 10:28 PM
> To: Yi-Hsiu Hsu
> Cc: gcc-patches@gcc.gnu.org ;
> Subject: Re: RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores
>
> On 06/20/12 03:53, Yi-Hsiu Hsu wrote:
>> marvell-pj4 is added to BE8_LINK_SPEC.
>
> Sorry about the time it's taken to finish this patch up. I seem to have missed this one in the review process.
>
> I've now applied the attached patch after taking into account the recent attribute changes and treated alu_reg and simple_alu_imm as you have treated alu, rebased to trunk to fix up some small issues with BE8_LINK_SPECS.
>
> Additionally I've removed tune_marvell as that seems redundant at this point of time - an additional attribute and testing that appears to be unnecessary instead of just one more inequality test.
>
> The only part I'm not sure about is how to treat the simple_alu_shift category here , so a patch to handle them in the pj4 pipeline description would be welcome.
>
>
> Thanks
> Ramana
>
> 2013-01-18  Yi-Hsiu Hsu  <ahsu@marvell.com>
>               Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
>
>           * config/arm/marvell-pj4.md: New file.
>           * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>           * config/arm/arm.md (generic_sched): Add marvell_pj4.
>           (generic_vfp): Likewise.
>           * config/arm/arm-cores.def: Add marvell-pj4.
>           * config/arm/arm-tune.md: Regenerate.
>           * config/arm/arm-tables.opt: Regenerate.
>           * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell_pj4.
>           * doc/invoke.texi: Document marvell-pj4.
>
>>
>> Modified patch is attached.
>>
>> Thanks!
>>
>> B.R.
>> Yi-Hsiu, Hsu
>>
>> -----Original Message-----
>> From: Ramana Radhakrishnan [mailto:ramana.radhakrishnan@linaro.org]
>> Sent: Thursday, June 14, 2012 2:19 AM
>> To: Yi-Hsiu Hsu
>> Cc: gcc-patches@gcc.gnu.org
>> Subject: Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores
>>
>> On 29 May 2012 10:07, Yi-Hsiu Hsu <ahsu@marvell.com> wrote:
>>> Hi,
>>>
>>> This patch maintains Marvell PJ4 cores pipeline description.
>>> Run arm testsuite on arm-linux-gnueabi and no extra regressions are found.
>>>
>>>          * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
>>>          * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>>>          * config/arm/arm-cores.def: Add core marvell-pj4.
>>>          * config/arm/arm-tune.md: Regenerated.
>>>          * config/arm/arm-tables.opt: Regenerated.
>>>          * doc/invoke.texi: Added entry for marvell-pj4.
>>
>> This command line option should also be added to BE8_LINK_SPEC similar
>> to what's done for the other v7-a cores.
>>
>> Ok with that change.
>>
>> regards,
>> Ramana
>>
>>
>>
>>>
>>>
>>> Thanks!
>>>
>>> P.S. I create the patch from revision 187308, but this revision is unable to build successfully, then I apply this patch to revision 187623 and successfully build and pass the testsuite.
>>> =

[-- Attachment #2: pj4.txt --]
[-- Type: text/plain, Size: 1669 bytes --]

Index: gcc/config/arm/marvell-pj4.md
===================================================================
--- gcc/config/arm/marvell-pj4.md	(revision 195332)
+++ gcc/config/arm/marvell-pj4.md	(working copy)
@@ -69,26 +69,26 @@
 
 (define_insn_reservation "pj4_shift" 1
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu_shift,alu_shift_reg")
+       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")
        (not (eq_attr "conds" "set"))
        (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_shift_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
-       (eq_attr "type" "alu_shift,alu_shift_reg")
+       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift")
        (eq_attr "conds" "set")
        (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_shift" 1
   (and (eq_attr "tune" "marvell_pj4")
        (not (eq_attr "conds" "set"))
-       (eq_attr "type" "alu_shift,alu_shift_reg"))
+       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift"))
                                "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
 
 (define_insn_reservation "pj4_alu_shift_conds" 4
   (and (eq_attr "tune" "marvell_pj4")
        (eq_attr "conds" "set")
-       (eq_attr "type" "alu_shift,alu_shift_reg"))
+       (eq_attr "type" "alu_shift,alu_shift_reg,simple_alu_shift"))
                                "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
 
 (define_bypass 2 "pj4_alu_shift,pj4_shift"

RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores

[Yi-Hsiu Hsu]

Hi Ramana,
Sorry for missing the Changelog, I will add it for future patches.
Thanks for your kindly help.

Cheers,
Compiler Team @ MTL
Yi-Hsiu, Hsu


-----Original Message-----
From: Ramana Radhakrishnan [mailto:ramrad01@arm.com] 
Sent: Monday, January 21, 2013 6:56 PM
To: Yi-Hsiu Hsu
Cc: gcc-patches@gcc.gnu.org; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores


Hi Yi-Hsiu Hsu,

On 01/21/13 08:51, Yi-Hsiu Hsu wrote:
> Hi Ramana,
>
> Attached is the patch for marvell-pj4.md to fix the simple_alu_shift category.
> Thanks for your kindly help.


In the future please submit patches with a Changelog entry. I've created one for this patch as it needed a bit of splitting up given the mis-commit earlier by doko.

So in this case I've now committed the following with the following Changelog entry.

Regards,
Ramana


2013-01-21  Yi-Hsiu Hsu  <ahsu@marvell.com>

         * config/arm/marvell-pj4.md (pj4_shift_conds, pj4_alu_shift,
         pj4_alu_shift_conds, pj4_shift): Handle simple_alu_shift.

>
> Cheers,
> Yi-Hsiu, Hsu
>
> -----Original Message-----
> From: Ramana Radhakrishnan [mailto:ramrad01@arm.com]
> Sent: Friday, January 18, 2013 10:28 PM
> To: Yi-Hsiu Hsu
> Cc: gcc-patches@gcc.gnu.org ;
> Subject: Re: RE: [PATCH, ARM] New CPU support for Marvell PJ4 cores
>
> On 06/20/12 03:53, Yi-Hsiu Hsu wrote:
>> marvell-pj4 is added to BE8_LINK_SPEC.
>
> Sorry about the time it's taken to finish this patch up. I seem to have missed this one in the review process.
>
> I've now applied the attached patch after taking into account the recent attribute changes and treated alu_reg and simple_alu_imm as you have treated alu, rebased to trunk to fix up some small issues with BE8_LINK_SPECS.
>
> Additionally I've removed tune_marvell as that seems redundant at this point of time - an additional attribute and testing that appears to be unnecessary instead of just one more inequality test.
>
> The only part I'm not sure about is how to treat the simple_alu_shift category here , so a patch to handle them in the pj4 pipeline description would be welcome.
>
>
> Thanks
> Ramana
>
> 2013-01-18  Yi-Hsiu Hsu  <ahsu@marvell.com>
>               Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
>
>           * config/arm/marvell-pj4.md: New file.
>           * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>           * config/arm/arm.md (generic_sched): Add marvell_pj4.
>           (generic_vfp): Likewise.
>           * config/arm/arm-cores.def: Add marvell-pj4.
>           * config/arm/arm-tune.md: Regenerate.
>           * config/arm/arm-tables.opt: Regenerate.
>           * config/arm/bpabi.h (BE8_LINK_SPEC): Add marvell_pj4.
>           * doc/invoke.texi: Document marvell-pj4.
>
>>
>> Modified patch is attached.
>>
>> Thanks!
>>
>> B.R.
>> Yi-Hsiu, Hsu
>>
>> -----Original Message-----
>> From: Ramana Radhakrishnan [mailto:ramana.radhakrishnan@linaro.org]
>> Sent: Thursday, June 14, 2012 2:19 AM
>> To: Yi-Hsiu Hsu
>> Cc: gcc-patches@gcc.gnu.org
>> Subject: Re: [PATCH, ARM] New CPU support for Marvell PJ4 cores
>>
>> On 29 May 2012 10:07, Yi-Hsiu Hsu <ahsu@marvell.com> wrote:
>>> Hi,
>>>
>>> This patch maintains Marvell PJ4 cores pipeline description.
>>> Run arm testsuite on arm-linux-gnueabi and no extra regressions are found.
>>>
>>>          * config/arm/marvell-pj4.md: New marvell-pj4 pipeline description.
>>>          * config/arm/arm.c (arm_issue_rate): Add marvell_pj4.
>>>          * config/arm/arm-cores.def: Add core marvell-pj4.
>>>          * config/arm/arm-tune.md: Regenerated.
>>>          * config/arm/arm-tables.opt: Regenerated.
>>>          * doc/invoke.texi: Added entry for marvell-pj4.
>>
>> This command line option should also be added to BE8_LINK_SPEC 
>> similar to what's done for the other v7-a cores.
>>
>> Ok with that change.
>>
>> regards,
>> Ramana
>>
>>
>>
>>>
>>>
>>> Thanks!
>>>
>>> P.S. I create the patch from revision 187308, but this revision is unable to build successfully, then I apply this patch to revision 187623 and successfully build and pass the testsuite.
>>> =