From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22973 invoked by alias); 22 Feb 2013 16:29:52 -0000 Received: (qmail 22965 invoked by uid 22791); 22 Feb 2013 16:29:50 -0000 X-SWARE-Spam-Status: No, hits=-1.5 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,KHOP_SPAMHAUS_DROP,KHOP_THREADED,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 22 Feb 2013 16:29:43 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 22 Feb 2013 16:29:42 +0000 Received: from [10.1.69.67] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 22 Feb 2013 16:29:40 +0000 Message-ID: <51279CF4.3010809@arm.com> Date: Fri, 22 Feb 2013 16:29:00 -0000 From: Richard Earnshaw User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:15.0) Gecko/20120907 Thunderbird/15.0.1 MIME-Version: 1.0 To: Greta Yorsh CC: GCC Patches , Ramana Radhakrishnan , "nickc@redhat.com" , "paul@codesourcery.com" Subject: Re: [PATCH,ARM][1/n] New patterns for subtract with carry References: <001101ce0e05$f5928a50$e0b79ef0$@yorsh@arm.com> <001301ce0e06$bbd193f0$3374bbd0$@yorsh@arm.com> In-Reply-To: <001301ce0e06$bbd193f0$3374bbd0$@yorsh@arm.com> X-MC-Unique: 113022216294202101 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2013-02/txt/msg01069.txt.bz2 On 18/02/13 18:35, Greta Yorsh wrote: > Add patterns to handle various subtract with carry operations. > > These patterns match RTL insns emitted by splitters > for DImode operations such as subdi, negdi, and cmpdi. > > gcc/ > > 2013-02-14 Greta Yorsh > > * config/arm/arm.md (subsi3_carryin, subsi3_carryin_const): New > patterns. > (subsi3_carryin_compare,subsi3_carryin_compare_const): Likewise. > (subsi3_carryin_shift,rsbsi3_carryin_shift): Likewise. > > Not ok. RSC does not exist in Thumb state. R. > 1-patterns-subtract-with-carry.patch.txt > > > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > index 35294dd6560ac63279d95eca6cf774257e06bd93..0000000000000000000000000= 000000000000000 100644 > --- a/gcc/config/arm/arm.md > +++ b/gcc/config/arm/arm.md > @@ -1019,3 +1019,86 @@ (define_insn "*addsi3_carryin_clobercc_< > [(set_attr "conds" "set")] > ) > > +(define_insn "*subsi3_carryin" > + [(set (match_operand:SI 0 "s_register_operand" "=3Dr,r") > + (minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,= I") > + (match_operand:SI 2 "s_register_operand" "r,= r")) > + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] > + "TARGET_32BIT" > + "@ > + sbc%?\\t%0, %1, %2 > + rsc%?\\t%0, %2, %1" > + [(set_attr "conds" "use") > + (set_attr "predicable" "yes")] > +) > + > +(define_insn "*subsi3_carryin_const" > + [(set (match_operand:SI 0 "s_register_operand" "=3Dr") > + (minus:SI (plus:SI (match_operand:SI 1 "reg_or_int_operand" "r") > + (match_operand:SI 2 "arm_not_operand" "K")) > + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] > + "TARGET_32BIT" > + "sbc\\t%0, %1, #%B2" > + [(set_attr "conds" "use")] > +) > + > +(define_insn "*subsi3_carryin_compare" > + [(set (reg:CC CC_REGNUM) > + (compare:CC (match_operand:SI 1 "s_register_operand" "r") > + (match_operand:SI 2 "s_register_operand" "r"))) > + (set (match_operand:SI 0 "s_register_operand" "=3Dr") > + (minus:SI (minus:SI (match_dup 1) > + (match_dup 2)) > + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] > + "TARGET_32BIT" > + "sbcs\\t%0, %1, %2" > + [(set_attr "conds" "set")] > +) > + > +(define_insn "*subsi3_carryin_compare_const" > + [(set (reg:CC CC_REGNUM) > + (compare:CC (match_operand:SI 1 "reg_or_int_operand" "r") > + (match_operand:SI 2 "arm_not_operand" "K"))) > + (set (match_operand:SI 0 "s_register_operand" "=3Dr") > + (minus:SI (plus:SI (match_dup 1) > + (match_dup 2)) > + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] > + "TARGET_32BIT" > + "sbcs\\t%0, %1, #%B2" > + [(set_attr "conds" "set")] > +) > + > +(define_insn "*subsi3_carryin_shift" > + [(set (match_operand:SI 0 "s_register_operand" "=3Dr") > + (minus:SI (minus:SI > + (match_operand:SI 1 "s_register_operand" "r") > + (match_operator:SI 2 "shift_operator" > + [(match_operand:SI 3 "s_register_operand" "r") > + (match_operand:SI 4 "reg_or_int_operand" "rM")])) > + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] > + "TARGET_32BIT" > + "sbc%?\\t%0, %1, %3%S2" > + [(set_attr "conds" "use") > + (set_attr "predicable" "yes") > + (set (attr "type") (if_then_else (match_operand 4 "const_int_operand"= "") > + (const_string "alu_shift") > + (const_string "alu_shift_reg")))] > +) > + > +(define_insn "*rsbsi3_carryin_shift" > + [(set (match_operand:SI 0 "s_register_operand" "=3Dr") > + (minus:SI (minus:SI > + (match_operator:SI 2 "shift_operator" > + [(match_operand:SI 3 "s_register_operand" "r") > + (match_operand:SI 4 "reg_or_int_operand" "rM")]) > + (match_operand:SI 1 "s_register_operand" "r")) > + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] > + "TARGET_32BIT" > + "rsc%?\\t%0, %1, %3%S2" > + [(set_attr "conds" "use") > + (set_attr "predicable" "yes") > + (set (attr "type") (if_then_else (match_operand 4 "const_int_operand"= "") > + (const_string "alu_shift") > + (const_string "alu_shift_reg")))] > +) > + >