[PATCH][ARM][3/n] Partial IT block deprecation in ARMv8 AArch32 - atomics patterns

[PATCH][ARM][3/n] Partial IT block deprecation in ARMv8 AArch32 - atomics patterns

[Kyrylo Tkachov]

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Hi all,

This patch restricts predication for the various atomics patterns in
sync.md by using the new predicable_short_it mechanism. The load/store
exclusive and the acquire/release instructions cannot be contained
inside IT blocks in ARMv8 so the logic behind disabling their predicable
versions for ARMv8 Thumb mode is pretty straightforward.

Tested together with the other patches in the series by bootstrap on
Cortex-A15 and regtest arm-none-eabi on qemu and model.

Ok for trunk?

Thanks,
Kyrill

2013-06-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/sync.md (atomic_loaddi_1):
	Disable predication for arm_restrict_it.
	(arm_load_exclusive<mode>): Likewise.
	(arm_load_exclusivesi): Likewise.
	(arm_load_exclusivedi): Likewise.
	(arm_load_acquire_exclusive<mode>): Likewise.
	(arm_load_acquire_exclusivesi): Likewise.
	(arm_load_acquire_exclusivedi): Likewise.
	(arm_store_exclusive<mode>): Likewise.
	(arm_store_exclusive<mode>): Likewise.
	(arm_store_release_exclusivedi): Likewise.
	(arm_store_release_exclusive<mode>): Likewise.

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diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md
index 9802348..8f7bd71 100644
--- a/gcc/config/arm/sync.md
+++ b/gcc/config/arm/sync.md
@@ -124,7 +124,8 @@
 		   UNSPEC_LL))]
   "TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN"
   "ldrexd%?\t%0, %H0, %C1"
-  [(set_attr "predicable" "yes")])
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")])
 
 (define_expand "atomic_compare_and_swap<mode>"
   [(match_operand:SI 0 "s_register_operand" "")		;; bool out
@@ -361,7 +362,8 @@
 	    VUNSPEC_LL)))]
   "TARGET_HAVE_LDREXBH"
   "ldrex<sync_sfx>%?\t%0, %C1"
-  [(set_attr "predicable" "yes")])
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")])
 
 (define_insn "arm_load_acquire_exclusive<mode>"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
@@ -371,7 +373,8 @@
 	    VUNSPEC_LAX)))]
   "TARGET_HAVE_LDACQ"
   "ldaex<sync_sfx>%?\\t%0, %C1"
-  [(set_attr "predicable" "yes")])
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")])
 
 (define_insn "arm_load_exclusivesi"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
@@ -380,7 +383,8 @@
 	  VUNSPEC_LL))]
   "TARGET_HAVE_LDREX"
   "ldrex%?\t%0, %C1"
-  [(set_attr "predicable" "yes")])
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")])
 
 (define_insn "arm_load_acquire_exclusivesi"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
@@ -389,7 +393,8 @@
 	  VUNSPEC_LAX))]
   "TARGET_HAVE_LDACQ"
   "ldaex%?\t%0, %C1"
-  [(set_attr "predicable" "yes")])
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")])
 
 (define_insn "arm_load_exclusivedi"
   [(set (match_operand:DI 0 "s_register_operand" "=r")
@@ -398,7 +403,8 @@
 	  VUNSPEC_LL))]
   "TARGET_HAVE_LDREXD"
   "ldrexd%?\t%0, %H0, %C1"
-  [(set_attr "predicable" "yes")])
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")])
 
 (define_insn "arm_load_acquire_exclusivedi"
   [(set (match_operand:DI 0 "s_register_operand" "=r")
@@ -407,7 +413,8 @@
 	  VUNSPEC_LAX))]
   "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN"
   "ldaexd%?\t%0, %H0, %C1"
-  [(set_attr "predicable" "yes")])
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")])
 
 (define_insn "arm_store_exclusive<mode>"
   [(set (match_operand:SI 0 "s_register_operand" "=&r")
@@ -431,7 +438,8 @@
       }
     return "strex<sync_sfx>%?\t%0, %2, %C1";
   }
-  [(set_attr "predicable" "yes")])
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")])
 
 (define_insn "arm_store_release_exclusivedi"
   [(set (match_operand:SI 0 "s_register_operand" "=&r")
@@ -448,7 +456,8 @@
     operands[3] = gen_rtx_REG (SImode, REGNO (value) + 1);
     return "stlexd%?\t%0, %2, %3, %C1";
   }
-  [(set_attr "predicable" "yes")])
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")])
 
 (define_insn "arm_store_release_exclusive<mode>"
   [(set (match_operand:SI 0 "s_register_operand" "=&r")
@@ -459,4 +468,5 @@
 	  VUNSPEC_SLX))]
   "TARGET_HAVE_LDACQ"
   "stlex<sync_sfx>%?\t%0, %2, %C1"
-  [(set_attr "predicable" "yes")])
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")])

Re: [PATCH][ARM][3/n] Partial IT block deprecation in ARMv8 AArch32 - atomics patterns

[Richard Earnshaw]

On 05/06/13 17:49, Kyrylo Tkachov wrote:
> Hi all,
>
> This patch restricts predication for the various atomics patterns in
> sync.md by using the new predicable_short_it mechanism. The load/store
> exclusive and the acquire/release instructions cannot be contained
> inside IT blocks in ARMv8 so the logic behind disabling their predicable
> versions for ARMv8 Thumb mode is pretty straightforward.
>
> Tested together with the other patches in the series by bootstrap on
> Cortex-A15 and regtest arm-none-eabi on qemu and model.
>
> Ok for trunk?
>
> Thanks,
> Kyrill
>
> 2013-06-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
>
> 	* config/arm/sync.md (atomic_loaddi_1):
> 	Disable predication for arm_restrict_it.
> 	(arm_load_exclusive<mode>): Likewise.
> 	(arm_load_exclusivesi): Likewise.
> 	(arm_load_exclusivedi): Likewise.
> 	(arm_load_acquire_exclusive<mode>): Likewise.
> 	(arm_load_acquire_exclusivesi): Likewise.
> 	(arm_load_acquire_exclusivedi): Likewise.
> 	(arm_store_exclusive<mode>): Likewise.
> 	(arm_store_exclusive<mode>): Likewise.
> 	(arm_store_release_exclusivedi): Likewise.
> 	(arm_store_release_exclusive<mode>): Likewise.
>
>

OK.

R.