[Patch, AArch64, ILP32] 0/5 Add support for ILP32

[Patch, AArch64, ILP32] 0/5 Add support for ILP32

[Yufeng Zhang]

Hi,

A set of five patches will be sent shortly as the gcc part of changes 
that add support for ILP32 in the AArch64 baremetal toolchain.

The five patches will be organized as the following:

1. Configury changes;

2. AArch64 backend changes that add necessary instruction patterns and 
update the backend macros and hooks to support ILP32;

3. Minor change to the generic part of the compiler to enable correct 
pass-by-reference parameter passing;

4. Changes to a number of tests for them to be ILP32-friendly;

5. Define _ILP32 and __ILP32__.

The patch set will enable the basic ILP32 support in the baremetal 
environment, with small absolute and small PIC as the supported 
addressing models.

Patches for binutils changes have been committed to the binutils trunk; 
they were previously posted here: 
http://sourceware.org/ml/binutils/2013-06/msg00176.html


Thanks,
Yufeng

[Patch, AArch64, ILP32] 1/5 Initial support - configury changes

[Yufeng Zhang]

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This patch adds the configuration changes to the AArch64 GCC to support:

* -milp32 and -mlp64 options in the compiler and the driver
* multilib of ilp32 and/or lp64 libraries
* differentiation of basic types in the compiler backend

The patch enables --with-multilib-list configuration option for 
specifying the list of library flavors to enable; the default value is 
"mlp64" and can be overridden by --with-abi to "milp32".

It also enables --with-abi for setting the default model in the 
compiler.  Its default value is "mlp64" unless --with-multilib-list is 
explicitly specified with "milp32", in which case it defaults to "milp32".

In the backend, two target flags are introduced: TARGET_ILP32 and 
TARGET_LP64.  They are set by -milp32 and -mlp64 respectively, exclusive 
to each other.  The default setting is via the option variable 
aarch64_pmodel_flags, which defaults to TARGET_DEFAULT_PMODEL, which is 
further defined in biarchlp64.h or biarchilp32.h depending which header 
file is included.

                           biarchlp64.h         biarchilp32.h
TARGET_DEFAULT_PMODEL     OPTION_MASK_LP64     OPTION_MASK_ILP32
TARGET_PMODEL             1                    2

TARGET_ILP32 and TARGET_LP64 are implicitly defined as:

#define TARGET_ILP32 ((aarch64_pmodel_flags & OPTION_MASK_ILP32) != 0)
#define TARGET_LP64 ((aarch64_pmodel_flags & OPTION_MASK_LP64) != 0)

Note that the multilib support in the Linux toolchain is suppressed 
deliberately.

OK for the trunk?

Thanks,
Yufeng


gcc/
	* config.gcc (aarch64*-*-*): Support --with-abi.
	(aarch64*-*-elf): Support --with-multilib-list.
	(aarch64*-*-linux*): Likewise.
	(supported_defaults): Add abi to aarch64*-*-*.
	* configure.ac: Mention AArch64 for --with-multilib-list.
	* configure: Re-generated.
	* config/aarch64/biarchilp32.h: New file.
	* config/aarch64/biarchlp64.h: New file.
	* config/aarch64/aarch64-elf.h (SPEC_LP64): New define.
	(SPEC_ILP32): Ditto.
	(ASM_SPEC): Update to SPEC_LP64 and SPEC_ILP32.
	(MULTILIB_DEFAULTS): New define.
	* config/aarch64/aarch64-elf-raw.h (EMUL_SUFFIX): New define.
	(LINK_SPEC): Change to depend on SPEC_LP64 and SPEC_ILP32 and also
	to use EMUL_SUFFIX.
	* config/aarch64/aarch64.h (LONG_TYPE_SIZE): Change to depend on
	TARGET_ILP32.
	(POINTER_SIZE): New define.
	(POINTERS_EXTEND_UNSIGNED): Ditto.
	* config/aarch64/aarch64.c (initialize_aarch64_programming_model):
	New declaration and definition.
	(aarch64_override_options): Call the new function.
	* config/aarch64/aarch64.opt (aarch64_pmodel_flags): New.
	(milp32, mlp64): New.
	* config/aarch64/t-aarch64 (comma): New define.
	(MULTILIB_OPTIONS): Ditto.
	(MULTILIB_DIRNAMES): Ditto.
	* config/aarch64/t-aarch64-linux (MULTIARCH_DIRNAME): New define.


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diff --git a/gcc/config.gcc b/gcc/config.gcc
index 0ad7217..c8af44e 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -497,6 +497,26 @@ then
 fi
 
 case ${target} in
+aarch64*-*-*)
+	case ${with_abi} in
+	"")
+		if test "x$with_multilib_list" = xmilp32; then
+			tm_file="aarch64/biarchilp32.h ${tm_file}"
+		else
+			tm_file="aarch64/biarchlp64.h ${tm_file}"
+		fi
+		;;
+	lp64 | mlp64)
+		tm_file="aarch64/biarchlp64.h ${tm_file}"
+		;;
+	ilp32 | milp32)
+		tm_file="aarch64/biarchilp32.h ${tm_file}"
+		;;
+	*)
+		echo "Unknown ABI used in --with-abi=$with_abi"
+		exit 1
+	esac
+	;;
 i[34567]86-*-*)
 	if test "x$with_abi" != x; then
 		echo "This target does not support --with-abi."
@@ -827,6 +847,32 @@ aarch64*-*-elf)
 		tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
 		;;
 	esac
+	aarch64_multilibs="${with_multilib_list}"
+	if test "$aarch64_multilibs" = "default"; then
+		case ${with_abi} in
+		ilp32 | milp32)
+			aarch64_multilibs="milp32"
+			;;
+		*)
+			# TODO: Change to build both flavours by default when
+			# the ILP32 support is mature enough.
+			# aarch64_multilibs="mlp64,milp32"
+			aarch64_multilibs="mlp64"
+			;;
+		esac
+	fi
+	aarch64_multilibs=`echo $aarch64_multilibs | sed -e 's/,/ /g'`
+	for aarch64_multilib in ${aarch64_multilibs}; do
+		case ${aarch64_multilib} in
+		milp32 | mlp64 )
+			TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG},${aarch64_multilib}"
+			;;
+		*)
+			echo "--with-multilib-list=${aarch64_multilib} not supported."
+			exit 1
+		esac
+	done
+	TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's/^,//'`
 	;;
 aarch64*-*-linux*)
 	tm_file="${tm_file} dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h"
@@ -837,6 +883,32 @@ aarch64*-*-linux*)
 		tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
 		;;
 	esac
+	aarch64_multilibs="${with_multilib_list}"
+	if test "$aarch64_multilibs" = "default"; then
+		case ${with_abi} in
+		ilp32 | milp32)
+			aarch64_multilibs="milp32"
+			;;
+		*)
+			# TODO: Change to build both flavours by default when
+			# the ILP32 support is mature enough.
+			# aarch64_multilibs="mlp64,milp32"
+			aarch64_multilibs="mlp64"
+			;;
+		esac
+	fi
+	aarch64_multilibs=`echo $aarch64_multilibs | sed -e 's/,/ /g'`
+	for aarch64_multilib in ${aarch64_multilibs}; do
+		case ${aarch64_multilib} in
+		milp32 | mlp64 )
+			TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG},${aarch64_multilib}"
+			;;
+		*)
+			echo "--with-multilib-list=${aarch64_multilib} not supported."
+			exit 1
+		esac
+	done
+	TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's/^,//'`
 	;;
 alpha*-*-linux*)
 	tm_file="elfos.h ${tm_file} alpha/elf.h alpha/linux.h alpha/linux-elf.h glibc-stdint.h"
@@ -3147,7 +3219,7 @@ fi
 supported_defaults=
 case "${target}" in
 	aarch64*-*-*)
-		supported_defaults="cpu arch"
+		supported_defaults="abi cpu arch"
 		for which in cpu arch; do
 
 			eval "val=\$with_$which"
diff --git a/gcc/config/aarch64/aarch64-elf-raw.h b/gcc/config/aarch64/aarch64-elf-raw.h
index 1cd0155..4bef8a6 100644
--- a/gcc/config/aarch64/aarch64-elf-raw.h
+++ b/gcc/config/aarch64/aarch64-elf-raw.h
@@ -25,8 +25,17 @@
 #define STARTFILE_SPEC " crti%O%s crtbegin%O%s crt0%O%s"
 #define ENDFILE_SPEC " crtend%O%s crtn%O%s"
 
+#if TARGET_BIG_ENDIAN_DEFAULT == 1
+#define EMUL_SUFFIX "b"
+#else
+#define EMUL_SUFFIX ""
+#endif
+
 #ifndef LINK_SPEC
-#define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X"
+#define LINK_SPEC "\
+%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \
+%{" SPEC_LP64 ":-m aarch64elf" EMUL_SUFFIX "} \
+%{" SPEC_ILP32 ":-m aarch64elf32" EMUL_SUFFIX "}"
 #endif
 
 #endif /* GCC_AARCH64_ELF_RAW_H */
diff --git a/gcc/config/aarch64/aarch64-elf.h b/gcc/config/aarch64/aarch64-elf.h
index 3f3ae52..ff1a730 100644
--- a/gcc/config/aarch64/aarch64-elf.h
+++ b/gcc/config/aarch64/aarch64-elf.h
@@ -111,12 +111,24 @@
 
 #define GLOBAL_ASM_OP "\t.global\t"
 
+#if TARGET_PMODEL == 2
+/* Default ILP32.  */
+#define SPEC_LP64  "mlp64"
+#define SPEC_ILP32 "mlp64:;"
+#else
+/* Default LP64.  */
+#define SPEC_LP64  "milp32:;"
+#define SPEC_ILP32 "milp32"
+#endif
+
 #ifndef ASM_SPEC
 #define ASM_SPEC "\
 %{mbig-endian:-EB} \
 %{mlittle-endian:-EL} \
 %{mcpu=*:-mcpu=%*} \
-%{march=*:-march=%*}"
+%{march=*:-march=%*} \
+%{" SPEC_ILP32 ":-milp32} \
+%{" SPEC_LP64 ":-mlp64}"
 #endif
 
 #undef TYPE_OPERAND_FMT
@@ -128,4 +140,10 @@
 /* Stabs debug not required.  */
 #undef DBX_DEBUGGING_INFO
 
+#if TARGET_PMODEL == 2
+#define MULTILIB_DEFAULTS { "milp32" }
+#else
+#define MULTILIB_DEFAULTS { "mlp64" }
+#endif
+
 #endif /* GCC_AARCH64_ELF_H */
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 527b00d..9d60225 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4715,6 +4715,8 @@ aarch64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
 
 static void initialize_aarch64_code_model (void);
 
+static void initialize_aarch64_programming_model (void);
+
 /* Parse the architecture extension string.  */
 
 static void
@@ -4931,6 +4933,8 @@ aarch64_override_options (void)
 
   initialize_aarch64_code_model ();
 
+  initialize_aarch64_programming_model ();
+
   aarch64_build_bitmask_table ();
 
   /* This target defaults to strict volatile bitfields.  */
@@ -5016,6 +5020,29 @@ initialize_aarch64_code_model (void)
      aarch64_cmodel = aarch64_cmodel_var;
 }
 
+/* A checking mechanism for the implementation of the various programming
+   models.  */
+
+static void
+initialize_aarch64_programming_model (void)
+{
+#if TARGET_PMODEL == 1
+  /* When TARGET_PMODEL == 1, by default, OPTION_MASK_LP64
+     is on and OPTION_MASK_ILP32 is off.  We turn off
+     OPTION_MASK_LP64 if OPTION_MASK_ILP32 is turned on by
+     -milp32.  */
+  if (TARGET_ILP32)
+    aarch64_pmodel_flags &= ~OPTION_MASK_LP64;
+#else
+  /* When TARGET_PMODEL == 2, by default, OPTION_MASK_ILP32 is
+     on and OPTION_MASK_LP64 is off.  We turn off
+     OPTION_MASK_ILP32 if OPTION_MASK_LP64 is turned on by
+     -mlp64.  */
+  if (TARGET_LP64)
+    aarch64_pmodel_flags &= ~OPTION_MASK_ILP32;
+#endif
+}
+
 /* Return true if SYMBOL_REF X binds locally.  */
 
 static bool
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index a08797b..cfdb120 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -95,7 +95,9 @@
 
 #define INT_TYPE_SIZE		32
 
-#define LONG_TYPE_SIZE		64	/* XXX This should be an option */
+#define LONG_TYPE_SIZE		(TARGET_ILP32 ? 32 : 64)
+
+#define POINTER_SIZE		(TARGET_ILP32 ? 32 : 64)
 
 #define LONG_LONG_TYPE_SIZE	64
 
@@ -704,7 +706,18 @@ do {									     \
 
 #define NO_FUNCTION_CSE	1
 
+/* Specify the machine mode that the hardware addresses have.
+   After generation of rtl, the compiler makes no further distinction
+   between pointers and any other objects of this machine mode.  */
 #define Pmode		DImode
+
+/* A C expression whose value is zero if pointers that need to be extended
+   from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
+   greater then zero if they are zero-extended and less then zero if the
+   ptr_extend instruction should be used.  */
+#define POINTERS_EXTEND_UNSIGNED 1
+
+/* Mode of a function address in a call instruction (for indexing purposes).  */
 #define FUNCTION_MODE	Pmode
 
 #define SELECT_CC_MODE(OP, X, Y)	aarch64_select_cc_mode (OP, X, Y)
diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
index 3518248..cf97c8d 100644
--- a/gcc/config/aarch64/aarch64.opt
+++ b/gcc/config/aarch64/aarch64.opt
@@ -59,6 +59,10 @@ const char *aarch64_cpu_string
 Variable
 const char *aarch64_tune_string
 
+; Bit flags that specify the programming model we are compiling with.
+Variable
+HOST_WIDE_INT aarch64_pmodel_flags = TARGET_DEFAULT_PMODEL
+
 mbig-endian
 Target Report RejectNegative Mask(BIG_END)
 Assume target CPU is configured as big endian
@@ -98,3 +102,11 @@ Target RejectNegative Joined Var(aarch64_cpu_string)
 mtune=
 Target RejectNegative Joined Var(aarch64_tune_string)
 -mtune=CPU	Optimize for CPU
+
+milp32
+Target Report RejectNegative Negative(mlp64) Mask(ILP32) Var(aarch64_pmodel_flags) Save
+Generate code using the ILP32 data model
+
+mlp64
+Target Report RejectNegative Negative(milp32) Mask(LP64) Var(aarch64_pmodel_flags) Save
+Generate code using the LP64 data model
diff --git a/gcc/config/aarch64/biarchilp32.h b/gcc/config/aarch64/biarchilp32.h
new file mode 100644
index 0000000..ad87840
--- /dev/null
+++ b/gcc/config/aarch64/biarchilp32.h
@@ -0,0 +1,29 @@
+/* Make configure files to produce biarch compiler defaulting to ilp32 ABI.
+   This file must be included very first, while the OS specific file later
+   to overwrite otherwise wrong defaults. 
+   Copyright (C) 2013 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+<http://www.gnu.org/licenses/>.  */
+
+#define TARGET_DEFAULT_PMODEL OPTION_MASK_ILP32
+#define TARGET_PMODEL 2
diff --git a/gcc/config/aarch64/biarchlp64.h b/gcc/config/aarch64/biarchlp64.h
new file mode 100644
index 0000000..87a592b
--- /dev/null
+++ b/gcc/config/aarch64/biarchlp64.h
@@ -0,0 +1,29 @@
+/* Make configure files to produce biarch compiler defaulting to ilp64 ABI.
+   This file must be included very first, while the OS specific file later
+   to overwrite otherwise wrong defaults. 
+   Copyright (C) 2013 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+<http://www.gnu.org/licenses/>.  */
+
+#define TARGET_DEFAULT_PMODEL OPTION_MASK_LP64
+#define TARGET_PMODEL 1
diff --git a/gcc/config/aarch64/t-aarch64 b/gcc/config/aarch64/t-aarch64
index 4c265eb..d300b12 100644
--- a/gcc/config/aarch64/t-aarch64
+++ b/gcc/config/aarch64/t-aarch64
@@ -34,3 +34,7 @@ aarch64-builtins.o: $(srcdir)/config/aarch64/aarch64-builtins.c $(CONFIG_H) \
   $(srcdir)/config/aarch64/aarch64-simd-builtins.def
 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
 		$(srcdir)/config/aarch64/aarch64-builtins.c
+
+comma=,
+MULTILIB_OPTIONS    = $(subst $(comma),/,$(TM_MULTILIB_CONFIG))
+MULTILIB_DIRNAMES   = $(patsubst m%, %, $(subst /, ,$(MULTILIB_OPTIONS)))
diff --git a/gcc/config/aarch64/t-aarch64-linux b/gcc/config/aarch64/t-aarch64-linux
index a7a0a88..ca1525e 100644
--- a/gcc/config/aarch64/t-aarch64-linux
+++ b/gcc/config/aarch64/t-aarch64-linux
@@ -23,3 +23,9 @@ LIB1ASMFUNCS = _aarch64_sync_cache_range
 
 AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be)
 MULTILIB_OSDIRNAMES = .=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
+MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
+
+# Disable the multilib for linux-gnu targets for the time being; focus
+# on the baremetal targets.
+MULTILIB_OPTIONS    =
+MULTILIB_DIRNAMES   =
diff --git a/gcc/configure.ac b/gcc/configure.ac
index eff48d6..6bad7d5 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -839,7 +839,7 @@ esac],
 [enable_languages=c])
 
 AC_ARG_WITH(multilib-list,
-[AS_HELP_STRING([--with-multilib-list], [select multilibs (SH and x86-64 only)])],
+[AS_HELP_STRING([--with-multilib-list], [select multilibs (AArch64, SH and x86-64 only)])],
 :,
 with_multilib_list=default)
 

[Patch, AArch64, ILP32] 2/5 More backend changes and support for small absolute and small PIC addressing models

[Yufeng Zhang]

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This patch updates the AArch64 backend to support the small absolute and 
small PIC addressing models for ILP32; it also updates a number of other 
backend macros and hooks in order to support ILP32.

OK for the trunk?

Thanks,
Yufeng


gcc/

         * config/aarch64/aarch64.c (POINTER_BYTES): New define.
         (aarch64_load_symref_appropriately): In the case of
         SYMBOL_SMALL_ABSOLUTE, use the mode of 'dest' instead of Pmode
         to generate new rtx; likewise to the case of SYMBOL_SMALL_GOT.
         (aarch64_expand_mov_immediate): In the case of SYMBOL_FORCE_TO_MEM,
         change to pass 'ptr_mode' to force_const_mem and zero-extend 'mem'
         if 'mode' doesn't equal to 'ptr_mode'.
         (aarch64_output_mi_thunk): Add an assertion on the alignment of
         'vcall_offset'; change to call aarch64_emit_move differently 
depending
         on whether 'Pmode' equals to 'ptr_mode' or not; use 'POINTER_BYTES'
         to calculate the upper bound of 'vcall_offset'.
         (aarch64_cannot_force_const_mem): Change to also return true if
         mode != ptr_mode.
         (aarch64_legitimize_reload_address): In the case of large
         displacements, add new local variable 'xmode' and an assertion
         based on it; change to use 'xmode' to generate the new rtx and
         reload.
         (aarch64_asm_trampoline_template): Change to generate the template
         differently depending on TARGET_ILP32 or not; change to use
         'POINTER_BYTES' in the argument passed to assemble_aligned_integer.
         (aarch64_trampoline_size): Removed.
         (aarch64_trampoline_init): Add new local constant 'tramp_code_sz'
         and replace immediate literals with it.  Change to use 'ptr_mode'
         instead of 'DImode' and call convert_memory_address if the mode
         of 'fnaddr' doesn't equal to 'ptr_mode'.
         (aarch64_elf_asm_constructor): Change to use 
assemble_aligned_integer
         to output symbol.
         (aarch64_elf_asm_destructor): Likewise.
         * config/aarch64/aarch64.h (TRAMPOLINE_SIZE): Change to be 
dependent
         on TARGET_ILP32 instead of aarch64_trampoline_size.
         * config/aarch64/aarch64.md (movsi_aarch64): Add new alternatives
         of 'mov' between WSP and W registers as well as 'adr' and 'adrp'.
         (loadwb_pair<GPI:mode>_<PTR:mode>): Rename to ...
         (loadwb_pair<GPI:mode>_<P:mode>): ... this.  Replace PTR with P.
         (storewb_pair<GPI:mode>_<PTR:mode>): Likewise; rename to ...
         (storewb_pair<GPI:mode>_<P:mode>): ... this.
         (add_losym): Change to 'define_expand' and call 
gen_add_losym_<mode>
         depending on the value of 'mode'.
         (add_losym_<mode>): New.
         (ldr_got_small_<mode>): New, based on ldr_got_small.
         (ldr_got_small): Remove.
         (ldr_got_small_sidi): New.
         * config/aarch64/iterators.md (P): New.
         (PTR): Change to 'ptr_mode' in the condition.


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diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index c16d55f..1117515 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -46,6 +46,9 @@
 #include "optabs.h"
 #include "dwarf2.h"
 
+/* Defined for convenience.  */
+#define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
+
 /* Classifies an address.
 
    ADDRESS_REG_IMM
@@ -519,13 +522,16 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
     {
     case SYMBOL_SMALL_ABSOLUTE:
       {
+	/* In ILP32, the mode of dest can be either SImode or DImode.  */
 	rtx tmp_reg = dest;
+	enum machine_mode mode = GET_MODE (dest);
+
+	gcc_assert (mode == Pmode || mode == ptr_mode);
+
 	if (can_create_pseudo_p ())
-	  {
-	    tmp_reg =  gen_reg_rtx (Pmode);
-	  }
+	  tmp_reg = gen_reg_rtx (mode);
 
-	emit_move_insn (tmp_reg, gen_rtx_HIGH (Pmode, imm));
+	emit_move_insn (tmp_reg, gen_rtx_HIGH (mode, imm));
 	emit_insn (gen_add_losym (dest, tmp_reg, imm));
 	return;
       }
@@ -536,11 +542,33 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
 
     case SYMBOL_SMALL_GOT:
       {
+	/* In ILP32, the mode of dest can be either SImode or DImode,
+	   while the got entry is always of SImode size.  The mode of
+	   dest depends on how dest is used: if dest is assigned to a
+	   pointer (e.g. in the memory), it has SImode; it may have
+	   DImode if dest is dereferenced to access the memeory.
+	   This is why we have to handle three different ldr_got_small
+	   patterns here (two patterns for ILP32).  */
 	rtx tmp_reg = dest;
+	enum machine_mode mode = GET_MODE (dest);
+
 	if (can_create_pseudo_p ())
-	  tmp_reg =  gen_reg_rtx (Pmode);
-	emit_move_insn (tmp_reg, gen_rtx_HIGH (Pmode, imm));
-	emit_insn (gen_ldr_got_small (dest, tmp_reg, imm));
+	  tmp_reg = gen_reg_rtx (mode);
+
+	emit_move_insn (tmp_reg, gen_rtx_HIGH (mode, imm));
+	if (mode == ptr_mode)
+	  {
+	    if (mode == DImode)
+	      emit_insn (gen_ldr_got_small_di (dest, tmp_reg, imm));
+	    else
+	      emit_insn (gen_ldr_got_small_si (dest, tmp_reg, imm));
+	  }
+	else
+	  {
+	    gcc_assert (mode == Pmode);
+	    emit_insn (gen_ldr_got_small_sidi (dest, tmp_reg, imm));
+	  }
+
 	return;
       }
 
@@ -857,8 +885,10 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
 	      aarch64_emit_move (dest, base);
 	      return;
 	    }
-	  mem = force_const_mem (mode, imm);
+	  mem = force_const_mem (ptr_mode, imm);
 	  gcc_assert (mem);
+	  if (mode != ptr_mode)
+	    mem = gen_rtx_ZERO_EXTEND (mode, mem);
 	  emit_insn (gen_rtx_SET (VOIDmode, dest, mem));
 	  return;
 
@@ -2489,7 +2519,7 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
     aarch64_add_constant (this_regno, IP1_REGNUM, delta);
   else
     {
-      gcc_assert ((vcall_offset & 0x7) == 0);
+      gcc_assert ((vcall_offset & (POINTER_BYTES - 1)) == 0);
 
       this_rtx = gen_rtx_REG (Pmode, this_regno);
       temp0 = gen_rtx_REG (Pmode, IP0_REGNUM);
@@ -2505,9 +2535,14 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
 	    aarch64_add_constant (this_regno, IP1_REGNUM, delta);
 	}
 
-      aarch64_emit_move (temp0, gen_rtx_MEM (Pmode, addr));
+      if (Pmode == ptr_mode)
+	aarch64_emit_move (temp0, gen_rtx_MEM (ptr_mode, addr));
+      else
+	aarch64_emit_move (temp0,
+			   gen_rtx_ZERO_EXTEND (Pmode,
+						gen_rtx_MEM (ptr_mode, addr)));
 
-      if (vcall_offset >= -256 && vcall_offset < 32768)
+      if (vcall_offset >= -256 && vcall_offset < 4096 * POINTER_BYTES)
 	  addr = plus_constant (Pmode, temp0, vcall_offset);
       else
 	{
@@ -2515,7 +2550,13 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
 	  addr = gen_rtx_PLUS (Pmode, temp0, temp1);
 	}
 
-      aarch64_emit_move (temp1, gen_rtx_MEM (Pmode,addr));
+      if (Pmode == ptr_mode)
+	aarch64_emit_move (temp1, gen_rtx_MEM (ptr_mode,addr));
+      else
+	aarch64_emit_move (temp1,
+			   gen_rtx_SIGN_EXTEND (Pmode,
+						gen_rtx_MEM (ptr_mode, addr)));
+
       emit_insn (gen_add2_insn (this_rtx, temp1));
     }
 
@@ -2692,7 +2733,14 @@ aarch64_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
 
   split_const (x, &base, &offset);
   if (GET_CODE (base) == SYMBOL_REF || GET_CODE (base) == LABEL_REF)
-    return (aarch64_classify_symbol (base, SYMBOL_CONTEXT_ADR) != SYMBOL_FORCE_TO_MEM);
+    {
+      if (aarch64_classify_symbol (base, SYMBOL_CONTEXT_ADR) != SYMBOL_FORCE_TO_MEM)
+	return true;
+      else
+	/* Avoid generating a 64-bit relocation in ILP32; leave
+	   to aarch64_expand_mov_immediate to handle it properly.  */
+	return mode != ptr_mode;
+    }
 
   return aarch64_tls_referenced_p (x);
 }
@@ -3876,6 +3924,10 @@ aarch64_legitimize_reload_address (rtx *x_p,
       HOST_WIDE_INT high = val - low;
       HOST_WIDE_INT offs;
       rtx cst;
+      enum machine_mode xmode = GET_MODE (x);
+
+      /* In ILP32, xmode can be either DImode or SImode.  */
+      gcc_assert (xmode == DImode || xmode == SImode);
 
       /* Reload non-zero BLKmode offsets.  This is because we cannot ascertain
 	 BLKmode alignment.  */
@@ -3909,16 +3961,16 @@ aarch64_legitimize_reload_address (rtx *x_p,
 
       cst = GEN_INT (high);
       if (!aarch64_uimm12_shift (high))
-	cst = force_const_mem (Pmode, cst);
+	cst = force_const_mem (xmode, cst);
 
       /* Reload high part into base reg, leaving the low part
 	 in the mem instruction.  */
-      x = gen_rtx_PLUS (Pmode,
-			gen_rtx_PLUS (Pmode, XEXP (x, 0), cst),
+      x = gen_rtx_PLUS (xmode,
+			gen_rtx_PLUS (xmode, XEXP (x, 0), cst),
 			GEN_INT (low));
 
       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
-		   BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
+		   BASE_REG_CLASS, xmode, VOIDmode, 0, 0,
 		   opnum, (enum reload_type) type);
       return x;
     }
@@ -4066,41 +4118,47 @@ aarch64_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
 static void
 aarch64_asm_trampoline_template (FILE *f)
 {
-  asm_fprintf (f, "\tldr\t%s, .+16\n", reg_names [IP1_REGNUM]);
-  asm_fprintf (f, "\tldr\t%s, .+20\n", reg_names [STATIC_CHAIN_REGNUM]);
+  if (TARGET_ILP32)
+    {
+      asm_fprintf (f, "\tldr\tw%d, .+16\n", IP1_REGNUM - R0_REGNUM);
+      asm_fprintf (f, "\tldr\tw%d, .+16\n", STATIC_CHAIN_REGNUM - R0_REGNUM);
+    }
+  else
+    {
+      asm_fprintf (f, "\tldr\t%s, .+16\n", reg_names [IP1_REGNUM]);
+      asm_fprintf (f, "\tldr\t%s, .+20\n", reg_names [STATIC_CHAIN_REGNUM]);
+    }
   asm_fprintf (f, "\tbr\t%s\n", reg_names [IP1_REGNUM]);
   assemble_aligned_integer (4, const0_rtx);
-  assemble_aligned_integer (UNITS_PER_WORD, const0_rtx);
-  assemble_aligned_integer (UNITS_PER_WORD, const0_rtx);
-}
-
-unsigned
-aarch64_trampoline_size (void)
-{
-  return 32;  /* 3 insns + padding + 2 dwords.  */
+  assemble_aligned_integer (POINTER_BYTES, const0_rtx);
+  assemble_aligned_integer (POINTER_BYTES, const0_rtx);
 }
 
 static void
 aarch64_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
 {
   rtx fnaddr, mem, a_tramp;
+  const int tramp_code_sz = 16;
 
   /* Don't need to copy the trailing D-words, we fill those in below.  */
   emit_block_move (m_tramp, assemble_trampoline_template (),
-		   GEN_INT (TRAMPOLINE_SIZE - 16), BLOCK_OP_NORMAL);
-  mem = adjust_address (m_tramp, DImode, 16);
+		   GEN_INT (tramp_code_sz), BLOCK_OP_NORMAL);
+  mem = adjust_address (m_tramp, ptr_mode, tramp_code_sz);
   fnaddr = XEXP (DECL_RTL (fndecl), 0);
+  if (GET_MODE (fnaddr) != ptr_mode)
+    fnaddr = convert_memory_address (ptr_mode, fnaddr);
   emit_move_insn (mem, fnaddr);
 
-  mem = adjust_address (m_tramp, DImode, 24);
+  mem = adjust_address (m_tramp, ptr_mode, tramp_code_sz + POINTER_BYTES);
   emit_move_insn (mem, chain_value);
 
   /* XXX We should really define a "clear_cache" pattern and use
      gen_clear_cache().  */
   a_tramp = XEXP (m_tramp, 0);
   emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"),
-		     LCT_NORMAL, VOIDmode, 2, a_tramp, Pmode,
-		     plus_constant (Pmode, a_tramp, TRAMPOLINE_SIZE), Pmode);
+		     LCT_NORMAL, VOIDmode, 2, a_tramp, ptr_mode,
+		     plus_constant (ptr_mode, a_tramp, TRAMPOLINE_SIZE),
+		     ptr_mode);
 }
 
 static unsigned char
@@ -4155,9 +4213,7 @@ aarch64_elf_asm_constructor (rtx symbol, int priority)
       s = get_section (buf, SECTION_WRITE, NULL);
       switch_to_section (s);
       assemble_align (POINTER_SIZE);
-      fputs ("\t.dword\t", asm_out_file);
-      output_addr_const (asm_out_file, symbol);
-      fputc ('\n', asm_out_file);
+      assemble_aligned_integer (POINTER_BYTES, symbol);
     }
 }
 
@@ -4174,9 +4230,7 @@ aarch64_elf_asm_destructor (rtx symbol, int priority)
       s = get_section (buf, SECTION_WRITE, NULL);
       switch_to_section (s);
       assemble_align (POINTER_SIZE);
-      fputs ("\t.dword\t", asm_out_file);
-      output_addr_const (asm_out_file, symbol);
-      fputc ('\n', asm_out_file);
+      assemble_aligned_integer (POINTER_BYTES, symbol);
     }
 }
 
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index cfdb120..d27d20f 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -738,7 +738,8 @@ do {									     \
 
 #define RETURN_ADDR_RTX aarch64_return_addr
 
-#define TRAMPOLINE_SIZE	aarch64_trampoline_size ()
+/* 3 insns + padding + 2 pointer-sized entries.  */
+#define TRAMPOLINE_SIZE	(TARGET_ILP32 ? 24 : 32)
 
 /* Trampolines contain dwords, so must be dword aligned.  */
 #define TRAMPOLINE_ALIGNMENT 64
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index e88e5be..b6f05f6 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -826,23 +826,27 @@
 )
 
 (define_insn "*movsi_aarch64"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,*w,m,  m,*w, r,*w")
-	(match_operand:SI 1 "aarch64_mov_operand"  " r,M,m, m,rZ,*w,rZ,*w,*w"))]
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,k,r,r,r,*w,m,  m,r,r  ,*w, r,*w")
+	(match_operand:SI 1 "aarch64_mov_operand"  " r,r,k,M,m, m,rZ,*w,S,Ush,rZ,*w,*w"))]
   "(register_operand (operands[0], SImode)
     || aarch64_reg_or_zero (operands[1], SImode))"
   "@
    mov\\t%w0, %w1
+   mov\\t%w0, %w1
+   mov\\t%w0, %w1
    mov\\t%w0, %1
    ldr\\t%w0, %1
    ldr\\t%s0, %1
    str\\t%w1, %0
    str\\t%s1, %0
+   adr\\t%x0, %a1
+   adrp\\t%x0, %A1
    fmov\\t%s0, %w1
    fmov\\t%w0, %s1
    fmov\\t%s0, %s1"
-  [(set_attr "v8type" "move,alu,load1,load1,store1,store1,fmov,fmov,fmov")
+  [(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov")
    (set_attr "mode" "SI")
-   (set_attr "fp" "*,*,*,yes,*,yes,yes,yes,yes")]
+   (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")]
 )
 
 (define_insn "*movdi_aarch64"
@@ -1107,17 +1111,17 @@
 
 ;; Load pair with writeback.  This is primarily used in function epilogues
 ;; when restoring [fp,lr]
-(define_insn "loadwb_pair<GPI:mode>_<PTR:mode>"
+(define_insn "loadwb_pair<GPI:mode>_<P:mode>"
   [(parallel
-    [(set (match_operand:PTR 0 "register_operand" "=k")
-          (plus:PTR (match_operand:PTR 1 "register_operand" "0")
-                  (match_operand:PTR 4 "const_int_operand" "n")))
+    [(set (match_operand:P 0 "register_operand" "=k")
+          (plus:P (match_operand:P 1 "register_operand" "0")
+                  (match_operand:P 4 "const_int_operand" "n")))
      (set (match_operand:GPI 2 "register_operand" "=r")
-          (mem:GPI (plus:PTR (match_dup 1)
+          (mem:GPI (plus:P (match_dup 1)
                    (match_dup 4))))
      (set (match_operand:GPI 3 "register_operand" "=r")
-          (mem:GPI (plus:PTR (match_dup 1)
-                   (match_operand:PTR 5 "const_int_operand" "n"))))])]
+          (mem:GPI (plus:P (match_dup 1)
+                   (match_operand:P 5 "const_int_operand" "n"))))])]
   "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPI:MODE>mode)"
   "ldp\\t%<w>2, %<w>3, [%1], %4"
   [(set_attr "v8type" "load2")
@@ -1126,16 +1130,16 @@
 
 ;; Store pair with writeback.  This is primarily used in function prologues
 ;; when saving [fp,lr]
-(define_insn "storewb_pair<GPI:mode>_<PTR:mode>"
+(define_insn "storewb_pair<GPI:mode>_<P:mode>"
   [(parallel
-    [(set (match_operand:PTR 0 "register_operand" "=&k")
-          (plus:PTR (match_operand:PTR 1 "register_operand" "0")
-                  (match_operand:PTR 4 "const_int_operand" "n")))
-     (set (mem:GPI (plus:PTR (match_dup 0)
+    [(set (match_operand:P 0 "register_operand" "=&k")
+          (plus:P (match_operand:P 1 "register_operand" "0")
+                  (match_operand:P 4 "const_int_operand" "n")))
+     (set (mem:GPI (plus:P (match_dup 0)
                    (match_dup 4)))
           (match_operand:GPI 2 "register_operand" "r"))
-     (set (mem:GPI (plus:PTR (match_dup 0)
-                   (match_operand:PTR 5 "const_int_operand" "n")))
+     (set (mem:GPI (plus:P (match_dup 0)
+                   (match_operand:P 5 "const_int_operand" "n")))
           (match_operand:GPI 3 "register_operand" "r"))])]
   "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPI:MODE>mode)"
   "stp\\t%<w>2, %<w>3, [%0, %4]!"
@@ -3681,25 +3685,53 @@
 ;; and lo_sum's to be used with the labels defining the jump tables in
 ;; rodata section.
 
-(define_insn "add_losym"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
-		   (match_operand 2 "aarch64_valid_symref" "S")))]
+(define_expand "add_losym"
+  [(set (match_operand 0 "register_operand" "=r")
+	(lo_sum (match_operand 1 "register_operand" "r")
+		(match_operand 2 "aarch64_valid_symref" "S")))]
   ""
-  "add\\t%0, %1, :lo12:%a2"
+{
+  enum machine_mode mode = GET_MODE (operands[0]);
+
+  emit_insn ((mode == DImode
+	      ? gen_add_losym_di
+	      : gen_add_losym_si) (operands[0],
+				   operands[1],
+				   operands[2]));
+  DONE;
+})
+
+(define_insn "add_losym_<mode>"
+  [(set (match_operand:P 0 "register_operand" "=r")
+	(lo_sum:P (match_operand:P 1 "register_operand" "r")
+		  (match_operand 2 "aarch64_valid_symref" "S")))]
+  ""
+  "add\\t%<w>0, %<w>1, :lo12:%a2"
   [(set_attr "v8type" "alu")
-   (set_attr "mode" "DI")]
+   (set_attr "mode" "<MODE>")]
+)
 
+(define_insn "ldr_got_small_<mode>"
+  [(set (match_operand:PTR 0 "register_operand" "=r")
+	(unspec:PTR [(mem:PTR (lo_sum:PTR
+			      (match_operand:PTR 1 "register_operand" "r")
+			      (match_operand:PTR 2 "aarch64_valid_symref" "S")))]
+		    UNSPEC_GOTSMALLPIC))]
+  ""
+  "ldr\\t%<w>0, [%1, #:got_lo12:%a2]"
+  [(set_attr "v8type" "load1")
+   (set_attr "mode" "<MODE>")]
 )
 
-(define_insn "ldr_got_small"
+(define_insn "ldr_got_small_sidi"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(unspec:DI [(mem:DI (lo_sum:DI
-			      (match_operand:DI 1 "register_operand" "r")
-			      (match_operand:DI 2 "aarch64_valid_symref" "S")))]
-		   UNSPEC_GOTSMALLPIC))]
-  ""
-  "ldr\\t%0, [%1, #:got_lo12:%a2]"
+	(zero_extend:DI
+	 (unspec:SI [(mem:SI (lo_sum:DI
+			     (match_operand:DI 1 "register_operand" "r")
+			     (match_operand:DI 2 "aarch64_valid_symref" "S")))]
+		    UNSPEC_GOTSMALLPIC)))]
+  "TARGET_ILP32"
+  "ldr\\t%w0, [%1, #:got_lo12:%a2]"
   [(set_attr "v8type" "load1")
    (set_attr "mode" "DI")]
 )
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 8e40c5d..76ff15d 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -76,9 +76,15 @@
 ;; Vector modes for moves.
 (define_mode_iterator VDQM [V8QI V16QI V4HI V8HI V2SI V4SI])
 
+;; This mode iterator allows :P to be used for patterns that operate on
+;; addresses in different modes.  In LP64, only DI will match, while in
+;; ILP32, either can match.
+(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
+			 (DI "ptr_mode == DImode || Pmode == DImode")])
+
 ;; This mode iterator allows :PTR to be used for patterns that operate on
 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
-(define_mode_iterator PTR [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
 
 ;; Vector Float modes.
 (define_mode_iterator VDQF [V2SF V4SF V2DF])

[Patch, AArch64, ILP32] 3/5 Minor change in function.c:assign_parm_find_data_types()

[Yufeng Zhang]

[-- Attachment #1: Type: text/plain, Size: 1718 bytes --]

This patch updates assign_parm_find_data_types to assign passed_mode and 
nominal_mode with the mode of the built pointer type instead of the 
hard-coded Pmode in the case of pass-by-reference.  This is in line with 
the assignment to passed_mode and nominal_mode in other cases inside the 
function.

assign_parm_find_data_types generally uses TYPE_MODE to calculate 
passed_mode and nominal_mode:

   /* Find mode of arg as it is passed, and mode of arg as it should be
      during execution of this function.  */
   passed_mode = TYPE_MODE (passed_type);
   nominal_mode = TYPE_MODE (nominal_type);

this includes the case when the passed argument is a pointer by itself.

However there is a discrepancy when it deals with argument passed by 
invisible reference; it builds the argument's corresponding pointer 
type, but sets passed_mode and nominal_mode with Pmode directly.

This is OK for targets where Pmode == ptr_mode, but on AArch64 with 
ILP32 they are different with Pmode as DImode and ptr_mode as SImode. 
When such a reference is passed on stack, the reference is prepared by 
the caller in the lower 4 bytes of an 8-byte slot but is fetched by the 
callee as an 8-byte datum, of which the higher 4 bytes may contain junk. 
  It is probably the combination of Pmode != ptr_mode and the particular 
ABI specification that make the AArch64 ILP32 the first target on which 
the issue manifests itself.

Bootstrapped on x86_64-none-linux-gnu.

OK for the trunk?

Thanks,
Yufeng


gcc/
	* function.c (assign_parm_find_data_types): Set passed_mode and
	nominal_mode to the TYPE_MODE of nominal_type for the built
	pointer type in case of the struct-pass-by-reference.

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 03-generic-change.patch --]
[-- Type: text/x-patch; name=03-generic-change.patch, Size: 499 bytes --]

diff --git a/gcc/function.c b/gcc/function.c
index 3e33fc7..6a0aaaf 100644
--- a/gcc/function.c
+++ b/gcc/function.c
@@ -2369,7 +2369,7 @@ assign_parm_find_data_types (struct assign_parm_data_all *all, tree parm,
     {
       passed_type = nominal_type = build_pointer_type (passed_type);
       data->passed_pointer = true;
-      passed_mode = nominal_mode = Pmode;
+      passed_mode = nominal_mode = TYPE_MODE (nominal_type);
     }
 
   /* Find mode as it is passed by the ABI.  */

[Patch, AArch64, ILP32] 4/5 Change tests to be ILP32-friendly

[Yufeng Zhang]

[-- Attachment #1: Type: text/plain, Size: 874 bytes --]

The attached patch fixes a few gcc test cases.


Thanks,
Yufeng


gcc/testsuite/

	* gcc.dg/20020219-1.c: Skip the test on aarch64*-*-* in ilp32.
	* gcc.target/aarch64/aapcs64/test_18.c (struct y): Change the field
	type from long to long long.
	* gcc.target/aarch64/atomic-op-long.c: Update dg-final directives
	to have effective-target keywords of lp64 and ilp32.
	* gcc.target/aarch64/fcvt_double_int.c: Likewise.
	* gcc.target/aarch64/fcvt_double_long.c: Likewise.
	* gcc.target/aarch64/fcvt_double_uint.c: Likewise.
	* gcc.target/aarch64/fcvt_double_ulong.c: Likewise.
	* gcc.target/aarch64/fcvt_float_int.c: Likewise.
	* gcc.target/aarch64/fcvt_float_long.c: Likewise.
	* gcc.target/aarch64/fcvt_float_uint.c: Likewise.
	* gcc.target/aarch64/fcvt_float_ulong.c: Likewise.
	* gcc.target/aarch64/vect_smlal_1.c: Replace 'long' with 'long long'.


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 04-fix-tests.patch --]
[-- Type: text/x-patch; name=04-fix-tests.patch, Size: 14584 bytes --]

diff --git a/gcc/testsuite/gcc.dg/20020219-1.c b/gcc/testsuite/gcc.dg/20020219-1.c
index ffdf19a..d2ba755 100644
--- a/gcc/testsuite/gcc.dg/20020219-1.c
+++ b/gcc/testsuite/gcc.dg/20020219-1.c
@@ -13,6 +13,7 @@
 /* { dg-do run } */
 /* { dg-options "-O2" } */
 /* { dg-options "-O2 -mdisable-indexing" { target hppa*-*-hpux* } } */
+/* { dg-skip-if "" { aarch64*-*-* && ilp32 } { "*" } { "" } } */
 /* { dg-skip-if "" { "ia64-*-hpux*" } "*" "-mlp64" } */
 /* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } { "*" } { "" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c
index b611e9b..2ebecee 100644
--- a/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c
+++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c
@@ -9,10 +9,10 @@
 
 struct y
 {
-  long p;
-  long q;
-  long r;
-  long s;
+  long long p;
+  long long q;
+  long long r;
+  long long s;
 } v = { 1, 2, 3, 4 };
 
 struct z
diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
index 9468ef4..0672d48 100644
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
@@ -39,5 +39,7 @@ atomic_fetch_or_RELAXED (long a)
   return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
 }
 
-/* { dg-final { scan-assembler-times "ldxr\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
-/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, x\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "ldxr\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */
+/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, x\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c
index 697aab1..e539909 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c
@@ -8,8 +8,10 @@
 #include "fcvt.x"
 
 /* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c
index edf640b..5eb36ff 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c
@@ -7,7 +7,11 @@
 
 #include "fcvt.x"
 
-/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 3 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 3 } } */
-/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c
index a1fae76..59be475 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c
@@ -8,8 +8,10 @@
 #include "fcvt.x"
 
 /* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
 /* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *d\[0-9\]" 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c
index f95fe55..55723cf 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c
@@ -7,9 +7,15 @@
 
 #include "fcvt.x"
 
-/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c
index ac15098..2e10e2d 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c
@@ -8,8 +8,10 @@
 #include "fcvt.x"
 
 /* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c
index 928ac52..1debf71 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c
@@ -7,7 +7,11 @@
 
 #include "fcvt.x"
 
-/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 3 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 3 } } */
-/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c
index a7d1868..c0b0c69 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c
@@ -8,8 +8,10 @@
 #include "fcvt.x"
 
 /* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
 /* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c
index ab6f46e..07309e2 100644
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c
@@ -7,9 +7,15 @@
 
 #include "fcvt.x"
 
-/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c b/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
index 1f86eae..f8cfecc 100644
--- a/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
@@ -4,11 +4,11 @@
 typedef signed char S8_t;
 typedef signed short S16_t;
 typedef signed int S32_t;
-typedef signed long S64_t;
+typedef signed long long S64_t;
 typedef signed char *__restrict__ pS8_t;
 typedef signed short *__restrict__ pS16_t;
 typedef signed int *__restrict__ pS32_t;
-typedef signed long *__restrict__ pS64_t;
+typedef signed long long *__restrict__ pS64_t;
 typedef unsigned char U8_t;
 typedef unsigned short U16_t;
 typedef unsigned int U32_t;
@@ -16,7 +16,7 @@ typedef unsigned long U64_t;
 typedef unsigned char *__restrict__ pU8_t;
 typedef unsigned short *__restrict__ pU16_t;
 typedef unsigned int *__restrict__ pU32_t;
-typedef unsigned long *__restrict__ pU64_t;
+typedef unsigned long long *__restrict__ pU64_t;
 
 extern void abort ();
 

[Patch, AArch64, ILP32] 5/5 Define _ILP32 and __ILP32__

[Yufeng Zhang]

[-- Attachment #1: Type: text/plain, Size: 357 bytes --]

This patch defines _ILP32 and __ILP32__ for the AArch64 port when the 
ILP32 ABI is in use.

This helps libraries, e.g. libgloss and glibc, recognize which model is 
being compiled.

OK for the trunk?

Thanks,
Yufeng


gcc/
	* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define _ILP32
	and __ILP32__ when the ILP32 model is in use.


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 05-define-ILP32-predefined-macros.patch --]
[-- Type: text/x-patch; name=05-define-ILP32-predefined-macros.patch, Size: 404 bytes --]

diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index d468dd8..e5dadb3 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -49,6 +49,11 @@
 	    break;					\
 	}						\
 							\
+      if (TARGET_ILP32)					\
+	{						\
+	  cpp_define (parse_in, "_ILP32");		\
+	  cpp_define (parse_in, "__ILP32__");		\
+	}						\
     } while (0)
 
 \f

Re: [Patch, AArch64, ILP32] 1/5 Initial support - configury changes

[Andrew Pinski]

On Wed, Jun 26, 2013 at 3:33 PM, Yufeng Zhang <Yufeng.Zhang@arm.com> wrote:
> This patch adds the configuration changes to the AArch64 GCC to support:
>
> * -milp32 and -mlp64 options in the compiler and the driver
> * multilib of ilp32 and/or lp64 libraries
> * differentiation of basic types in the compiler backend
>
> The patch enables --with-multilib-list configuration option for specifying
> the list of library flavors to enable; the default value is "mlp64" and can
> be overridden by --with-abi to "milp32".
>
> It also enables --with-abi for setting the default model in the compiler.
> Its default value is "mlp64" unless --with-multilib-list is explicitly
> specified with "milp32", in which case it defaults to "milp32".
>
> In the backend, two target flags are introduced: TARGET_ILP32 and
> TARGET_LP64.  They are set by -milp32 and -mlp64 respectively, exclusive to
> each other.  The default setting is via the option variable
> aarch64_pmodel_flags, which defaults to TARGET_DEFAULT_PMODEL, which is
> further defined in biarchlp64.h or biarchilp32.h depending which header file
> is included.
>
>                           biarchlp64.h         biarchilp32.h
> TARGET_DEFAULT_PMODEL     OPTION_MASK_LP64     OPTION_MASK_ILP32
> TARGET_PMODEL             1                    2
>
> TARGET_ILP32 and TARGET_LP64 are implicitly defined as:
>
> #define TARGET_ILP32 ((aarch64_pmodel_flags & OPTION_MASK_ILP32) != 0)
> #define TARGET_LP64 ((aarch64_pmodel_flags & OPTION_MASK_LP64) != 0)
>
> Note that the multilib support in the Linux toolchain is suppressed
> deliberately.
>
> OK for the trunk?


I think you should not support --with-multilib-list at all.  It should
just include ilp32 multilib no matter what.  Note the linux multilib
has to wait until the glibc/kernel side is done.

Also:
+#if TARGET_BIG_ENDIAN_DEFAULT == 1
+#define EMUL_SUFFIX "b"
+#else
+#define EMUL_SUFFIX ""
+#endif

is broken when you supply the opposite endian option.

Also you really should just use -mabi=ilp32 and -mabi=lp64 which
reduces the number of changes needed to be done to config.gcc.

You should use DRIVER_SELF_SPECS to simplify your LINKS_SPECS.
Something like:
#ifdef TARGET_BIG_ENDIAN_DEFAULT
#define ENDIAN_SPEC "-mbig-endian"
#else
#define ENDIAN_SPEC "-mlittle-endian"
#endif
/* Force the default endianness and ABI flags onto the command line
   in order to make the other specs easier to write.  */
#undef DRIVER_SELF_SPECS
#define DRIVER_SELF_SPECS \
  " %{!mbig-endian:%{!mlittle-endian:" ENDIAN_SPEC "}}" \
  " %{!milp32:%{!mlp64:-mlp64}}"

or rather:
" %{!mabi=*: -mabi=lp64}"



And then in aarch64-elf-raw.h:
#ifndef LINK_SPEC
#define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \
-maarch64elf%{milp32:32}%{mbig-endian:b}"
#endif

Or using the -mabi=* way:
#ifndef LINK_SPEC
#define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \
-maarch64elf%{mabi=ilp32:32}%{mbig-endian:b}"
#endif



Thanks,
Andrew Pinski


>
> Thanks,
> Yufeng
>
>
> gcc/
>         * config.gcc (aarch64*-*-*): Support --with-abi.
>         (aarch64*-*-elf): Support --with-multilib-list.
>         (aarch64*-*-linux*): Likewise.
>         (supported_defaults): Add abi to aarch64*-*-*.
>         * configure.ac: Mention AArch64 for --with-multilib-list.
>         * configure: Re-generated.
>         * config/aarch64/biarchilp32.h: New file.
>         * config/aarch64/biarchlp64.h: New file.
>         * config/aarch64/aarch64-elf.h (SPEC_LP64): New define.
>         (SPEC_ILP32): Ditto.
>         (ASM_SPEC): Update to SPEC_LP64 and SPEC_ILP32.
>         (MULTILIB_DEFAULTS): New define.
>         * config/aarch64/aarch64-elf-raw.h (EMUL_SUFFIX): New define.
>         (LINK_SPEC): Change to depend on SPEC_LP64 and SPEC_ILP32 and also
>         to use EMUL_SUFFIX.
>         * config/aarch64/aarch64.h (LONG_TYPE_SIZE): Change to depend on
>         TARGET_ILP32.
>         (POINTER_SIZE): New define.
>         (POINTERS_EXTEND_UNSIGNED): Ditto.
>         * config/aarch64/aarch64.c (initialize_aarch64_programming_model):
>         New declaration and definition.
>         (aarch64_override_options): Call the new function.
>         * config/aarch64/aarch64.opt (aarch64_pmodel_flags): New.
>         (milp32, mlp64): New.
>         * config/aarch64/t-aarch64 (comma): New define.
>         (MULTILIB_OPTIONS): Ditto.
>         (MULTILIB_DIRNAMES): Ditto.
>         * config/aarch64/t-aarch64-linux (MULTIARCH_DIRNAME): New define.
>

Re: [Patch, AArch64, ILP32] 3/5 Minor change in function.c:assign_parm_find_data_types()

[Andrew Pinski]

On Wed, Jun 26, 2013 at 3:39 PM, Yufeng Zhang <Yufeng.Zhang@arm.com> wrote:
> This patch updates assign_parm_find_data_types to assign passed_mode and
> nominal_mode with the mode of the built pointer type instead of the
> hard-coded Pmode in the case of pass-by-reference.  This is in line with the
> assignment to passed_mode and nominal_mode in other cases inside the
> function.
>
> assign_parm_find_data_types generally uses TYPE_MODE to calculate
> passed_mode and nominal_mode:
>
>   /* Find mode of arg as it is passed, and mode of arg as it should be
>      during execution of this function.  */
>   passed_mode = TYPE_MODE (passed_type);
>   nominal_mode = TYPE_MODE (nominal_type);
>
> this includes the case when the passed argument is a pointer by itself.
>
> However there is a discrepancy when it deals with argument passed by
> invisible reference; it builds the argument's corresponding pointer type,
> but sets passed_mode and nominal_mode with Pmode directly.
>
> This is OK for targets where Pmode == ptr_mode, but on AArch64 with ILP32
> they are different with Pmode as DImode and ptr_mode as SImode. When such a
> reference is passed on stack, the reference is prepared by the caller in the
> lower 4 bytes of an 8-byte slot but is fetched by the callee as an 8-byte
> datum, of which the higher 4 bytes may contain junk.  It is probably the
> combination of Pmode != ptr_mode and the particular ABI specification that
> make the AArch64 ILP32 the first target on which the issue manifests itself.
>
> Bootstrapped on x86_64-none-linux-gnu.
>
> OK for the trunk?


IA64-hpux also uses Pmode != ptr_mode, can you provide the testcase
which fails without this change?
I used a powerpc64 target where Pmode != ptr_mode which did not hit
this bug either.

Thanks,
Andrew

>
> Thanks,
> Yufeng
>
>
> gcc/
>         * function.c (assign_parm_find_data_types): Set passed_mode and
>         nominal_mode to the TYPE_MODE of nominal_type for the built
>         pointer type in case of the struct-pass-by-reference.

Re: [Patch, AArch64, ILP32] 3/5 Minor change in function.c:assign_parm_find_data_types()

[Yufeng Zhang]

On 06/27/13 00:04, Andrew Pinski wrote:
> On Wed, Jun 26, 2013 at 3:39 PM, Yufeng Zhang<Yufeng.Zhang@arm.com>  wrote:
>> This patch updates assign_parm_find_data_types to assign passed_mode and
>> nominal_mode with the mode of the built pointer type instead of the
>> hard-coded Pmode in the case of pass-by-reference.  This is in line with the
>> assignment to passed_mode and nominal_mode in other cases inside the
>> function.
>>
>> assign_parm_find_data_types generally uses TYPE_MODE to calculate
>> passed_mode and nominal_mode:
>>
>>    /* Find mode of arg as it is passed, and mode of arg as it should be
>>       during execution of this function.  */
>>    passed_mode = TYPE_MODE (passed_type);
>>    nominal_mode = TYPE_MODE (nominal_type);
>>
>> this includes the case when the passed argument is a pointer by itself.
>>
>> However there is a discrepancy when it deals with argument passed by
>> invisible reference; it builds the argument's corresponding pointer type,
>> but sets passed_mode and nominal_mode with Pmode directly.
>>
>> This is OK for targets where Pmode == ptr_mode, but on AArch64 with ILP32
>> they are different with Pmode as DImode and ptr_mode as SImode. When such a
>> reference is passed on stack, the reference is prepared by the caller in the
>> lower 4 bytes of an 8-byte slot but is fetched by the callee as an 8-byte
>> datum, of which the higher 4 bytes may contain junk.  It is probably the
>> combination of Pmode != ptr_mode and the particular ABI specification that
>> make the AArch64 ILP32 the first target on which the issue manifests itself.
>>
>> Bootstrapped on x86_64-none-linux-gnu.
>>
>> OK for the trunk?
>
>
> IA64-hpux also uses Pmode != ptr_mode, can you provide the testcase
> which fails without this change?
> I used a powerpc64 target where Pmode != ptr_mode which did not hit
> this bug either.

The issue was firstly observed in one of the compat tests which passes a 
large number of non-small structures.  The following is a trimmed-down 
reproducible code snippet (although not runnable but shall be easy to be 
make runnable):

struct s5
{
   double a;
   double b;
   double c;
   double d;
   double e;
} gS;

double foo (struct s5 p1, struct s5 p2,struct s5 p3,struct s5 p4,struct 
s5 p5,struct s5 p6,struct s5 p7,struct s5 p8, struct s5 p9)
{
   return p9.c;
}
--------------- CUT ---------------

The code-gen (-O2) without the patch is:

         .text
         .align  2
         .global foo
         .type   foo, %function
foo:
         ldr     x0, [sp]	<<=== here!
         ldr     d0, [x0,16]
         ret
         .size   foo, .-foo

Where the arrow points is the load of the pointer to 'p9' that is passed 
on stack.  The instruction really should be ldr w0, [sp], i.e. the 
pointer mode is SImode rather than DImode.

It needs a number of conditions for the issue to manifest:

1. pass-by-reference; on aarch64 one example is a struct that is larger 
than 16 bytes.
2. the reference is passed on stack; on aarch64, this usually only 
happens after registers x0 - x7 are used.
3. the size of stack slot for passing pointer is larger than the pointer 
size; on aarch64, it is 8-byte vs. 4-byte
4. the unused part of the stack slot is not zeroed out, i.e. undefined 
by the ABI
5. in the runtime, the unused part of such a stack slot contains junk.

The runtime segmentation fault may only be generated when all the above 
conditions are met.  I'm not familiar with IA64-hpux or powerpc64 
procedure call ABIs, but I guess those targets are just being lucky?

Thanks,
Yufeng

Re: [Patch, AArch64, ILP32] 3/5 Minor change in function.c:assign_parm_find_data_types()

[Andrew Pinski]

On Wed, Jun 26, 2013 at 4:41 PM, Yufeng Zhang <Yufeng.Zhang@arm.com> wrote:
> On 06/27/13 00:04, Andrew Pinski wrote:
>>
>> On Wed, Jun 26, 2013 at 3:39 PM, Yufeng Zhang<Yufeng.Zhang@arm.com>
>> wrote:
>>>
>>> This patch updates assign_parm_find_data_types to assign passed_mode and
>>> nominal_mode with the mode of the built pointer type instead of the
>>> hard-coded Pmode in the case of pass-by-reference.  This is in line with
>>> the
>>> assignment to passed_mode and nominal_mode in other cases inside the
>>> function.
>>>
>>> assign_parm_find_data_types generally uses TYPE_MODE to calculate
>>> passed_mode and nominal_mode:
>>>
>>>    /* Find mode of arg as it is passed, and mode of arg as it should be
>>>       during execution of this function.  */
>>>    passed_mode = TYPE_MODE (passed_type);
>>>    nominal_mode = TYPE_MODE (nominal_type);
>>>
>>> this includes the case when the passed argument is a pointer by itself.
>>>
>>> However there is a discrepancy when it deals with argument passed by
>>> invisible reference; it builds the argument's corresponding pointer type,
>>> but sets passed_mode and nominal_mode with Pmode directly.
>>>
>>> This is OK for targets where Pmode == ptr_mode, but on AArch64 with ILP32
>>> they are different with Pmode as DImode and ptr_mode as SImode. When such
>>> a
>>> reference is passed on stack, the reference is prepared by the caller in
>>> the
>>> lower 4 bytes of an 8-byte slot but is fetched by the callee as an 8-byte
>>> datum, of which the higher 4 bytes may contain junk.  It is probably the
>>> combination of Pmode != ptr_mode and the particular ABI specification
>>> that
>>> make the AArch64 ILP32 the first target on which the issue manifests
>>> itself.
>>>
>>> Bootstrapped on x86_64-none-linux-gnu.
>>>
>>> OK for the trunk?
>>
>>
>>
>> IA64-hpux also uses Pmode != ptr_mode, can you provide the testcase
>> which fails without this change?
>> I used a powerpc64 target where Pmode != ptr_mode which did not hit
>> this bug either.
>
>
> The issue was firstly observed in one of the compat tests which passes a
> large number of non-small structures.  The following is a trimmed-down
> reproducible code snippet (although not runnable but shall be easy to be
> make runnable):
>
> struct s5
> {
>   double a;
>   double b;
>   double c;
>   double d;
>   double e;
> } gS;
>
> double foo (struct s5 p1, struct s5 p2,struct s5 p3,struct s5 p4,struct s5
> p5,struct s5 p6,struct s5 p7,struct s5 p8, struct s5 p9)
> {
>   return p9.c;
> }
> --------------- CUT ---------------
>
> The code-gen (-O2) without the patch is:
>
>         .text
>         .align  2
>         .global foo
>         .type   foo, %function
> foo:
>         ldr     x0, [sp]        <<=== here!
>         ldr     d0, [x0,16]
>         ret
>         .size   foo, .-foo
>
> Where the arrow points is the load of the pointer to 'p9' that is passed on
> stack.  The instruction really should be ldr w0, [sp], i.e. the pointer mode
> is SImode rather than DImode.
>
> It needs a number of conditions for the issue to manifest:
>
> 1. pass-by-reference; on aarch64 one example is a struct that is larger than
> 16 bytes.
> 2. the reference is passed on stack; on aarch64, this usually only happens
> after registers x0 - x7 are used.
> 3. the size of stack slot for passing pointer is larger than the pointer
> size; on aarch64, it is 8-byte vs. 4-byte
> 4. the unused part of the stack slot is not zeroed out, i.e. undefined by
> the ABI

This is the real issue.  I think it is better if we change the ABI to
say they are zero'd.  It really makes things like this a mess.

> 5. in the runtime, the unused part of such a stack slot contains junk.
>
> The runtime segmentation fault may only be generated when all the above
> conditions are met.  I'm not familiar with IA64-hpux or powerpc64 procedure
> call ABIs, but I guess those targets are just being lucky?

Or rather their ABIs all say are zero or sign extended for values less
than 8 byte wide.

Thanks,
Andrew Pinski

Re: [Patch, AArch64, ILP32] 3/5 Minor change in function.c:assign_parm_find_data_types()

[Andrew Pinski]

On Wed, Jun 26, 2013 at 4:51 PM, Andrew Pinski <pinskia@gmail.com> wrote:
> On Wed, Jun 26, 2013 at 4:41 PM, Yufeng Zhang <Yufeng.Zhang@arm.com> wrote:
>> On 06/27/13 00:04, Andrew Pinski wrote:
>>>
>>> On Wed, Jun 26, 2013 at 3:39 PM, Yufeng Zhang<Yufeng.Zhang@arm.com>
>>> wrote:
>>>>
>>>> This patch updates assign_parm_find_data_types to assign passed_mode and
>>>> nominal_mode with the mode of the built pointer type instead of the
>>>> hard-coded Pmode in the case of pass-by-reference.  This is in line with
>>>> the
>>>> assignment to passed_mode and nominal_mode in other cases inside the
>>>> function.
>>>>
>>>> assign_parm_find_data_types generally uses TYPE_MODE to calculate
>>>> passed_mode and nominal_mode:
>>>>
>>>>    /* Find mode of arg as it is passed, and mode of arg as it should be
>>>>       during execution of this function.  */
>>>>    passed_mode = TYPE_MODE (passed_type);
>>>>    nominal_mode = TYPE_MODE (nominal_type);
>>>>
>>>> this includes the case when the passed argument is a pointer by itself.
>>>>
>>>> However there is a discrepancy when it deals with argument passed by
>>>> invisible reference; it builds the argument's corresponding pointer type,
>>>> but sets passed_mode and nominal_mode with Pmode directly.
>>>>
>>>> This is OK for targets where Pmode == ptr_mode, but on AArch64 with ILP32
>>>> they are different with Pmode as DImode and ptr_mode as SImode. When such
>>>> a
>>>> reference is passed on stack, the reference is prepared by the caller in
>>>> the
>>>> lower 4 bytes of an 8-byte slot but is fetched by the callee as an 8-byte
>>>> datum, of which the higher 4 bytes may contain junk.  It is probably the
>>>> combination of Pmode != ptr_mode and the particular ABI specification
>>>> that
>>>> make the AArch64 ILP32 the first target on which the issue manifests
>>>> itself.
>>>>
>>>> Bootstrapped on x86_64-none-linux-gnu.
>>>>
>>>> OK for the trunk?
>>>
>>>
>>>
>>> IA64-hpux also uses Pmode != ptr_mode, can you provide the testcase
>>> which fails without this change?
>>> I used a powerpc64 target where Pmode != ptr_mode which did not hit
>>> this bug either.
>>
>>
>> The issue was firstly observed in one of the compat tests which passes a
>> large number of non-small structures.  The following is a trimmed-down
>> reproducible code snippet (although not runnable but shall be easy to be
>> make runnable):
>>
>> struct s5
>> {
>>   double a;
>>   double b;
>>   double c;
>>   double d;
>>   double e;
>> } gS;
>>
>> double foo (struct s5 p1, struct s5 p2,struct s5 p3,struct s5 p4,struct s5
>> p5,struct s5 p6,struct s5 p7,struct s5 p8, struct s5 p9)
>> {
>>   return p9.c;
>> }
>> --------------- CUT ---------------
>>
>> The code-gen (-O2) without the patch is:
>>
>>         .text
>>         .align  2
>>         .global foo
>>         .type   foo, %function
>> foo:
>>         ldr     x0, [sp]        <<=== here!
>>         ldr     d0, [x0,16]
>>         ret
>>         .size   foo, .-foo
>>
>> Where the arrow points is the load of the pointer to 'p9' that is passed on
>> stack.  The instruction really should be ldr w0, [sp], i.e. the pointer mode
>> is SImode rather than DImode.
>>
>> It needs a number of conditions for the issue to manifest:
>>
>> 1. pass-by-reference; on aarch64 one example is a struct that is larger than
>> 16 bytes.
>> 2. the reference is passed on stack; on aarch64, this usually only happens
>> after registers x0 - x7 are used.
>> 3. the size of stack slot for passing pointer is larger than the pointer
>> size; on aarch64, it is 8-byte vs. 4-byte
>> 4. the unused part of the stack slot is not zeroed out, i.e. undefined by
>> the ABI
>
> This is the real issue.  I think it is better if we change the ABI to
> say they are zero'd.  It really makes things like this a mess.
>
>> 5. in the runtime, the unused part of such a stack slot contains junk.
>>
>> The runtime segmentation fault may only be generated when all the above
>> conditions are met.  I'm not familiar with IA64-hpux or powerpc64 procedure
>> call ABIs, but I guess those targets are just being lucky?
>
> Or rather their ABIs all say are zero or sign extended for values less
> than 8 byte wide.

One more thing, it looks like your change will not work correctly for
big-endian ILP32 AARCH64 either as the least significant word is
offsetted by 4.
Did you test big-endian ILP32 AARCH64?

Thanks,
Andrew Pinski

Re: [Patch, AArch64, ILP32] 3/5 Minor change in function.c:assign_parm_find_data_types()

[Yufeng Zhang]

On 06/27/13 00:51, Andrew Pinski wrote:
> On Wed, Jun 26, 2013 at 4:41 PM, Yufeng Zhang<Yufeng.Zhang@arm.com>  wrote:
>> On 06/27/13 00:04, Andrew Pinski wrote:
>>>
>>> On Wed, Jun 26, 2013 at 3:39 PM, Yufeng Zhang<Yufeng.Zhang@arm.com>
>>> wrote:
>>>>
>>>> This patch updates assign_parm_find_data_types to assign passed_mode and
>>>> nominal_mode with the mode of the built pointer type instead of the
>>>> hard-coded Pmode in the case of pass-by-reference.  This is in line with
>>>> the
>>>> assignment to passed_mode and nominal_mode in other cases inside the
>>>> function.
>>>>
>>>> assign_parm_find_data_types generally uses TYPE_MODE to calculate
>>>> passed_mode and nominal_mode:
>>>>
>>>>     /* Find mode of arg as it is passed, and mode of arg as it should be
>>>>        during execution of this function.  */
>>>>     passed_mode = TYPE_MODE (passed_type);
>>>>     nominal_mode = TYPE_MODE (nominal_type);
>>>>
>>>> this includes the case when the passed argument is a pointer by itself.
>>>>
>>>> However there is a discrepancy when it deals with argument passed by
>>>> invisible reference; it builds the argument's corresponding pointer type,
>>>> but sets passed_mode and nominal_mode with Pmode directly.
>>>>
>>>> This is OK for targets where Pmode == ptr_mode, but on AArch64 with ILP32
>>>> they are different with Pmode as DImode and ptr_mode as SImode. When such
>>>> a
>>>> reference is passed on stack, the reference is prepared by the caller in
>>>> the
>>>> lower 4 bytes of an 8-byte slot but is fetched by the callee as an 8-byte
>>>> datum, of which the higher 4 bytes may contain junk.  It is probably the
>>>> combination of Pmode != ptr_mode and the particular ABI specification
>>>> that
>>>> make the AArch64 ILP32 the first target on which the issue manifests
>>>> itself.
>>>>
>>>> Bootstrapped on x86_64-none-linux-gnu.
>>>>
>>>> OK for the trunk?
>>>
>>>
>>>
>>> IA64-hpux also uses Pmode != ptr_mode, can you provide the testcase
>>> which fails without this change?
>>> I used a powerpc64 target where Pmode != ptr_mode which did not hit
>>> this bug either.
>>
>>
>> The issue was firstly observed in one of the compat tests which passes a
>> large number of non-small structures.  The following is a trimmed-down
>> reproducible code snippet (although not runnable but shall be easy to be
>> make runnable):
>>
>> struct s5
>> {
>>    double a;
>>    double b;
>>    double c;
>>    double d;
>>    double e;
>> } gS;
>>
>> double foo (struct s5 p1, struct s5 p2,struct s5 p3,struct s5 p4,struct s5
>> p5,struct s5 p6,struct s5 p7,struct s5 p8, struct s5 p9)
>> {
>>    return p9.c;
>> }
>> --------------- CUT ---------------
>>
>> The code-gen (-O2) without the patch is:
>>
>>          .text
>>          .align  2
>>          .global foo
>>          .type   foo, %function
>> foo:
>>          ldr     x0, [sp]<<=== here!
>>          ldr     d0, [x0,16]
>>          ret
>>          .size   foo, .-foo
>>
>> Where the arrow points is the load of the pointer to 'p9' that is passed on
>> stack.  The instruction really should be ldr w0, [sp], i.e. the pointer mode
>> is SImode rather than DImode.
>>
>> It needs a number of conditions for the issue to manifest:
>>
>> 1. pass-by-reference; on aarch64 one example is a struct that is larger than
>> 16 bytes.
>> 2. the reference is passed on stack; on aarch64, this usually only happens
>> after registers x0 - x7 are used.
>> 3. the size of stack slot for passing pointer is larger than the pointer
>> size; on aarch64, it is 8-byte vs. 4-byte
>> 4. the unused part of the stack slot is not zeroed out, i.e. undefined by
>> the ABI
>
> This is the real issue.  I think it is better if we change the ABI to
> say they are zero'd.  It really makes things like this a mess.

I don't agree on this.  There is nothing wrong with the unused bits 
filled with unspecified values; there are sufficient number of 
load/store instruction variants on AArch64 that are able to load/store 
smaller-sized datum from/to memory; zeroing-unused bits on the stack may 
require extra instructions which add cost.

Nevertheless, assign_parm_find_data_types() shall not generate different 
modes for pass-by-reference argument and straight-forward pointer one. 
For instance in the following code snippet, the passed_mode and 
nominal_mode for '&p9' in foo and 'p9' in bar shall be the same; but 
'&p9' in foo gets DImode and 'p3' in bar get SImode, which is really 
wrong (by typing '&p9', I mean the pass-by-reference).

struct s5
{
   double a;
   double b;
   double c;
   double d;
   double e;
} gS;

double foo (struct s5 p1, struct s5 p2,struct s5 p3,struct s5 p4,struct 
s5 p5,struct s5 p6,struct s5 p7,struct s5 p8, struct s5 p9)
{
   return p9.c;
}

double bar (struct s5 *p1, struct s5 *p2,struct s5 *p3,struct s5 
*p4,struct s5 *p5,struct s5 *p6,struct s5 *p7,struct s5 *p8, struct s5 *p9)
{
   return p9->c;
}

Hope I have demonstrated the issue clearly.

Thanks,
Yufeng

Re: [Patch, AArch64, ILP32] 3/5 Minor change in function.c:assign_parm_find_data_types()

[Yufeng Zhang]

On 06/27/13 00:57, Andrew Pinski wrote:
> On Wed, Jun 26, 2013 at 4:51 PM, Andrew Pinski<pinskia@gmail.com>  wrote:
>> On Wed, Jun 26, 2013 at 4:41 PM, Yufeng Zhang<Yufeng.Zhang@arm.com>  wrote:
>>> On 06/27/13 00:04, Andrew Pinski wrote:
>>>>
>>>> On Wed, Jun 26, 2013 at 3:39 PM, Yufeng Zhang<Yufeng.Zhang@arm.com>
>>>> wrote:
>>>>>
>>>>> This patch updates assign_parm_find_data_types to assign passed_mode and
>>>>> nominal_mode with the mode of the built pointer type instead of the
>>>>> hard-coded Pmode in the case of pass-by-reference.  This is in line with
>>>>> the
>>>>> assignment to passed_mode and nominal_mode in other cases inside the
>>>>> function.
>>>>>
>>>>> assign_parm_find_data_types generally uses TYPE_MODE to calculate
>>>>> passed_mode and nominal_mode:
>>>>>
>>>>>     /* Find mode of arg as it is passed, and mode of arg as it should be
>>>>>        during execution of this function.  */
>>>>>     passed_mode = TYPE_MODE (passed_type);
>>>>>     nominal_mode = TYPE_MODE (nominal_type);
>>>>>
>>>>> this includes the case when the passed argument is a pointer by itself.
>>>>>
>>>>> However there is a discrepancy when it deals with argument passed by
>>>>> invisible reference; it builds the argument's corresponding pointer type,
>>>>> but sets passed_mode and nominal_mode with Pmode directly.
>>>>>
>>>>> This is OK for targets where Pmode == ptr_mode, but on AArch64 with ILP32
>>>>> they are different with Pmode as DImode and ptr_mode as SImode. When such
>>>>> a
>>>>> reference is passed on stack, the reference is prepared by the caller in
>>>>> the
>>>>> lower 4 bytes of an 8-byte slot but is fetched by the callee as an 8-byte
>>>>> datum, of which the higher 4 bytes may contain junk.  It is probably the
>>>>> combination of Pmode != ptr_mode and the particular ABI specification
>>>>> that
>>>>> make the AArch64 ILP32 the first target on which the issue manifests
>>>>> itself.
>>>>>
>>>>> Bootstrapped on x86_64-none-linux-gnu.
>>>>>
>>>>> OK for the trunk?
>>>>
>>>>
>>>>
>>>> IA64-hpux also uses Pmode != ptr_mode, can you provide the testcase
>>>> which fails without this change?
>>>> I used a powerpc64 target where Pmode != ptr_mode which did not hit
>>>> this bug either.
>>>
>>>
>>> The issue was firstly observed in one of the compat tests which passes a
>>> large number of non-small structures.  The following is a trimmed-down
>>> reproducible code snippet (although not runnable but shall be easy to be
>>> make runnable):
>>>
>>> struct s5
>>> {
>>>    double a;
>>>    double b;
>>>    double c;
>>>    double d;
>>>    double e;
>>> } gS;
>>>
>>> double foo (struct s5 p1, struct s5 p2,struct s5 p3,struct s5 p4,struct s5
>>> p5,struct s5 p6,struct s5 p7,struct s5 p8, struct s5 p9)
>>> {
>>>    return p9.c;
>>> }
>>> --------------- CUT ---------------
>>>
>>> The code-gen (-O2) without the patch is:
>>>
>>>          .text
>>>          .align  2
>>>          .global foo
>>>          .type   foo, %function
>>> foo:
>>>          ldr     x0, [sp]<<=== here!
>>>          ldr     d0, [x0,16]
>>>          ret
>>>          .size   foo, .-foo
>>>
>>> Where the arrow points is the load of the pointer to 'p9' that is passed on
>>> stack.  The instruction really should be ldr w0, [sp], i.e. the pointer mode
>>> is SImode rather than DImode.
>>>
>>> It needs a number of conditions for the issue to manifest:
>>>
>>> 1. pass-by-reference; on aarch64 one example is a struct that is larger than
>>> 16 bytes.
>>> 2. the reference is passed on stack; on aarch64, this usually only happens
>>> after registers x0 - x7 are used.
>>> 3. the size of stack slot for passing pointer is larger than the pointer
>>> size; on aarch64, it is 8-byte vs. 4-byte
>>> 4. the unused part of the stack slot is not zeroed out, i.e. undefined by
>>> the ABI
>>
>> This is the real issue.  I think it is better if we change the ABI to
>> say they are zero'd.  It really makes things like this a mess.
>>
>>> 5. in the runtime, the unused part of such a stack slot contains junk.
>>>
>>> The runtime segmentation fault may only be generated when all the above
>>> conditions are met.  I'm not familiar with IA64-hpux or powerpc64 procedure
>>> call ABIs, but I guess those targets are just being lucky?
>>
>> Or rather their ABIs all say are zero or sign extended for values less
>> than 8 byte wide.
>
> One more thing, it looks like your change will not work correctly for
> big-endian ILP32 AARCH64 either as the least significant word is
> offsetted by 4.

Ah, this is definitely a bug and I can confirm that it only happens on 
the 32-bit pointer-type parameter passed on stack.  I'll bring up a 
patch today to fix it.

> Did you test big-endian ILP32 AARCH64?

I started the big-endian testing fairly recently, so there is limited 
testing done so far but I am still working on it and will prepare 
patches if more issues are found.

Thanks,
Yufeng

Re: [Patch, AArch64, ILP32] 5/5 Define _ILP32 and __ILP32__

[Joseph S. Myers]

On Wed, 26 Jun 2013, Yufeng Zhang wrote:

> This patch defines _ILP32 and __ILP32__ for the AArch64 port when the ILP32
> ABI is in use.
> 
> This helps libraries, e.g. libgloss and glibc, recognize which model is being
> compiled.

GCC already defines _LP64 and __LP64__ in architecture-independent code 
for LP64 systems.  Libraries can use those to distinguish the two models 
for AArch64, so I don't see any need to add architecture-specific macros 
with the opposite sense.

-- 
Joseph S. Myers
joseph@codesourcery.com

[Patch, AArch64, ILP32] Pad pointer-typed stack argument downward in ILP32

[Yufeng Zhang]

[-- Attachment #1: Type: text/plain, Size: 376 bytes --]

This patch fixes the bug that pointer-typed argument passed on stack is 
not padded properly in ILP32.

OK for the trunk?

Thanks,
Yufeng



gcc/

         * config/aarch64/aarch64.c (aarch64_pad_arg_upward): In big-endian,
         pad pointer-typed argument downward.

gcc/testsuite/

         * gcc.target/aarch64/test-ptr-arg-on-stack-1.c: New test.



[-- Attachment #2: 06-fix-32-bit-ptr-padding.txt --]
[-- Type: text/plain, Size: 2142 bytes --]

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index f78e0d6..79f8761 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1585,11 +1585,12 @@ aarch64_pad_arg_upward (enum machine_mode mode, const_tree type)
   if (!BYTES_BIG_ENDIAN)
     return true;
 
-  /* Otherwise, integral types and floating point types are padded downward:
+  /* Otherwise, integral, floating-point and pointer types are padded downward:
      the least significant byte of a stack argument is passed at the highest
      byte address of the stack slot.  */
   if (type
-      ? (INTEGRAL_TYPE_P (type) || SCALAR_FLOAT_TYPE_P (type))
+      ? (INTEGRAL_TYPE_P (type) || SCALAR_FLOAT_TYPE_P (type)
+	 || POINTER_TYPE_P (type))
       : (SCALAR_INT_MODE_P (mode) || SCALAR_FLOAT_MODE_P (mode)))
     return false;
 
diff --git a/gcc/testsuite/gcc.target/aarch64/test-ptr-arg-on-stack-1.c b/gcc/testsuite/gcc.target/aarch64/test-ptr-arg-on-stack-1.c
new file mode 100644
index 0000000..bb68e0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/test-ptr-arg-on-stack-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-inline" } */
+
+/* Test pass-by-reference and pointer-typed argument passing on stack.
+   This test shall pass on any of the following four combinitions:
+    {big-endian, little-endian} {LP64, ILP32}.  */
+
+struct s5
+{
+  double a;
+  double b;
+  double c;
+  double d;
+  double e;
+} gS = {1.0, 2.0, 3.0, 4.0, 5.0};
+
+double  __attribute__ ((noinline))
+foo (struct s5 p1, struct s5 p2, struct s5 p3, struct s5 p4,
+     struct s5 p5, struct s5 p6, struct s5 p7, struct s5 p8,
+     struct s5 p9)
+{
+  asm ("");
+  return p9.c;
+}
+
+void abort (void);
+int printf (const char *, ...);
+
+int main (void)
+{
+  printf ("Here we print out some values and more importantly hope that"
+	  " the stack is getting a bit dirty for the bug to manifest itself"
+	  "\n\t%f, %f, %f, %f, %f\n", gS.a, gS.b, gS.c, gS.d, gS.e);
+
+  if (foo (gS, gS, gS, gS, gS, gS, gS, gS, gS) != 3.0)
+    abort ();
+
+  return 0;
+}

Re: [Patch, AArch64, ILP32] 5/5 Define _ILP32 and __ILP32__

[Yufeng Zhang]

On 06/27/13 01:56, Joseph S. Myers wrote:
> On Wed, 26 Jun 2013, Yufeng Zhang wrote:
>
>> This patch defines _ILP32 and __ILP32__ for the AArch64 port when the ILP32
>> ABI is in use.
>>
>> This helps libraries, e.g. libgloss and glibc, recognize which model is being
>> compiled.
>
> GCC already defines _LP64 and __LP64__ in architecture-independent code
> for LP64 systems.  Libraries can use those to distinguish the two models
> for AArch64, so I don't see any need to add architecture-specific macros
> with the opposite sense.

We need a reliable way to tell we are compiling for ILP32.  On one hand 
LLP64 support may be added in the future; on the other hand, not all 
AArch64 compilers may define _LP64 and __LP64__.

Other ports like x86_64, ia64-hpux and pa-hpux also define one or both.

Thanks,
Yufeng

Re: [Patch, AArch64, ILP32] 5/5 Define _ILP32 and __ILP32__

[Joseph S. Myers]

On Thu, 27 Jun 2013, Yufeng Zhang wrote:

> We need a reliable way to tell we are compiling for ILP32.  On one hand LLP64
> support may be added in the future; on the other hand, not all AArch64

If thinking of adding a third ABI, that suggests you should be using 
something along the lines of _MIPS_SIM - a macro that's always defined, 
with an integer value depending on the ABI in used.

> compilers may define _LP64 and __LP64__.

Why should all such compilers define the ILP32 macros, but not all define 
the LP64 macros?  Do you have an AArch64 equivalent of the ACLE that 
specifies such things?

> Other ports like x86_64, ia64-hpux and pa-hpux also define one or both.

If multiple ports define something, that might be an indication for 
defining it in target-independent code (like _LP64) rather than repeating 
it for more targets.  Although of course the macros __SIZEOF_INT__, 
__SIZEOF_LONG__, __SIZEOF_LONG_LONG__ and __SIZEOF_POINTER__ have been 
around for a long time, so new macros would just be for convenience (which 
may nevertheless be a sensible reason to define macros) at the expense of 
startup time.

-- 
Joseph S. Myers
joseph@codesourcery.com

Re: [Patch, AArch64, ILP32] 1/5 Initial support - configury changes

[Yufeng Zhang]

Hi Andrew,

Thank you for your review.  I'm currently testing an updated patch and 
will send it for further review early next week.

Regards,
Yufeng


On 06/26/13 23:59, Andrew Pinski wrote:
> On Wed, Jun 26, 2013 at 3:33 PM, Yufeng Zhang<Yufeng.Zhang@arm.com>  wrote:
>> This patch adds the configuration changes to the AArch64 GCC to support:
>>
>> * -milp32 and -mlp64 options in the compiler and the driver
>> * multilib of ilp32 and/or lp64 libraries
>> * differentiation of basic types in the compiler backend
>>
>> The patch enables --with-multilib-list configuration option for specifying
>> the list of library flavors to enable; the default value is "mlp64" and can
>> be overridden by --with-abi to "milp32".
>>
>> It also enables --with-abi for setting the default model in the compiler.
>> Its default value is "mlp64" unless --with-multilib-list is explicitly
>> specified with "milp32", in which case it defaults to "milp32".
>>
>> In the backend, two target flags are introduced: TARGET_ILP32 and
>> TARGET_LP64.  They are set by -milp32 and -mlp64 respectively, exclusive to
>> each other.  The default setting is via the option variable
>> aarch64_pmodel_flags, which defaults to TARGET_DEFAULT_PMODEL, which is
>> further defined in biarchlp64.h or biarchilp32.h depending which header file
>> is included.
>>
>>                            biarchlp64.h         biarchilp32.h
>> TARGET_DEFAULT_PMODEL     OPTION_MASK_LP64     OPTION_MASK_ILP32
>> TARGET_PMODEL             1                    2
>>
>> TARGET_ILP32 and TARGET_LP64 are implicitly defined as:
>>
>> #define TARGET_ILP32 ((aarch64_pmodel_flags&  OPTION_MASK_ILP32) != 0)
>> #define TARGET_LP64 ((aarch64_pmodel_flags&  OPTION_MASK_LP64) != 0)
>>
>> Note that the multilib support in the Linux toolchain is suppressed
>> deliberately.
>>
>> OK for the trunk?
>
>
> I think you should not support --with-multilib-list at all.  It should
> just include ilp32 multilib no matter what.  Note the linux multilib
> has to wait until the glibc/kernel side is done.
>
> Also:
> +#if TARGET_BIG_ENDIAN_DEFAULT == 1
> +#define EMUL_SUFFIX "b"
> +#else
> +#define EMUL_SUFFIX ""
> +#endif
>
> is broken when you supply the opposite endian option.
>
> Also you really should just use -mabi=ilp32 and -mabi=lp64 which
> reduces the number of changes needed to be done to config.gcc.
>
> You should use DRIVER_SELF_SPECS to simplify your LINKS_SPECS.
> Something like:
> #ifdef TARGET_BIG_ENDIAN_DEFAULT
> #define ENDIAN_SPEC "-mbig-endian"
> #else
> #define ENDIAN_SPEC "-mlittle-endian"
> #endif
> /* Force the default endianness and ABI flags onto the command line
>     in order to make the other specs easier to write.  */
> #undef DRIVER_SELF_SPECS
> #define DRIVER_SELF_SPECS \
>    " %{!mbig-endian:%{!mlittle-endian:" ENDIAN_SPEC "}}" \
>    " %{!milp32:%{!mlp64:-mlp64}}"
>
> or rather:
> " %{!mabi=*: -mabi=lp64}"
>
>
>
> And then in aarch64-elf-raw.h:
> #ifndef LINK_SPEC
> #define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \
> -maarch64elf%{milp32:32}%{mbig-endian:b}"
> #endif
>
> Or using the -mabi=* way:
> #ifndef LINK_SPEC
> #define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \
> -maarch64elf%{mabi=ilp32:32}%{mbig-endian:b}"
> #endif
>
>
>
> Thanks,
> Andrew Pinski
>
>
>>
>> Thanks,
>> Yufeng
>>
>>
>> gcc/
>>          * config.gcc (aarch64*-*-*): Support --with-abi.
>>          (aarch64*-*-elf): Support --with-multilib-list.
>>          (aarch64*-*-linux*): Likewise.
>>          (supported_defaults): Add abi to aarch64*-*-*.
>>          * configure.ac: Mention AArch64 for --with-multilib-list.
>>          * configure: Re-generated.
>>          * config/aarch64/biarchilp32.h: New file.
>>          * config/aarch64/biarchlp64.h: New file.
>>          * config/aarch64/aarch64-elf.h (SPEC_LP64): New define.
>>          (SPEC_ILP32): Ditto.
>>          (ASM_SPEC): Update to SPEC_LP64 and SPEC_ILP32.
>>          (MULTILIB_DEFAULTS): New define.
>>          * config/aarch64/aarch64-elf-raw.h (EMUL_SUFFIX): New define.
>>          (LINK_SPEC): Change to depend on SPEC_LP64 and SPEC_ILP32 and also
>>          to use EMUL_SUFFIX.
>>          * config/aarch64/aarch64.h (LONG_TYPE_SIZE): Change to depend on
>>          TARGET_ILP32.
>>          (POINTER_SIZE): New define.
>>          (POINTERS_EXTEND_UNSIGNED): Ditto.
>>          * config/aarch64/aarch64.c (initialize_aarch64_programming_model):
>>          New declaration and definition.
>>          (aarch64_override_options): Call the new function.
>>          * config/aarch64/aarch64.opt (aarch64_pmodel_flags): New.
>>          (milp32, mlp64): New.
>>          * config/aarch64/t-aarch64 (comma): New define.
>>          (MULTILIB_OPTIONS): Ditto.
>>          (MULTILIB_DIRNAMES): Ditto.
>>          * config/aarch64/t-aarch64-linux (MULTIARCH_DIRNAME): New define.
>>
>

Re: [Patch, AArch64, ILP32] 5/5 Define _ILP32 and __ILP32__

[Yufeng Zhang]

On 06/27/13 20:28, Joseph S. Myers wrote:
> On Thu, 27 Jun 2013, Yufeng Zhang wrote:
>
>> We need a reliable way to tell we are compiling for ILP32.  On one hand LLP64
>> support may be added in the future; on the other hand, not all AArch64
>
> If thinking of adding a third ABI, that suggests you should be using
> something along the lines of _MIPS_SIM - a macro that's always defined,
> with an integer value depending on the ABI in used.
>
>> compilers may define _LP64 and __LP64__.
>
> Why should all such compilers define the ILP32 macros, but not all define
> the LP64 macros?  Do you have an AArch64 equivalent of the ACLE that
> specifies such things?

There will be ACLE for AArch64 and it is in the view that both macros 
will be specified.

Since a few other ports that support ILP32 have already defined these 
macros, it shall help the code porting with them defined for AArch64 as 
well.

>> Other ports like x86_64, ia64-hpux and pa-hpux also define one or both.
>
> If multiple ports define something, that might be an indication for
> defining it in target-independent code (like _LP64) rather than repeating
> it for more targets.

I can propose a patch later to have _ILP32 and __ILP32__ defined in the 
target-independent code instead and see if the community like it?

Thanks,
Yufeng

Re: [Patch, AArch64, ILP32] 1/5 Initial support - configury changes

[Yufeng Zhang]

[-- Attachment #1: Type: text/plain, Size: 5211 bytes --]

Hi Andrew,

Please find the updated patch in the attachment that addresses your 
comments.

It now builds both ilp32 and lp64 multilibs by default, with the 
--with-multilib-list support remaining to provide options to turn off 
one of them.

-mabi=ilp32 and -mabi=lp64 are now the command line options to use.  The 
SPECs have been updated as well.

Thanks,
Yufeng


gcc/
         * config.gcc (aarch64*-*-*): Support --with-abi.
         (aarch64*-*-elf): Support --with-multilib-list.
         (aarch64*-*-linux*): Likewise.
         (supported_defaults): Add abi to aarch64*-*-*.
         * configure.ac: Mention AArch64 for --with-multilib-list.
         * configure: Re-generated.
         * config/aarch64/biarchilp32.h: New file.
         * config/aarch64/biarchlp64.h: New file.
         * config/aarch64/aarch64-elf.h (ENDIAN_SPEC): New define.
         (ABI_SPEC): Ditto.
         (MULTILIB_DEFAULTS): Ditto.
         (DRIVER_SELF_SPECS): Ditto.
         (ASM_SPEC): Update to also substitute -mabi.
         * config/aarch64/aarch64-elf-raw.h (LINK_SPEC): Add linker script
         file whose name depends on -mabi= and -mbig-endian.
         * config/aarch64/aarch64.h (LONG_TYPE_SIZE): Change to depend on
         TARGET_ILP32.
         (POINTER_SIZE): New define.
         (POINTERS_EXTEND_UNSIGNED): Ditto.
         (enum aarch64_abi_type): New enumeration tag.
         (AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators.
         (AARCH64_ABI_DEFAULT): Define to AARCH64_ABI_LP64 if undefined.
         (TARGET_ILP32): New define.
         * config/aarch64/aarch64.opt (mabi): New.
         (aarch64_abi): New.
         (ilp32, lp64): New values for -mabi.
         * config/aarch64/t-aarch64 (comma): New define.
         (MULTILIB_OPTIONS): Ditto.
         (MULTILIB_DIRNAMES): Ditto.
         * config/aarch64/t-aarch64-linux (MULTIARCH_DIRNAME): New define.
         * doc/invoke.texi: Document -mabi for AArch64.



On 06/26/13 23:59, Andrew Pinski wrote:
> On Wed, Jun 26, 2013 at 3:33 PM, Yufeng Zhang<Yufeng.Zhang@arm.com>  wrote:
>> This patch adds the configuration changes to the AArch64 GCC to support:
>>
>> * -milp32 and -mlp64 options in the compiler and the driver
>> * multilib of ilp32 and/or lp64 libraries
>> * differentiation of basic types in the compiler backend
>>
>> The patch enables --with-multilib-list configuration option for specifying
>> the list of library flavors to enable; the default value is "mlp64" and can
>> be overridden by --with-abi to "milp32".
>>
>> It also enables --with-abi for setting the default model in the compiler.
>> Its default value is "mlp64" unless --with-multilib-list is explicitly
>> specified with "milp32", in which case it defaults to "milp32".
>>
>> In the backend, two target flags are introduced: TARGET_ILP32 and
>> TARGET_LP64.  They are set by -milp32 and -mlp64 respectively, exclusive to
>> each other.  The default setting is via the option variable
>> aarch64_pmodel_flags, which defaults to TARGET_DEFAULT_PMODEL, which is
>> further defined in biarchlp64.h or biarchilp32.h depending which header file
>> is included.
>>
>>                            biarchlp64.h         biarchilp32.h
>> TARGET_DEFAULT_PMODEL     OPTION_MASK_LP64     OPTION_MASK_ILP32
>> TARGET_PMODEL             1                    2
>>
>> TARGET_ILP32 and TARGET_LP64 are implicitly defined as:
>>
>> #define TARGET_ILP32 ((aarch64_pmodel_flags&  OPTION_MASK_ILP32) != 0)
>> #define TARGET_LP64 ((aarch64_pmodel_flags&  OPTION_MASK_LP64) != 0)
>>
>> Note that the multilib support in the Linux toolchain is suppressed
>> deliberately.
>>
>> OK for the trunk?
>
>
> I think you should not support --with-multilib-list at all.  It should
> just include ilp32 multilib no matter what.  Note the linux multilib
> has to wait until the glibc/kernel side is done.
>
> Also:
> +#if TARGET_BIG_ENDIAN_DEFAULT == 1
> +#define EMUL_SUFFIX "b"
> +#else
> +#define EMUL_SUFFIX ""
> +#endif
>
> is broken when you supply the opposite endian option.
>
> Also you really should just use -mabi=ilp32 and -mabi=lp64 which
> reduces the number of changes needed to be done to config.gcc.
>
> You should use DRIVER_SELF_SPECS to simplify your LINKS_SPECS.
> Something like:
> #ifdef TARGET_BIG_ENDIAN_DEFAULT
> #define ENDIAN_SPEC "-mbig-endian"
> #else
> #define ENDIAN_SPEC "-mlittle-endian"
> #endif
> /* Force the default endianness and ABI flags onto the command line
>     in order to make the other specs easier to write.  */
> #undef DRIVER_SELF_SPECS
> #define DRIVER_SELF_SPECS \
>    " %{!mbig-endian:%{!mlittle-endian:" ENDIAN_SPEC "}}" \
>    " %{!milp32:%{!mlp64:-mlp64}}"
>
> or rather:
> " %{!mabi=*: -mabi=lp64}"
>
>
>
> And then in aarch64-elf-raw.h:
> #ifndef LINK_SPEC
> #define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \
> -maarch64elf%{milp32:32}%{mbig-endian:b}"
> #endif
>
> Or using the -mabi=* way:
> #ifndef LINK_SPEC
> #define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \
> -maarch64elf%{mabi=ilp32:32}%{mbig-endian:b}"
> #endif
>
>
>
> Thanks,
> Andrew Pinski

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 01-gcc-configury.patch --]
[-- Type: text/x-patch; name=01-gcc-configury.patch, Size: 12673 bytes --]

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 0ad7217..50dd045 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -497,6 +497,26 @@ then
 fi
 
 case ${target} in
+aarch64*-*-*)
+	case ${with_abi} in
+	"")
+		if test "x$with_multilib_list" = xilp32; then
+			tm_file="aarch64/biarchilp32.h ${tm_file}"
+		else
+			tm_file="aarch64/biarchlp64.h ${tm_file}"
+		fi
+		;;
+	ilp32)
+		tm_file="aarch64/biarchilp32.h ${tm_file}"
+		;;
+	lp64)
+		tm_file="aarch64/biarchlp64.h ${tm_file}"
+		;;
+	*)
+		echo "Unknown ABI used in --with-abi=$with_abi"
+		exit 1
+	esac
+	;;
 i[34567]86-*-*)
 	if test "x$with_abi" != x; then
 		echo "This target does not support --with-abi."
@@ -827,6 +847,22 @@ aarch64*-*-elf)
 		tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
 		;;
 	esac
+	aarch64_multilibs="${with_multilib_list}"
+	if test "$aarch64_multilibs" = "default"; then
+		aarch64_multilibs="lp64,ilp32"
+	fi
+	aarch64_multilibs=`echo $aarch64_multilibs | sed -e 's/,/ /g'`
+	for aarch64_multilib in ${aarch64_multilibs}; do
+		case ${aarch64_multilib} in
+		ilp32 | lp64 )
+			TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG},${aarch64_multilib}"
+			;;
+		*)
+			echo "--with-multilib-list=${aarch64_multilib} not supported."
+			exit 1
+		esac
+	done
+	TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's/^,//'`
 	;;
 aarch64*-*-linux*)
 	tm_file="${tm_file} dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h"
@@ -837,6 +873,24 @@ aarch64*-*-linux*)
 		tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
 		;;
 	esac
+	aarch64_multilibs="${with_multilib_list}"
+	if test "$aarch64_multilibs" = "default"; then
+		# TODO: turn on ILP32 multilib build after its support is mature.
+		# aarch64_multilibs="lp64,ilp32"
+		aarch64_multilibs="lp64"
+	fi
+	aarch64_multilibs=`echo $aarch64_multilibs | sed -e 's/,/ /g'`
+	for aarch64_multilib in ${aarch64_multilibs}; do
+		case ${aarch64_multilib} in
+		ilp32 | lp64 )
+			TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG},${aarch64_multilib}"
+			;;
+		*)
+			echo "--with-multilib-list=${aarch64_multilib} not supported."
+			exit 1
+		esac
+	done
+	TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's/^,//'`
 	;;
 alpha*-*-linux*)
 	tm_file="elfos.h ${tm_file} alpha/elf.h alpha/linux.h alpha/linux-elf.h glibc-stdint.h"
@@ -3147,7 +3201,7 @@ fi
 supported_defaults=
 case "${target}" in
 	aarch64*-*-*)
-		supported_defaults="cpu arch"
+		supported_defaults="abi cpu arch"
 		for which in cpu arch; do
 
 			eval "val=\$with_$which"
diff --git a/gcc/config/aarch64/aarch64-elf-raw.h b/gcc/config/aarch64/aarch64-elf-raw.h
index 1cd0155..dfaa9f4 100644
--- a/gcc/config/aarch64/aarch64-elf-raw.h
+++ b/gcc/config/aarch64/aarch64-elf-raw.h
@@ -26,7 +26,8 @@
 #define ENDFILE_SPEC " crtend%O%s crtn%O%s"
 
 #ifndef LINK_SPEC
-#define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X"
+#define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \
+  -maarch64elf%{mabi=ilp32*:32}%{mbig-endian:b}"
 #endif
 
 #endif /* GCC_AARCH64_ELF_RAW_H */
diff --git a/gcc/config/aarch64/aarch64-elf.h b/gcc/config/aarch64/aarch64-elf.h
index 3f3ae52..315a510 100644
--- a/gcc/config/aarch64/aarch64-elf.h
+++ b/gcc/config/aarch64/aarch64-elf.h
@@ -111,12 +111,37 @@
 
 #define GLOBAL_ASM_OP "\t.global\t"
 
+#ifdef TARGET_BIG_ENDIAN_DEFAULT
+#define ENDIAN_SPEC "-mbig-endian"
+#else
+#define ENDIAN_SPEC "-mlittle-endian"
+#endif
+
+#if TARGET_DATA_MODEL == 1
+#define ABI_SPEC  "-mabi=lp64"
+#define MULTILIB_DEFAULTS { "mabi=lp64" }
+#elif TARGET_DATA_MODEL == 2
+#define ABI_SPEC  "-mabi=ilp32"
+#define MULTILIB_DEFAULTS { "mabi=ilp32" }
+#else
+#error "Unknown or undefined TARGET_DATA_MODEL!"
+#endif
+
+/* Force the default endianness and ABI flags onto the command line
+   in order to make the other specs easier to write.  */
+#undef DRIVER_SELF_SPECS
+#define DRIVER_SELF_SPECS \
+  " %{!mbig-endian:%{!mlittle-endian:" ENDIAN_SPEC "}}" \
+  " %{!mabi=*:" ABI_SPEC "}"
+
 #ifndef ASM_SPEC
 #define ASM_SPEC "\
 %{mbig-endian:-EB} \
 %{mlittle-endian:-EL} \
 %{mcpu=*:-mcpu=%*} \
-%{march=*:-march=%*}"
+%{march=*:-march=%*} \
+%{mabi=ilp32*:-milp32} \
+%{mabi=lp64*:-mlp64}"
 #endif
 
 #undef TYPE_OPERAND_FMT
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 7bdb1e2..6011ab8 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -95,7 +95,9 @@
 
 #define INT_TYPE_SIZE		32
 
-#define LONG_TYPE_SIZE		64	/* XXX This should be an option */
+#define LONG_TYPE_SIZE		(TARGET_ILP32 ? 32 : 64)
+
+#define POINTER_SIZE		(TARGET_ILP32 ? 32 : 64)
 
 #define LONG_LONG_TYPE_SIZE	64
 
@@ -520,6 +522,18 @@ typedef struct GTY (()) machine_function
 } machine_function;
 #endif
 
+/* Which ABI to use.  */
+enum aarch64_abi_type
+{
+  AARCH64_ABI_LP64 = 0,
+  AARCH64_ABI_ILP32 = 1
+};
+
+#ifndef AARCH64_ABI_DEFAULT
+#define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64
+#endif
+
+#define TARGET_ILP32	(aarch64_abi & AARCH64_ABI_ILP32)
 
 enum arm_pcs
 {
@@ -694,7 +708,18 @@ do {									     \
 
 #define NO_FUNCTION_CSE	1
 
+/* Specify the machine mode that the hardware addresses have.
+   After generation of rtl, the compiler makes no further distinction
+   between pointers and any other objects of this machine mode.  */
 #define Pmode		DImode
+
+/* A C expression whose value is zero if pointers that need to be extended
+   from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
+   greater then zero if they are zero-extended and less then zero if the
+   ptr_extend instruction should be used.  */
+#define POINTERS_EXTEND_UNSIGNED 1
+
+/* Mode of a function address in a call instruction (for indexing purposes).  */
 #define FUNCTION_MODE	Pmode
 
 #define SELECT_CC_MODE(OP, X, Y)	aarch64_select_cc_mode (OP, X, Y)
diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
index 3518248..8ff6ca1 100644
--- a/gcc/config/aarch64/aarch64.opt
+++ b/gcc/config/aarch64/aarch64.opt
@@ -98,3 +98,17 @@ Target RejectNegative Joined Var(aarch64_cpu_string)
 mtune=
 Target RejectNegative Joined Var(aarch64_tune_string)
 -mtune=CPU	Optimize for CPU
+
+mabi=
+Target RejectNegative Joined Enum(aarch64_abi) Var(aarch64_abi) Init(AARCH64_ABI_DEFAULT)
+-mabi=ABI	Generate code that conforms to the specified ABI
+
+Enum
+Name(aarch64_abi) Type(int)
+Known AArch64 ABIs (for use with the -mabi= option):
+
+EnumValue
+Enum(aarch64_abi) String(ilp32) Value(AARCH64_ABI_ILP32)
+
+EnumValue
+Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64)
diff --git a/gcc/config/aarch64/biarchilp32.h b/gcc/config/aarch64/biarchilp32.h
new file mode 100644
index 0000000..fe13837
--- /dev/null
+++ b/gcc/config/aarch64/biarchilp32.h
@@ -0,0 +1,29 @@
+/* Make configure files to produce biarch compiler defaulting to ilp32 ABI.
+   This file must be included very first, while the OS specific file later
+   to overwrite otherwise wrong defaults.
+   Copyright (C) 2013 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+<http://www.gnu.org/licenses/>.  */
+
+#define AARCH64_ABI_DEFAULT AARCH64_ABI_ILP32
+#define TARGET_DATA_MODEL 2
diff --git a/gcc/config/aarch64/biarchlp64.h b/gcc/config/aarch64/biarchlp64.h
new file mode 100644
index 0000000..86803af
--- /dev/null
+++ b/gcc/config/aarch64/biarchlp64.h
@@ -0,0 +1,29 @@
+/* Make configure files to produce biarch compiler defaulting to ilp64 ABI.
+   This file must be included very first, while the OS specific file later
+   to overwrite otherwise wrong defaults.
+   Copyright (C) 2013 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+<http://www.gnu.org/licenses/>.  */
+
+#define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64
+#define TARGET_DATA_MODEL 1
diff --git a/gcc/config/aarch64/t-aarch64 b/gcc/config/aarch64/t-aarch64
index 4c265eb..2975850 100644
--- a/gcc/config/aarch64/t-aarch64
+++ b/gcc/config/aarch64/t-aarch64
@@ -34,3 +34,7 @@ aarch64-builtins.o: $(srcdir)/config/aarch64/aarch64-builtins.c $(CONFIG_H) \
   $(srcdir)/config/aarch64/aarch64-simd-builtins.def
 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
 		$(srcdir)/config/aarch64/aarch64-builtins.c
+
+comma=,
+MULTILIB_OPTIONS    = $(patsubst %, mabi=%, $(subst $(comma), ,$(TM_MULTILIB_CONFIG)))
+MULTILIB_DIRNAMES   = $(subst $(comma), ,$(TM_MULTILIB_CONFIG))
diff --git a/gcc/config/aarch64/t-aarch64-linux b/gcc/config/aarch64/t-aarch64-linux
index a7a0a88..ca1525e 100644
--- a/gcc/config/aarch64/t-aarch64-linux
+++ b/gcc/config/aarch64/t-aarch64-linux
@@ -23,3 +23,9 @@ LIB1ASMFUNCS = _aarch64_sync_cache_range
 
 AARCH_BE = $(if $(findstring TARGET_BIG_ENDIAN_DEFAULT=1, $(tm_defines)),_be)
 MULTILIB_OSDIRNAMES = .=../lib64$(call if_multiarch,:aarch64$(AARCH_BE)-linux-gnu)
+MULTIARCH_DIRNAME = $(call if_multiarch,aarch64$(AARCH_BE)-linux-gnu)
+
+# Disable the multilib for linux-gnu targets for the time being; focus
+# on the baremetal targets.
+MULTILIB_OPTIONS    =
+MULTILIB_DIRNAMES   =
diff --git a/gcc/configure.ac b/gcc/configure.ac
index eff48d6..6bad7d5 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -839,7 +839,7 @@ esac],
 [enable_languages=c])
 
 AC_ARG_WITH(multilib-list,
-[AS_HELP_STRING([--with-multilib-list], [select multilibs (SH and x86-64 only)])],
+[AS_HELP_STRING([--with-multilib-list], [select multilibs (AArch64, SH and x86-64 only)])],
 :,
 with_multilib_list=default)
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index dd82880..c3eff15 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -470,7 +470,7 @@ Objective-C and Objective-C++ Dialects}.
 @c so users have a clue at guessing where the ones they want will be.
 
 @emph{AArch64 Options}
-@gccoptlist{-mbig-endian  -mlittle-endian @gol
+@gccoptlist{-mabi=@var{name}  -mbig-endian  -mlittle-endian @gol
 -mgeneral-regs-only @gol
 -mcmodel=tiny  -mcmodel=small  -mcmodel=large @gol
 -mstrict-align @gol
@@ -10967,6 +10967,17 @@ These options are defined for AArch64 implementations:
 
 @table @gcctabopt
 
+@item -mabi=@var{name}
+@opindex mabi
+Generate code for the specified data model.  Permissible values
+are @samp{ilp32} for SysV-like data model where int, long int and pointer
+are 32-bit, and @samp{lp64} for SysV-like data model where int is 32-bit,
+but long int and pointer are 64-bit.
+
+The default depends on the specific target configuration.  Note that
+the LP64 and ILP32 ABIs are not link-compatible; you must compile your
+entire program with the same ABI, and link with a compatible set of libraries.
+
 @item -mbig-endian
 @opindex mbig-endian
 Generate big-endian code.  This is the default when GCC is configured for an

Re: [Patch, AArch64, ILP32] 1/5 Initial support - configury changes

[Andrew Pinski]

On Tue, Jul 2, 2013 at 11:53 AM, Yufeng Zhang <Yufeng.Zhang@arm.com> wrote:
> Hi Andrew,
>
> Please find the updated patch in the attachment that addresses your
> comments.
>
> It now builds both ilp32 and lp64 multilibs by default, with the
> --with-multilib-list support remaining to provide options to turn off one of
> them.
>
> -mabi=ilp32 and -mabi=lp64 are now the command line options to use.  The
> SPECs have been updated as well.

Thanks for doing this.  I like this patch much better than the first one.

Thanks,
Andrew

>
>
> Thanks,
> Yufeng
>
>
> gcc/
>         * config.gcc (aarch64*-*-*): Support --with-abi.
>         (aarch64*-*-elf): Support --with-multilib-list.
>         (aarch64*-*-linux*): Likewise.
>         (supported_defaults): Add abi to aarch64*-*-*.
>         * configure.ac: Mention AArch64 for --with-multilib-list.
>         * configure: Re-generated.
>         * config/aarch64/biarchilp32.h: New file.
>         * config/aarch64/biarchlp64.h: New file.
>         * config/aarch64/aarch64-elf.h (ENDIAN_SPEC): New define.
>         (ABI_SPEC): Ditto.
>         (MULTILIB_DEFAULTS): Ditto.
>         (DRIVER_SELF_SPECS): Ditto.
>         (ASM_SPEC): Update to also substitute -mabi.
>         * config/aarch64/aarch64-elf-raw.h (LINK_SPEC): Add linker script
>         file whose name depends on -mabi= and -mbig-endian.
>
>         * config/aarch64/aarch64.h (LONG_TYPE_SIZE): Change to depend on
>         TARGET_ILP32.
>         (POINTER_SIZE): New define.
>         (POINTERS_EXTEND_UNSIGNED): Ditto.
>         (enum aarch64_abi_type): New enumeration tag.
>         (AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators.
>         (AARCH64_ABI_DEFAULT): Define to AARCH64_ABI_LP64 if undefined.
>         (TARGET_ILP32): New define.
>         * config/aarch64/aarch64.opt (mabi): New.
>         (aarch64_abi): New.
>         (ilp32, lp64): New values for -mabi.
>
>         * config/aarch64/t-aarch64 (comma): New define.
>         (MULTILIB_OPTIONS): Ditto.
>         (MULTILIB_DIRNAMES): Ditto.
>         * config/aarch64/t-aarch64-linux (MULTIARCH_DIRNAME): New define.
>         * doc/invoke.texi: Document -mabi for AArch64.
>
>
>
>
> On 06/26/13 23:59, Andrew Pinski wrote:
>>
>> On Wed, Jun 26, 2013 at 3:33 PM, Yufeng Zhang<Yufeng.Zhang@arm.com>
>> wrote:
>>>
>>> This patch adds the configuration changes to the AArch64 GCC to support:
>>>
>>> * -milp32 and -mlp64 options in the compiler and the driver
>>> * multilib of ilp32 and/or lp64 libraries
>>> * differentiation of basic types in the compiler backend
>>>
>>> The patch enables --with-multilib-list configuration option for
>>> specifying
>>> the list of library flavors to enable; the default value is "mlp64" and
>>> can
>>> be overridden by --with-abi to "milp32".
>>>
>>> It also enables --with-abi for setting the default model in the compiler.
>>> Its default value is "mlp64" unless --with-multilib-list is explicitly
>>> specified with "milp32", in which case it defaults to "milp32".
>>>
>>> In the backend, two target flags are introduced: TARGET_ILP32 and
>>> TARGET_LP64.  They are set by -milp32 and -mlp64 respectively, exclusive
>>> to
>>> each other.  The default setting is via the option variable
>>> aarch64_pmodel_flags, which defaults to TARGET_DEFAULT_PMODEL, which is
>>> further defined in biarchlp64.h or biarchilp32.h depending which header
>>> file
>>> is included.
>>>
>>>                            biarchlp64.h         biarchilp32.h
>>> TARGET_DEFAULT_PMODEL     OPTION_MASK_LP64     OPTION_MASK_ILP32
>>> TARGET_PMODEL             1                    2
>>>
>>> TARGET_ILP32 and TARGET_LP64 are implicitly defined as:
>>>
>>> #define TARGET_ILP32 ((aarch64_pmodel_flags&  OPTION_MASK_ILP32) != 0)
>>> #define TARGET_LP64 ((aarch64_pmodel_flags&  OPTION_MASK_LP64) != 0)
>>>
>>>
>>> Note that the multilib support in the Linux toolchain is suppressed
>>> deliberately.
>>>
>>> OK for the trunk?
>>
>>
>>
>> I think you should not support --with-multilib-list at all.  It should
>> just include ilp32 multilib no matter what.  Note the linux multilib
>> has to wait until the glibc/kernel side is done.
>>
>> Also:
>> +#if TARGET_BIG_ENDIAN_DEFAULT == 1
>> +#define EMUL_SUFFIX "b"
>> +#else
>> +#define EMUL_SUFFIX ""
>> +#endif
>>
>> is broken when you supply the opposite endian option.
>>
>> Also you really should just use -mabi=ilp32 and -mabi=lp64 which
>> reduces the number of changes needed to be done to config.gcc.
>>
>> You should use DRIVER_SELF_SPECS to simplify your LINKS_SPECS.
>> Something like:
>> #ifdef TARGET_BIG_ENDIAN_DEFAULT
>> #define ENDIAN_SPEC "-mbig-endian"
>> #else
>> #define ENDIAN_SPEC "-mlittle-endian"
>> #endif
>> /* Force the default endianness and ABI flags onto the command line
>>     in order to make the other specs easier to write.  */
>> #undef DRIVER_SELF_SPECS
>> #define DRIVER_SELF_SPECS \
>>    " %{!mbig-endian:%{!mlittle-endian:" ENDIAN_SPEC "}}" \
>>    " %{!milp32:%{!mlp64:-mlp64}}"
>>
>> or rather:
>> " %{!mabi=*: -mabi=lp64}"
>>
>>
>>
>> And then in aarch64-elf-raw.h:
>> #ifndef LINK_SPEC
>> #define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \
>> -maarch64elf%{milp32:32}%{mbig-endian:b}"
>> #endif
>>
>> Or using the -mabi=* way:
>> #ifndef LINK_SPEC
>> #define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \
>> -maarch64elf%{mabi=ilp32:32}%{mbig-endian:b}"
>> #endif
>>
>>
>>
>> Thanks,
>> Andrew Pinski

Re: [Ping] [Patch, AArch64, ILP32] 3/5 Minor change in function.c:assign_parm_find_data_types()

[Yufeng Zhang]

Ping~

Can I get an OK please if there is no objection?

Regards,
Yufeng

On 06/26/13 23:39, Yufeng Zhang wrote:
> This patch updates assign_parm_find_data_types to assign passed_mode and
> nominal_mode with the mode of the built pointer type instead of the
> hard-coded Pmode in the case of pass-by-reference.  This is in line with
> the assignment to passed_mode and nominal_mode in other cases inside the
> function.
>
> assign_parm_find_data_types generally uses TYPE_MODE to calculate
> passed_mode and nominal_mode:
>
>     /* Find mode of arg as it is passed, and mode of arg as it should be
>        during execution of this function.  */
>     passed_mode = TYPE_MODE (passed_type);
>     nominal_mode = TYPE_MODE (nominal_type);
>
> this includes the case when the passed argument is a pointer by itself.
>
> However there is a discrepancy when it deals with argument passed by
> invisible reference; it builds the argument's corresponding pointer
> type, but sets passed_mode and nominal_mode with Pmode directly.
>
> This is OK for targets where Pmode == ptr_mode, but on AArch64 with
> ILP32 they are different with Pmode as DImode and ptr_mode as SImode.
> When such a reference is passed on stack, the reference is prepared by
> the caller in the lower 4 bytes of an 8-byte slot but is fetched by the
> callee as an 8-byte datum, of which the higher 4 bytes may contain junk.
>    It is probably the combination of Pmode != ptr_mode and the particular
> ABI specification that make the AArch64 ILP32 the first target on which
> the issue manifests itself.
>
> Bootstrapped on x86_64-none-linux-gnu.
>
> OK for the trunk?
>
> Thanks,
> Yufeng
>
>
> gcc/
> 	* function.c (assign_parm_find_data_types): Set passed_mode and
> 	nominal_mode to the TYPE_MODE of nominal_type for the built
> 	pointer type in case of the struct-pass-by-reference.

Re: [Ping^2] [Patch, AArch64, ILP32] 3/5 Minor change in function.c:assign_parm_find_data_types()

[Yufeng Zhang]

Ping^2~

Thanks,
Yufeng


On 07/02/13 23:44, Yufeng Zhang wrote:
> Ping~
>
> Can I get an OK please if there is no objection?
>
> Regards,
> Yufeng
>
> On 06/26/13 23:39, Yufeng Zhang wrote:
>> This patch updates assign_parm_find_data_types to assign passed_mode and
>> nominal_mode with the mode of the built pointer type instead of the
>> hard-coded Pmode in the case of pass-by-reference.  This is in line with
>> the assignment to passed_mode and nominal_mode in other cases inside the
>> function.
>>
>> assign_parm_find_data_types generally uses TYPE_MODE to calculate
>> passed_mode and nominal_mode:
>>
>>      /* Find mode of arg as it is passed, and mode of arg as it should be
>>         during execution of this function.  */
>>      passed_mode = TYPE_MODE (passed_type);
>>      nominal_mode = TYPE_MODE (nominal_type);
>>
>> this includes the case when the passed argument is a pointer by itself.
>>
>> However there is a discrepancy when it deals with argument passed by
>> invisible reference; it builds the argument's corresponding pointer
>> type, but sets passed_mode and nominal_mode with Pmode directly.
>>
>> This is OK for targets where Pmode == ptr_mode, but on AArch64 with
>> ILP32 they are different with Pmode as DImode and ptr_mode as SImode.
>> When such a reference is passed on stack, the reference is prepared by
>> the caller in the lower 4 bytes of an 8-byte slot but is fetched by the
>> callee as an 8-byte datum, of which the higher 4 bytes may contain junk.
>>     It is probably the combination of Pmode != ptr_mode and the particular
>> ABI specification that make the AArch64 ILP32 the first target on which
>> the issue manifests itself.
>>
>> Bootstrapped on x86_64-none-linux-gnu.
>>
>> OK for the trunk?
>>
>> Thanks,
>> Yufeng
>>
>>
>> gcc/
>> 	* function.c (assign_parm_find_data_types): Set passed_mode and
>> 	nominal_mode to the TYPE_MODE of nominal_type for the built
>> 	pointer type in case of the struct-pass-by-reference.
>
>
>

Re: [Ping] [Patch, AArch64, ILP32] 1/5 Initial support - configury changes

[Yufeng Zhang]

Ping~

Thanks,
Yufeng

On 07/02/13 19:53, Yufeng Zhang wrote:
> Hi Andrew,
>
> Please find the updated patch in the attachment that addresses your
> comments.
>
> It now builds both ilp32 and lp64 multilibs by default, with the
> --with-multilib-list support remaining to provide options to turn off
> one of them.
>
> -mabi=ilp32 and -mabi=lp64 are now the command line options to use.  The
> SPECs have been updated as well.
>
> Thanks,
> Yufeng
>
>
> gcc/
>           * config.gcc (aarch64*-*-*): Support --with-abi.
>           (aarch64*-*-elf): Support --with-multilib-list.
>           (aarch64*-*-linux*): Likewise.
>           (supported_defaults): Add abi to aarch64*-*-*.
>           * configure.ac: Mention AArch64 for --with-multilib-list.
>           * configure: Re-generated.
>           * config/aarch64/biarchilp32.h: New file.
>           * config/aarch64/biarchlp64.h: New file.
>           * config/aarch64/aarch64-elf.h (ENDIAN_SPEC): New define.
>           (ABI_SPEC): Ditto.
>           (MULTILIB_DEFAULTS): Ditto.
>           (DRIVER_SELF_SPECS): Ditto.
>           (ASM_SPEC): Update to also substitute -mabi.
>           * config/aarch64/aarch64-elf-raw.h (LINK_SPEC): Add linker script
>           file whose name depends on -mabi= and -mbig-endian.
>           * config/aarch64/aarch64.h (LONG_TYPE_SIZE): Change to depend on
>           TARGET_ILP32.
>           (POINTER_SIZE): New define.
>           (POINTERS_EXTEND_UNSIGNED): Ditto.
>           (enum aarch64_abi_type): New enumeration tag.
>           (AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators.
>           (AARCH64_ABI_DEFAULT): Define to AARCH64_ABI_LP64 if undefined.
>           (TARGET_ILP32): New define.
>           * config/aarch64/aarch64.opt (mabi): New.
>           (aarch64_abi): New.
>           (ilp32, lp64): New values for -mabi.
>           * config/aarch64/t-aarch64 (comma): New define.
>           (MULTILIB_OPTIONS): Ditto.
>           (MULTILIB_DIRNAMES): Ditto.
>           * config/aarch64/t-aarch64-linux (MULTIARCH_DIRNAME): New define.
>           * doc/invoke.texi: Document -mabi for AArch64.
>
>
>
> On 06/26/13 23:59, Andrew Pinski wrote:
>> On Wed, Jun 26, 2013 at 3:33 PM, Yufeng Zhang<Yufeng.Zhang@arm.com>   wrote:
>>> This patch adds the configuration changes to the AArch64 GCC to support:
>>>
>>> * -milp32 and -mlp64 options in the compiler and the driver
>>> * multilib of ilp32 and/or lp64 libraries
>>> * differentiation of basic types in the compiler backend
>>>
>>> The patch enables --with-multilib-list configuration option for specifying
>>> the list of library flavors to enable; the default value is "mlp64" and can
>>> be overridden by --with-abi to "milp32".
>>>
>>> It also enables --with-abi for setting the default model in the compiler.
>>> Its default value is "mlp64" unless --with-multilib-list is explicitly
>>> specified with "milp32", in which case it defaults to "milp32".
>>>
>>> In the backend, two target flags are introduced: TARGET_ILP32 and
>>> TARGET_LP64.  They are set by -milp32 and -mlp64 respectively, exclusive to
>>> each other.  The default setting is via the option variable
>>> aarch64_pmodel_flags, which defaults to TARGET_DEFAULT_PMODEL, which is
>>> further defined in biarchlp64.h or biarchilp32.h depending which header file
>>> is included.
>>>
>>>                             biarchlp64.h         biarchilp32.h
>>> TARGET_DEFAULT_PMODEL     OPTION_MASK_LP64     OPTION_MASK_ILP32
>>> TARGET_PMODEL             1                    2
>>>
>>> TARGET_ILP32 and TARGET_LP64 are implicitly defined as:
>>>
>>> #define TARGET_ILP32 ((aarch64_pmodel_flags&   OPTION_MASK_ILP32) != 0)
>>> #define TARGET_LP64 ((aarch64_pmodel_flags&   OPTION_MASK_LP64) != 0)
>>>
>>> Note that the multilib support in the Linux toolchain is suppressed
>>> deliberately.
>>>
>>> OK for the trunk?
>>
>>
>> I think you should not support --with-multilib-list at all.  It should
>> just include ilp32 multilib no matter what.  Note the linux multilib
>> has to wait until the glibc/kernel side is done.
>>
>> Also:
>> +#if TARGET_BIG_ENDIAN_DEFAULT == 1
>> +#define EMUL_SUFFIX "b"
>> +#else
>> +#define EMUL_SUFFIX ""
>> +#endif
>>
>> is broken when you supply the opposite endian option.
>>
>> Also you really should just use -mabi=ilp32 and -mabi=lp64 which
>> reduces the number of changes needed to be done to config.gcc.
>>
>> You should use DRIVER_SELF_SPECS to simplify your LINKS_SPECS.
>> Something like:
>> #ifdef TARGET_BIG_ENDIAN_DEFAULT
>> #define ENDIAN_SPEC "-mbig-endian"
>> #else
>> #define ENDIAN_SPEC "-mlittle-endian"
>> #endif
>> /* Force the default endianness and ABI flags onto the command line
>>      in order to make the other specs easier to write.  */
>> #undef DRIVER_SELF_SPECS
>> #define DRIVER_SELF_SPECS \
>>     " %{!mbig-endian:%{!mlittle-endian:" ENDIAN_SPEC "}}" \
>>     " %{!milp32:%{!mlp64:-mlp64}}"
>>
>> or rather:
>> " %{!mabi=*: -mabi=lp64}"
>>
>>
>>
>> And then in aarch64-elf-raw.h:
>> #ifndef LINK_SPEC
>> #define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \
>> -maarch64elf%{milp32:32}%{mbig-endian:b}"
>> #endif
>>
>> Or using the -mabi=* way:
>> #ifndef LINK_SPEC
>> #define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \
>> -maarch64elf%{mabi=ilp32:32}%{mbig-endian:b}"
>> #endif
>>
>>
>>
>> Thanks,
>> Andrew Pinski

Re: [Ping] [Patch, AArch64, ILP32] 2/5 More backend changes and support for small absolute and small PIC addressing models

[Yufeng Zhang]

Ping~

Thanks,
Yufeng

On 06/26/13 23:35, Yufeng Zhang wrote:
> This patch updates the AArch64 backend to support the small absolute and
> small PIC addressing models for ILP32; it also updates a number of other
> backend macros and hooks in order to support ILP32.
>
> OK for the trunk?
>
> Thanks,
> Yufeng
>
>
> gcc/
>
>           * config/aarch64/aarch64.c (POINTER_BYTES): New define.
>           (aarch64_load_symref_appropriately): In the case of
>           SYMBOL_SMALL_ABSOLUTE, use the mode of 'dest' instead of Pmode
>           to generate new rtx; likewise to the case of SYMBOL_SMALL_GOT.
>           (aarch64_expand_mov_immediate): In the case of SYMBOL_FORCE_TO_MEM,
>           change to pass 'ptr_mode' to force_const_mem and zero-extend 'mem'
>           if 'mode' doesn't equal to 'ptr_mode'.
>           (aarch64_output_mi_thunk): Add an assertion on the alignment of
>           'vcall_offset'; change to call aarch64_emit_move differently
> depending
>           on whether 'Pmode' equals to 'ptr_mode' or not; use 'POINTER_BYTES'
>           to calculate the upper bound of 'vcall_offset'.
>           (aarch64_cannot_force_const_mem): Change to also return true if
>           mode != ptr_mode.
>           (aarch64_legitimize_reload_address): In the case of large
>           displacements, add new local variable 'xmode' and an assertion
>           based on it; change to use 'xmode' to generate the new rtx and
>           reload.
>           (aarch64_asm_trampoline_template): Change to generate the template
>           differently depending on TARGET_ILP32 or not; change to use
>           'POINTER_BYTES' in the argument passed to assemble_aligned_integer.
>           (aarch64_trampoline_size): Removed.
>           (aarch64_trampoline_init): Add new local constant 'tramp_code_sz'
>           and replace immediate literals with it.  Change to use 'ptr_mode'
>           instead of 'DImode' and call convert_memory_address if the mode
>           of 'fnaddr' doesn't equal to 'ptr_mode'.
>           (aarch64_elf_asm_constructor): Change to use
> assemble_aligned_integer
>           to output symbol.
>           (aarch64_elf_asm_destructor): Likewise.
>           * config/aarch64/aarch64.h (TRAMPOLINE_SIZE): Change to be
> dependent
>           on TARGET_ILP32 instead of aarch64_trampoline_size.
>           * config/aarch64/aarch64.md (movsi_aarch64): Add new alternatives
>           of 'mov' between WSP and W registers as well as 'adr' and 'adrp'.
>           (loadwb_pair<GPI:mode>_<PTR:mode>): Rename to ...
>           (loadwb_pair<GPI:mode>_<P:mode>): ... this.  Replace PTR with P.
>           (storewb_pair<GPI:mode>_<PTR:mode>): Likewise; rename to ...
>           (storewb_pair<GPI:mode>_<P:mode>): ... this.
>           (add_losym): Change to 'define_expand' and call
> gen_add_losym_<mode>
>           depending on the value of 'mode'.
>           (add_losym_<mode>): New.
>           (ldr_got_small_<mode>): New, based on ldr_got_small.
>           (ldr_got_small): Remove.
>           (ldr_got_small_sidi): New.
>           * config/aarch64/iterators.md (P): New.
>           (PTR): Change to 'ptr_mode' in the condition.

Re: [Ping^3] [Patch, AArch64, ILP32] 3/5 Minor change in function.c:assign_parm_find_data_types()

[Yufeng Zhang]

Ping^3~

Thanks,
Yufeng

On 07/08/13 11:11, Yufeng Zhang wrote:
> Ping^2~
>
> Thanks,
> Yufeng
>
>
> On 07/02/13 23:44, Yufeng Zhang wrote:
>> Ping~
>>
>> Can I get an OK please if there is no objection?
>>
>> Regards,
>> Yufeng
>>
>> On 06/26/13 23:39, Yufeng Zhang wrote:
>>> This patch updates assign_parm_find_data_types to assign passed_mode and
>>> nominal_mode with the mode of the built pointer type instead of the
>>> hard-coded Pmode in the case of pass-by-reference.  This is in line with
>>> the assignment to passed_mode and nominal_mode in other cases inside the
>>> function.
>>>
>>> assign_parm_find_data_types generally uses TYPE_MODE to calculate
>>> passed_mode and nominal_mode:
>>>
>>>       /* Find mode of arg as it is passed, and mode of arg as it should be
>>>          during execution of this function.  */
>>>       passed_mode = TYPE_MODE (passed_type);
>>>       nominal_mode = TYPE_MODE (nominal_type);
>>>
>>> this includes the case when the passed argument is a pointer by itself.
>>>
>>> However there is a discrepancy when it deals with argument passed by
>>> invisible reference; it builds the argument's corresponding pointer
>>> type, but sets passed_mode and nominal_mode with Pmode directly.
>>>
>>> This is OK for targets where Pmode == ptr_mode, but on AArch64 with
>>> ILP32 they are different with Pmode as DImode and ptr_mode as SImode.
>>> When such a reference is passed on stack, the reference is prepared by
>>> the caller in the lower 4 bytes of an 8-byte slot but is fetched by the
>>> callee as an 8-byte datum, of which the higher 4 bytes may contain junk.
>>>      It is probably the combination of Pmode != ptr_mode and the particular
>>> ABI specification that make the AArch64 ILP32 the first target on which
>>> the issue manifests itself.
>>>
>>> Bootstrapped on x86_64-none-linux-gnu.
>>>
>>> OK for the trunk?
>>>
>>> Thanks,
>>> Yufeng
>>>
>>>
>>> gcc/
>>> 	* function.c (assign_parm_find_data_types): Set passed_mode and
>>> 	nominal_mode to the TYPE_MODE of nominal_type for the built
>>> 	pointer type in case of the struct-pass-by-reference.
>>
>>
>>
>
>
>

Re: [Ping] [Patch, AArch64, ILP32] 4/5 Change tests to be ILP32-friendly

[Yufeng Zhang]

Ping~

Thanks,
Yufeng

On 06/26/13 23:41, Yufeng Zhang wrote:
> The attached patch fixes a few gcc test cases.
>
>
> Thanks,
> Yufeng
>
>
> gcc/testsuite/
>
> 	* gcc.dg/20020219-1.c: Skip the test on aarch64*-*-* in ilp32.
> 	* gcc.target/aarch64/aapcs64/test_18.c (struct y): Change the field
> 	type from long to long long.
> 	* gcc.target/aarch64/atomic-op-long.c: Update dg-final directives
> 	to have effective-target keywords of lp64 and ilp32.
> 	* gcc.target/aarch64/fcvt_double_int.c: Likewise.
> 	* gcc.target/aarch64/fcvt_double_long.c: Likewise.
> 	* gcc.target/aarch64/fcvt_double_uint.c: Likewise.
> 	* gcc.target/aarch64/fcvt_double_ulong.c: Likewise.
> 	* gcc.target/aarch64/fcvt_float_int.c: Likewise.
> 	* gcc.target/aarch64/fcvt_float_long.c: Likewise.
> 	* gcc.target/aarch64/fcvt_float_uint.c: Likewise.
> 	* gcc.target/aarch64/fcvt_float_ulong.c: Likewise.
> 	* gcc.target/aarch64/vect_smlal_1.c: Replace 'long' with 'long long'.

Re: [Ping] [Patch, AArch64, ILP32] 5/5 Define _ILP32 and __ILP32__

[Yufeng Zhang]

Ping~

Thanks,
Yufeng

On 06/26/13 23:42, Yufeng Zhang wrote:
> This patch defines _ILP32 and __ILP32__ for the AArch64 port when the
> ILP32 ABI is in use.
>
> This helps libraries, e.g. libgloss and glibc, recognize which model is
> being compiled.
>
> OK for the trunk?
>
> Thanks,
> Yufeng
>
>
> gcc/
> 	* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define _ILP32
> 	and __ILP32__ when the ILP32 model is in use.

Re: [Ping] [Patch, AArch64, ILP32] Pad pointer-typed stack argument downward in ILP32

[Yufeng Zhang]

Ping~

Thanks,
Yufeng

On 06/27/13 17:00, Yufeng Zhang wrote:
> This patch fixes the bug that pointer-typed argument passed on stack is
> not padded properly in ILP32.
>
> OK for the trunk?
>
> Thanks,
> Yufeng
>
>
>
> gcc/
>
>           * config/aarch64/aarch64.c (aarch64_pad_arg_upward): In big-endian,
>           pad pointer-typed argument downward.
>
> gcc/testsuite/
>
>           * gcc.target/aarch64/test-ptr-arg-on-stack-1.c: New test.
>

Re: [Patch, AArch64, ILP32] 2/5 More backend changes and support for small absolute and small PIC addressing models

[Marcus Shawcroft]

On 26 June 2013 23:35, Yufeng Zhang <Yufeng.Zhang@arm.com> wrote:
> This patch updates the AArch64 backend to support the small absolute and
> small PIC addressing models for ILP32; it also updates a number of other
> backend macros and hooks in order to support ILP32.
>
> OK for the trunk?

OK
/Marcus

Re: [Patch, AArch64, ILP32] 1/5 Initial support - configury changes

[Marcus Shawcroft]

On 2 July 2013 19:53, Yufeng Zhang <Yufeng.Zhang@arm.com> wrote:
> Hi Andrew,
>
> Please find the updated patch in the attachment that addresses your
> comments.
>
> It now builds both ilp32 and lp64 multilibs by default, with the
> --with-multilib-list support remaining to provide options to turn off one of
> them.
>
> -mabi=ilp32 and -mabi=lp64 are now the command line options to use.  The
> SPECs have been updated as well.
>
>
> Thanks,
> Yufeng

OK
/Marcus

Re: [Patch, AArch64, ILP32] 3/5 Minor change in function.c:assign_parm_find_data_types()

[Marcus Shawcroft]

On 26 June 2013 23:39, Yufeng Zhang <Yufeng.Zhang@arm.com> wrote:
> This patch updates assign_parm_find_data_types to assign passed_mode and
> nominal_mode with the mode of the built pointer type instead of the
> hard-coded Pmode in the case of pass-by-reference.  This is in line with the
> assignment to passed_mode and nominal_mode in other cases inside the
> function.
>
> assign_parm_find_data_types generally uses TYPE_MODE to calculate
> passed_mode and nominal_mode:
>
>   /* Find mode of arg as it is passed, and mode of arg as it should be
>      during execution of this function.  */
>   passed_mode = TYPE_MODE (passed_type);
>   nominal_mode = TYPE_MODE (nominal_type);
>
> this includes the case when the passed argument is a pointer by itself.
>
> However there is a discrepancy when it deals with argument passed by
> invisible reference; it builds the argument's corresponding pointer type,
> but sets passed_mode and nominal_mode with Pmode directly.
>
> This is OK for targets where Pmode == ptr_mode, but on AArch64 with ILP32
> they are different with Pmode as DImode and ptr_mode as SImode. When such a
> reference is passed on stack, the reference is prepared by the caller in the
> lower 4 bytes of an 8-byte slot but is fetched by the callee as an 8-byte
> datum, of which the higher 4 bytes may contain junk.  It is probably the
> combination of Pmode != ptr_mode and the particular ABI specification that
> make the AArch64 ILP32 the first target on which the issue manifests itself.
>
> Bootstrapped on x86_64-none-linux-gnu.
>
> OK for the trunk?

Yufeng, this change makes sense to me, however I can't approve such a change.
/Marcus

Re: [Patch, AArch64, ILP32] 4/5 Change tests to be ILP32-friendly

[Marcus Shawcroft]

On 26 June 2013 23:41, Yufeng Zhang <Yufeng.Zhang@arm.com> wrote:

> gcc/testsuite/
>
>         * gcc.dg/20020219-1.c: Skip the test on aarch64*-*-* in ilp32.
>         * gcc.target/aarch64/aapcs64/test_18.c (struct y): Change the field
>         type from long to long long.
>         * gcc.target/aarch64/atomic-op-long.c: Update dg-final directives
>         to have effective-target keywords of lp64 and ilp32.
>         * gcc.target/aarch64/fcvt_double_int.c: Likewise.
>         * gcc.target/aarch64/fcvt_double_long.c: Likewise.
>         * gcc.target/aarch64/fcvt_double_uint.c: Likewise.
>         * gcc.target/aarch64/fcvt_double_ulong.c: Likewise.
>         * gcc.target/aarch64/fcvt_float_int.c: Likewise.
>         * gcc.target/aarch64/fcvt_float_long.c: Likewise.
>         * gcc.target/aarch64/fcvt_float_uint.c: Likewise.
>         * gcc.target/aarch64/fcvt_float_ulong.c: Likewise.
>         * gcc.target/aarch64/vect_smlal_1.c: Replace 'long' with 'long
> long'.
>

OK
/Marcus

Re: [Patch, AArch64, ILP32] 5/5 Define _ILP32 and __ILP32__

[Marcus Shawcroft]

On 26 June 2013 23:42, Yufeng Zhang <Yufeng.Zhang@arm.com> wrote:

> gcc/
>         * config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define _ILP32
>         and __ILP32__ when the ILP32 model is in use.
>

OK
/Marcus

Re: [Patch, AArch64, ILP32] Pad pointer-typed stack argument downward in ILP32

[Marcus Shawcroft]

On 27 June 2013 17:00, Yufeng Zhang <Yufeng.Zhang@arm.com> wrote:
> This patch fixes the bug that pointer-typed argument passed on stack is not
> padded properly in ILP32.
>
> OK for the trunk?

OK
/Marcus

Re: [Ping^4] [Patch, AArch64, ILP32] 3/5 Minor change in function.c:assign_parm_find_data_types()

[Yufeng Zhang]

Ping^4~

I am aware that it is currently holiday season, but it would be really 
nice if this tiny patch can get some further comments even if it is not 
an approval.

The original RFA email is here:
http://gcc.gnu.org/ml/gcc-patches/2013-06/msg01485.html

Regards,
Yufeng

On 07/18/13 11:28, Yufeng Zhang wrote:
> Ping^3~
>
> Thanks,
> Yufeng
>
> On 07/08/13 11:11, Yufeng Zhang wrote:
>> Ping^2~
>>
>> Thanks,
>> Yufeng
>>
>>
>> On 07/02/13 23:44, Yufeng Zhang wrote:
>>> Ping~
>>>
>>> Can I get an OK please if there is no objection?
>>>
>>> Regards,
>>> Yufeng
>>>
>>> On 06/26/13 23:39, Yufeng Zhang wrote:
>>>> This patch updates assign_parm_find_data_types to assign passed_mode and
>>>> nominal_mode with the mode of the built pointer type instead of the
>>>> hard-coded Pmode in the case of pass-by-reference.  This is in line with
>>>> the assignment to passed_mode and nominal_mode in other cases inside the
>>>> function.
>>>>
>>>> assign_parm_find_data_types generally uses TYPE_MODE to calculate
>>>> passed_mode and nominal_mode:
>>>>
>>>>        /* Find mode of arg as it is passed, and mode of arg as it should be
>>>>           during execution of this function.  */
>>>>        passed_mode = TYPE_MODE (passed_type);
>>>>        nominal_mode = TYPE_MODE (nominal_type);
>>>>
>>>> this includes the case when the passed argument is a pointer by itself.
>>>>
>>>> However there is a discrepancy when it deals with argument passed by
>>>> invisible reference; it builds the argument's corresponding pointer
>>>> type, but sets passed_mode and nominal_mode with Pmode directly.
>>>>
>>>> This is OK for targets where Pmode == ptr_mode, but on AArch64 with
>>>> ILP32 they are different with Pmode as DImode and ptr_mode as SImode.
>>>> When such a reference is passed on stack, the reference is prepared by
>>>> the caller in the lower 4 bytes of an 8-byte slot but is fetched by the
>>>> callee as an 8-byte datum, of which the higher 4 bytes may contain junk.
>>>>       It is probably the combination of Pmode != ptr_mode and the particular
>>>> ABI specification that make the AArch64 ILP32 the first target on which
>>>> the issue manifests itself.
>>>>
>>>> Bootstrapped on x86_64-none-linux-gnu.
>>>>
>>>> OK for the trunk?
>>>>
>>>> Thanks,
>>>> Yufeng
>>>>
>>>>
>>>> gcc/
>>>> 	* function.c (assign_parm_find_data_types): Set passed_mode and
>>>> 	nominal_mode to the TYPE_MODE of nominal_type for the built
>>>> 	pointer type in case of the struct-pass-by-reference.
>>>
>>>
>>>
>>
>>
>>
>
>
>

Re: [Ping^4] [Patch, AArch64, ILP32] 3/5 Minor change in function.c:assign_parm_find_data_types()

[Andrew Pinski]

On Thu, Aug 15, 2013 at 11:21 AM, Yufeng Zhang <Yufeng.Zhang@arm.com> wrote:
> Ping^4~
>
> I am aware that it is currently holiday season, but it would be really nice
> if this tiny patch can get some further comments even if it is not an
> approval.
>
> The original RFA email is here:
> http://gcc.gnu.org/ml/gcc-patches/2013-06/msg01485.html

From my point of view it is correct after understanding the ABI better
though I cannot approve it.

Thanks,
Andrew Pinski

>
> Regards,
> Yufeng
>
>
> On 07/18/13 11:28, Yufeng Zhang wrote:
>>
>> Ping^3~
>>
>> Thanks,
>> Yufeng
>>
>> On 07/08/13 11:11, Yufeng Zhang wrote:
>>>
>>> Ping^2~
>>>
>>> Thanks,
>>> Yufeng
>>>
>>>
>>> On 07/02/13 23:44, Yufeng Zhang wrote:
>>>>
>>>> Ping~
>>>>
>>>> Can I get an OK please if there is no objection?
>>>>
>>>> Regards,
>>>> Yufeng
>>>>
>>>> On 06/26/13 23:39, Yufeng Zhang wrote:
>>>>>
>>>>> This patch updates assign_parm_find_data_types to assign passed_mode
>>>>> and
>>>>> nominal_mode with the mode of the built pointer type instead of the
>>>>> hard-coded Pmode in the case of pass-by-reference.  This is in line
>>>>> with
>>>>> the assignment to passed_mode and nominal_mode in other cases inside
>>>>> the
>>>>> function.
>>>>>
>>>>> assign_parm_find_data_types generally uses TYPE_MODE to calculate
>>>>> passed_mode and nominal_mode:
>>>>>
>>>>>        /* Find mode of arg as it is passed, and mode of arg as it
>>>>> should be
>>>>>           during execution of this function.  */
>>>>>        passed_mode = TYPE_MODE (passed_type);
>>>>>        nominal_mode = TYPE_MODE (nominal_type);
>>>>>
>>>>> this includes the case when the passed argument is a pointer by itself.
>>>>>
>>>>> However there is a discrepancy when it deals with argument passed by
>>>>> invisible reference; it builds the argument's corresponding pointer
>>>>> type, but sets passed_mode and nominal_mode with Pmode directly.
>>>>>
>>>>> This is OK for targets where Pmode == ptr_mode, but on AArch64 with
>>>>> ILP32 they are different with Pmode as DImode and ptr_mode as SImode.
>>>>> When such a reference is passed on stack, the reference is prepared by
>>>>> the caller in the lower 4 bytes of an 8-byte slot but is fetched by the
>>>>> callee as an 8-byte datum, of which the higher 4 bytes may contain
>>>>> junk.
>>>>>       It is probably the combination of Pmode != ptr_mode and the
>>>>> particular
>>>>> ABI specification that make the AArch64 ILP32 the first target on which
>>>>> the issue manifests itself.
>>>>>
>>>>> Bootstrapped on x86_64-none-linux-gnu.
>>>>>
>>>>> OK for the trunk?
>>>>>
>>>>> Thanks,
>>>>> Yufeng
>>>>>
>>>>>
>>>>> gcc/
>>>>>         * function.c (assign_parm_find_data_types): Set passed_mode and
>>>>>         nominal_mode to the TYPE_MODE of nominal_type for the built
>>>>>         pointer type in case of the struct-pass-by-reference.
>>>>
>>>>
>>>>
>>>>
>>>
>>>
>>>
>>
>>
>>
>
>

Re: [Ping^4] [Patch, AArch64, ILP32] 3/5 Minor change in function.c:assign_parm_find_data_types()

[Richard Henderson]

On 08/15/2013 11:21 AM, Yufeng Zhang wrote:
> Ping^4~
> 
> I am aware that it is currently holiday season, but it would be really nice if
> this tiny patch can get some further comments even if it is not an approval.
> 
> The original RFA email is here:
> http://gcc.gnu.org/ml/gcc-patches/2013-06/msg01485.html
> 

Ok.

It probably would have helped to have included the link or the patch itself in
the various pings.

It would have also been helpful to note that this makes the callee side match
up with the caller side in calls.c:1247, initialize_argument_information.


r~

Re: [Patch, AArch64, ILP32] 1/5 Initial support - configury changes

[Andreas Schwab]

Yufeng Zhang <Yufeng.Zhang@arm.com> writes:

>         (ASM_SPEC): Update to also substitute -mabi.

You should check that the assembler actually understands that option.
Currently it is impossible to build an aarch64-linux compiler with
binutils from the binutils-2_23 branch.

Andreas.

-- 
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."

Re: [Patch, AArch64, ILP32] 1/5 Initial support - configury changes

[Yufeng Zhang]

On 09/18/13 11:21, Andreas Schwab wrote:
> Yufeng Zhang<Yufeng.Zhang@arm.com>  writes:
>
>>          (ASM_SPEC): Update to also substitute -mabi.
>
> You should check that the assembler actually understands that option.
> Currently it is impossible to build an aarch64-linux compiler with
> binutils from the binutils-2_23 branch.

Ah, I didn't think too much at then on the backward compatibility issue 
with binutils-2_23.  One potential solution can be to backport part of 
configury change from binutils trunk to 2_23.  Can I ask if there is any 
particular reason that you wouldn't like to build the trunk compiler 
with the trunk binutils?  Also since binutils 2.24 release shall not be 
far away, would you be happy to wait for that instead?

Thanks,
Yufeng

Re: [Patch, AArch64, ILP32] 1/5 Initial support - configury changes

[Andreas Schwab]

Yufeng Zhang <Yufeng.Zhang@arm.com> writes:

> Ah, I didn't think too much at then on the backward compatibility issue
> with binutils-2_23.  One potential solution can be to backport part of
> configury change from binutils trunk to 2_23.  Can I ask if there is any
> particular reason that you wouldn't like to build the trunk compiler with
> the trunk binutils?

You also get the error with a slightly older binutils trunk.  There
should be a configure check instead of failing to build.  It should
either require that the assembler is new enough, or drop the unknown
option (for aarch64-linux where multilibs are not enabled you don't need
it anyway).

Andreas.

-- 
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."